[PATCH 33/77] target/microblaze: Remove LOG_DIS

Also remove the related defines, DISAS_MB and DEBUG_DISAS. Rely on print_insn_microblaze. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 78 +-- 1 file changed, 1 insertion(+), 77 deletions(-) diff --git a/target/microblaze/translate.c b/tar

[PATCH 70/77] target/microblaze: Tidy do_rti, do_rtb, do_rte

Since cpu_msr is no longer a 64-bit quantity, we can simplify the arithmetic in these functions. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++- 1 file changed, 25 insertions(+), 40 deletions(-) diff --git a/target/microblaze/translat

[PATCH 62/77] target/microblaze: Try to keep imm and delay slot together

If the last insn on a page is imm, or a branch with delay slot, then end a tb early if this has not begun the tb. If it has begun the tb, then we can allow the tb to span two pages as if the imm plus its consumer, or branch plus delay, or imm plus branch plus delay, are a single insn. If the insn

[PATCH 34/77] target/microblaze: Ensure imm constant is always available

Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Signed-off-by: Richard Henderson --- target/m

QEMU | Pipeline #181919678 has failed for master | d1a2b51f

Your pipeline has failed. Project: QEMU ( https://gitlab.com/qemu-project/qemu ) Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master ) Commit: d1a2b51f ( https://gitlab.com/qemu-project/qemu/-/commit/d1a2b51f868d09ca8489ee9aee9c55632ed8fb92 ) Commit Message: Merge remote-tr

[PATCH 35/77] target/microblaze: Add decodetree infrastructure

The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 18 ++ target/microblaze/translate.c | 11 +-- target/microblaze/meson.build | 3 ++

[PATCH 69/77] target/microblaze: Convert dec_rts to decodetree

Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 5 target/microblaze/translate.c | 54 +++--- 2 files changed, 29 insertions(+), 30 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 21d08289f7.

[PATCH 32/77] target/microblaze: Remove empty D macros

This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Signed-off-by: Richard Henderson --- target/microblaze/helper.c| 11 --- target/microblaze/op_helper.c | 2 -- target/microblaz

[PATCH 55/77] target/microblaze: Move bimm to BIMM_FLAG

It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular signi

[PATCH 29/77] target/microblaze: Convert to translator_loop

Part two of conversion to the generic translator_loop. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++ 1 file changed, 149 insertions(+), 140 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c inde

[PATCH 50/77] target/microblaze: Replace MSR_EE_FLAG with MSR_EE

There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +++- target/microblaze/translate.c | 4 ++-- 2 files chang

[PATCH 25/77] target/microblaze: Split out MSR[C] to its own variable

Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 19 +++- linux-user/elfload.c

[PATCH 27/77] target/microblaze: Check singlestep_enabled in gen_goto_tb

Do not use goto_tb if we're single-stepping. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 53ca0bfb38..7d5b96c38b 100644 --- a/target

[PATCH 54/77] target/microblaze: Assert no overlap in flags making up tb_flags

Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 5

[PATCH 28/77] target/microblaze: Convert to DisasContextBase

Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 104 +- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/target/microb

[PATCH 52/77] target/microblaze: Fix cpu unwind for stackprot

Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 2 +- target/microblaze/op_helper.c | 6 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h ind

[PATCH 24/77] target/microblaze: Tidy mb_tcg_init

All of the tcg globals can be recorded in the same table. Drop the "r" prefix from "rpc" and "rmsr". Obviates the need for regnames[], which was incorrectly not const. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++ 1 file changed, 27

[PATCH 47/77] target/microblaze: Convert dec_fpu to decodetree

The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu == 2. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 19 + target/microblaze/translate.c | 152

[PATCH 37/77] target/microblaze: Convert dec_sub to decodetree

Use tcg_gen_add2_i32 for computing carry. This removes the last use of helper_carry, so remove that. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 1 - target/microblaze/insns.decode | 13 + target/microblaze/op_helper.c | 16 - target/microblaze/translate.c

[PATCH 23/77] target/microblaze: Rename env_* tcg variables to cpu_*

This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. It is standard for these file-scope globals to begin with cpu_*. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 54 +-- 1 file changed, 27 insertions(+), 27 deletions(-)

[PATCH 21/77] target/microblaze: Mark raise_exception as noreturn

This will allow tcg to remove any dead code that might follow an exception. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 2f8bdea22b..820711366d 100

[PATCH 44/77] target/microblaze: Convert dec_bit to decodetree

Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 + target/microblaze/translate.c | 148 + 2 files changed, 95 insertions(+), 73 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 18619e923

[PATCH 22/77] target/microblaze: Remove helper_debug and env->debug

This is not used, and seems redundant with -d cpu. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 - target/microblaze/helper.h| 1 - target/microblaze/op_helper.c | 23 --- target/microblaze/translate.c | 16 ++-- 4 files changed, 2

[PATCH 18/77] target/microblaze: Fix width of EDR

The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h

[PATCH 20/77] target/microblaze: Tidy raising of exceptions

Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the

[PATCH 43/77] target/microblaze: Unwind properly when raising divide-by-zero

Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 4 ++-- target/microblaze/op_helper.c | 23 --- 2 files changed, 14 inser

[PATCH 17/77] target/microblaze: Fix width of BTR

The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h

[PATCH 41/77] target/microblaze: Convert dec_mul to decodetree

Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 77 ++ 2 files changed, 37 insertions(+), 46 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 6b3cc9a182..

[PATCH 19/77] target/microblaze: Remove cpu_ear

Since cpu_ear is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 23 +++ 1 file changed, 15 insertions(+), 8 deletions(-) diff --g

[PATCH 16/77] target/microblaze: Fix width of FSR

The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.

[PATCH 36/77] target/microblaze: Convert dec_add to decodetree

Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 21 target/microblaze/translate.c | 185 ++

[PATCH 15/77] target/microblaze: Fix width of ESR

The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c| 2 +

[PATCH 14/77] target/microblaze: Fix width of MSR

The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c| 4 ++-- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 38 -

[PATCH 11/77] target/microblaze: Split out EDR from env->sregs

Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/elfload.c | 9 ++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/translat

[PATCH 31/77] target/microblaze: Remove DISAS_GNU

This is never used. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a90e56a17f..6757720776 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/

[PATCH 10/77] target/microblaze: Split out BTR from env->sregs

Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c| 4 ++-- target/microblaze/translate.c | 6

[PATCH 13/77] target/microblaze: Fix width of PC and BTARGET

The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/helper.c| 16 +++ target/microblaze/mmu.c

[PATCH 09/77] target/microblaze: Split out FSR from env->sregs

Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/op_hel

[PATCH 12/77] target/microblaze: Split the cpu_SR array

Similar to splitting the sregs array, this will allow further fixes and cleanups. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 106 +- 1 file changed, 65 insertions(+), 41 deletions(-) diff --git a/target/microblaze/translate.c b/target/mi

[PATCH 30/77] target/microblaze: Remove SIM_COMPAT

Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a9710d76d..a90e56a17f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/

[PATCH 07/77] target/microblaze: Split out EAR from env->sregs

Continue eliminating the sregs array in favor of individual members. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c| 6 +++--- target/microblaze/op_helper.c | 8 target/microblaze/translate

[PATCH 02/77] tests/tcg: Do not require FE_TOWARDZERO

This is optional in ISO C, and not all cpus provide it. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_convs.c | 2 ++ tests/tcg/multiarch/float_madds.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarc

[PATCH 26/77] target/microblaze: Use DISAS_NORETURN

Both exceptions and gen_goto_tb do not return. Use the official DISAS_NORETURN enumerator for this case. This eliminates all use of DISAS_TB_JUMP. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++-- 1 file changed, 7 insertions(+), 10 deletions(-) diff --

[PATCH 04/77] target/microblaze: Tidy gdbstub

Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 193 +++-

[PATCH 01/77] tests/tcg: Add microblaze to arches filter

Not attempting to use a single cross-compiler for both big-endian and little-endian at this time. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/configure.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index

[PATCH 06/77] target/microblaze: Split out MSR from env->sregs

Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 7 ++--- target/microblaze/cpu.c | 4 +-- target/microblaze/gdbstub.c | 4 +-- target/microblaze/helper.c

[PATCH 08/77] target/microblaze: Split out ESR from env->sregs

Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 6 +++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/h

[PATCH 05/77] target/microblaze: Split out PC from env->sregs

Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- linux-user/microblaze/cpu_loop.c | 12 +-- linux-user/microblaze/signal.c | 8 target/micro

[PATCH 00/77] target/microblaze improvements

Well, this is larger than I expected. I started off thinking conversion to decodetree would be quick, after I reviewed the mttcg patches last week. Then I realized that this could also use conversion to the generic translation loop. Then I realized that there were a number of bugs, and some ineff

[PATCH 03/77] tests/tcg: Do not require FE_* exception bits

Define anything that is missing as 0, so that flags & FE_FOO is false for any missing FOO. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_helpers.h | 17 + 1 file changed, 17 insertions(+) diff --git a/tests/tcg/multiarch/float_helpers.h b/tests

linux-user static build broken

Hi, since we have switched to meson, the statically linked binaries of qemu linux-user are broken: cd $OBJ $SRC/configure --static --target-list=m68k-linux-user make ./qemu-m68k Segmentation fault (core dumped) Program received signal SIGSEGV, Segmentation fault. 0x77bd6833 in __dcigette

[PATCH v2 1/4] configure: Use discovered make for in-source build

A recursive make is invoked if in-source build is used but $(MAKE) is the same as the one used in the original make invocation. Some platforms have preference to use gmake, or a make passed as an option to "configure". Honor the choice. Signed-off-by: Roman Bolshakov --- configure | 6 ++ 1

[PATCH v2 4/4] configure: Test if $make actually exists

configure doesn't detect if $make is installed on the build host. This is also helpful for hosts where an alias for make is used, i.e. configure would fail if gmake is not present on macOS. Reviewed-by: Daniel P. Berrangé Signed-off-by: Roman Bolshakov --- configure | 4 1 file changed, 4

[PATCH v2 3/4] configure: Prefer gmake on darwin

New meson/make build requires GNU make 3.82+ but macOS ships 3.81 even on Big Sur while homebrew provides GNU make 4.3 as 'gmake' in $PATH. With the change, 'make' switches over to gmake implicitly. Signed-off-by: Roman Bolshakov --- configure | 26 ++ 1 file changed, 26

[PATCH v2 0/4] Compatibility make fixes for meson

The set of changes addresses "Diagnose "make is too old" in configure (or in the makefile?)" from https://wiki.qemu.org/Features/Meson#Easy. It also provides cleaner backwards compatible build invocation on macOS. Changes since v1: - Added explicit error for partially-completed configure (Eric B.

[PATCH v2 2/4] Makefile: Require GNU make 3.82+

QEMU build fails with cryptic messages if make is too old: Makefile.ninja:2655: *** multiple target patterns. Stop. To avoid the confusion it's worth to fail the build right away and print a friendly error message. Reviewed-by: Daniel P. Berrangé Signed-off-by: Roman Bolshakov --- Makefile

Re: [PULL] nvme updates

On Sun, Aug 23, 2020 at 02:56:12PM +0100, Peter Maydell wrote: > On Wed, 19 Aug 2020 at 20:23, Keith Busch wrote: > > > > We're trying our first nvme pull request from a dedicated development > > tree containing various fixes, cleanups, spec compliance, and welcoming > > Klaus Jensen to maintainin

Re: [PULL 0/1] Socket next patches

On Tue, 25 Aug 2020 at 11:53, Daniel P. Berrangé wrote: > > The following changes since commit 44423107e7b5731ef40c5c8632a5bad8b49d0838: > > Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into > staging (2020-08-24 19:55:23 +0100) > > are available in the Git repository at:

Re: [PATCH 20/22] target/arm: Implement new VFP fp16 insn VMOVX

On 8/24/20 7:29 AM, Peter Maydell wrote: > The fp16 extension includes a new instruction VMOVX, which copies the > upper 16 bits of a 32-bit source VFP register into the lower 16 > bits of the destination and zeroes the high half of the destination. > Implement it. > > Signed-off-by: Peter Maydell

[PATCH v3 70/74] [automated] Use OBJECT_DECLARE_TYPE where possible (pass 2)

Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: this is a new p

[Bug 1892604] Re: qemu-system-arm: ../hw/usb/hcd-dwc2.c:666: dwc2_glbreg_read: Assertion `addr <= GINTSTS2' failed.

What happens if you add "dwc_otg.fiq_fsm_enable=0" to the kernel command line? This is noted as a requirement in the changelog at https://wiki.qemu.org/ChangeLog/5.1 -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchp

[PATCH v3 65/74] [automated] Move QOM typedefs and add missing includes (pass 2)

Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') whic

Re: [PATCH 0/1] qcow2: Skip copy-on-write when allocating a zero cluster

On Tue, Aug 25, 2020 at 07:18:19PM +0200, Alberto Garcia wrote: > On Tue 25 Aug 2020 06:54:15 PM CEST, Brian Foster wrote: > > If I compare this 5m fio test between XFS and ext4 on a couple of my > > systems (with either no prealloc or full file prealloc), I end up seeing > > ext4 run slightly fast

[PATCH v3 73/74] crypto: use QOM macros for declaration/definition of secret types

From: Daniel P. Berrangé This introduces the use of the OBJECT_DEFINE and OBJECT_DECLARE macro families in the secret types, in order to eliminate boilerplate code. Signed-off-by: Daniel P. Berrangé Message-Id: <20200723181410.3145233-4-berra...@redhat.com> [ehabkost: rebase, update to pass add

[PATCH v3 69/74] [automated] Use OBJECT_DECLARE_TYPE where possible

Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes

[PATCH v3 68/74] [semi-automated] Use DECLARE_*CHECKER* when possible (--force mode)

Separate run of the TypeCheckMacro converter using the --force flag, for the cases where typedefs weren't found in the same header nor in typedefs.h. Generated initially using: $ ./scripts/codeconverter/converter.py --force -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Then eac

Re: [PATCH 19/22] target/arm: Implement new VFP fp16 insn VINS

On 8/24/20 7:29 AM, Peter Maydell wrote: > The fp16 extension includes a new instruction VINS, which copies the > lower 16 bits of a 32-bit source VFP register into the upper 16 bits > of the destination. Implement it. > > Signed-off-by: Peter Maydell > --- > target/arm/vfp-uncond.decode | 3

[PATCH v3 59/74] qom: TYPE_INFO macro

Provide a TYPE_INFO macro that can be used to register a TypeInfo struct declaratively. This will allow QOM type registration to be 100% declarative. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes v1 -> v2: none --- include/qom/object.h | 15

[PATCH v3 60/74] codeconverter: script for automating QOM code cleanups

This started as a simple script that scanned for regular expressions, but became more and more complex when exceptions to the rules were found. I don't know if this should be maintained in the QEMU source tree long term (maybe it can be reused for other code transformations that Coccinelle can't h

[PATCH v3 63/74] [automated] Use TYPE_INFO macro (pass 2)

Generated using: $ ./scripts/codeconverter/converter.py -i --passes=2 \ --pattern=TypeRegisterCall,TypeInitMacro $(git grep -l TypeInfo -- '*.[ch]') One notable difference is that files declaring multiple types will now have multiple separate __construtor__ functions declared, instead of one

[PATCH v3 58/74] qom: Make type checker functions accept const pointers

The existing type check macros all unconditionally drop const qualifiers from their arguments. Keep this behavior in the macros generated by DECLARE_*CHECKER* by now. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: * Remo

[PATCH v3 55/74] qom: provide convenient macros for declaring and defining types

From: Daniel P. Berrangé When creating new QOM types, there is a lot of boilerplate code that must be repeated using a standard pattern. This is tedious to write and liable to suffer from subtle inconsistencies. Thus it would benefit from some simple automation. QOM was loosely inspired by GLib'

[PATCH v3 61/74] [automated] Delete duplicate QOM typedefs

Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMDuplicatedTypedefs $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes v1 -> v2: none --- Cc: "Daniel P. Berrangé" Cc: qemu-devel@nongnu.o

[PATCH v3 47/74] rdma: Rename INTERFACE_RDMA_PROVIDER_CLASS macro

Rename the macro to be consistent with RDMA_PROVIDER and RDMA_PROVIDER_GET_CLASS. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Yuval Shaia Cc: Marcel Apfelbaum Cc: qemu-devel@nongnu

[PATCH v3 57/74] qom: DECLARE_*_CHECKERS macros

Sometimes the typedefs are buried inside another header, but we want to benefit from the automatic definition of type cast functions. Introduce macros that will let type checkers be defined when typedefs are already available. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- C

Re: [PATCH 22/22] target/arm: Enable FP16 in '-cpu max'

On 8/24/20 7:29 AM, Peter Maydell wrote: > Set the MVFR1 ID register FPHP and SIMDHP fields to indicate > that our "-cpu max" has v8.2-FP16. > > TODO: this patch needs to go at the end of the series. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.c | 3 ++- > target/arm/cpu64.c | 10

[PATCH v3 56/74] qom: Allow class type name to be specified in OBJECT_DECLARE*

Many QOM types don't follow the Type/TypeClass pattern on the instance/struct names. Let the class struct name be specified in the OBJECT_DECLARE* macros. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes v1 -> v2: none --- include/qom/object.h

[PATCH v3 53/74] rx: Move typedef RXCPU to cpu-qom.h

Move the typedef closer to the QOM type checking macros. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Yoshinori Sato Cc: qemu-devel@nongnu.org --- target/rx/cpu-qom.h | 1 + target/r

Re: [PATCH 21/22] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers

On 8/24/20 7:29 AM, Peter Maydell wrote: > Implement the VFP fp16 variant of VMOV that transfers a 16-bit > value between a general purpose register and a VFP register. > > Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later > only we have no need to replicate the old "updates CPS

[PATCH v3 38/74] rocker: Move QOM macros to header

This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes series v1 -> v2: new patch in series v2 Cc: Jiri Pirko Cc: Jason Wang Cc: qemu-devel@nongnu.org --- hw/net/rocker/rocker.h | 6 +-

[PATCH v3 72/74] [automated] Remove redundant instance_size/class_size fields

This will remove instance_size/class_size fields from TypeInfo variables when the value is exactly the same as the one in the parent class. Generated by: $ ./scripts/codeconverter/converter.py -i \ --pattern=RedundantTypeSizes $(git grep -l TypeInfo -- '*.[ch]') Signed-off-by: Eduardo Habkos

[PATCH v3 52/74] rx: Rename QOM type check macros

Currently we have a RXCPU typedef and a RXCPU type checking macro, but OBJECT_DECLARE* would transform the RXCPU macro into a function, and the function name would conflict with the typedef name. Rename the RXCPU* QOM type check macros to RX_CPU*, so we will avoid the conflict and make the macro n

[PATCH v3 35/74] virtio-serial-bus: Move QOM macros to header

This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes series v1 -> v2: new patch in series v2 Cc: Laurent Vivier Cc: Amit Shah Cc: "Michael S. Tsirkin" Cc: "Marc-André Lureau" Cc: Paolo

[PATCH v3 74/74] crypto: use QOM macros for declaration/definition of TLS creds types

From: Daniel P. Berrangé This introduces the use of the OBJECT_DEFINE and OBJECT_DECLARE macro families in the TLS creds types, in order to eliminate boilerplate code. Signed-off-by: Daniel P. Berrangé Message-Id: <20200723181410.3145233-5-berra...@redhat.com> [ehabkost: rebase, update to pass

[PATCH v3 50/74] migration: Rename class type checking macros

Rename the macros to make them consistent with the MIGRATION_OBJ macro name. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Juan Quintela Cc: "Dr. David Alan Gilbert" Cc: qemu-devel@n

[PATCH v3 54/74] qom: make object_ref/unref use a void * instead of Object *.

From: Daniel P. Berrangé The object_ref/unref methods are intended for use with any subclass of the base Object. Using "Object *" in the signature is not adding any meaningful level of type safety, since callers simply use "OBJECT(ptr)" and this expands to an unchecked cast "(Object *)". By usin

[PATCH v3 34/74] vmbus: Move QOM macros to vmbus.h

Move all declarations related to TYPE_VMBUS to the same place in vmbus.h. This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes series v1 -> v2: new patch in series v2 Cc: qemu-devel@nongnu

[PATCH v3 48/74] s390-virtio-ccw: Rename S390_MACHINE_CLASS macro

Rename it to be consistent with S390_CCW_MACHINE and TYPE_S390_CCW_MACHINE. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Richard Henderson Cc: David Hildenbrand Cc: Cornelia Huck C

[PATCH v3 31/74] i8257: Move QOM macro to header

Move the I8257 macro to i8257.h, close to the TYPE_I8257 define. This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes series v1 -> v2: new patch in series v2 Cc: "Michael S. Tsirkin" Cc:

[PATCH v3 51/74] arm: Fix typo in AARCH64_CPU_GET_CLASS definition

There's a typo in the type name of AARCH64_CPU_GET_CLASS. This was never detected because the macro is not used by any code. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Peter Maydell Cc: qemu-...@nongnu.org Cc: qemu-devel@nongnu.org --- tar

[PATCH v3 71/74] [automated] Use OBJECT_DECLARE_SIMPLE_TYPE when possible

Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=ObjectDeclareType $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes v1 -> v2: none --- Cc: "Marc-André Lureau" Cc: "Daniel P. Berrangé" Cc

[PATCH v3 45/74] mos6522: Rename QOM macros

Rename the MOS6522_DEVICE_CLASS and MOS6522_DEVICE_GET_CLASS macros to be consistent with the TYPE_MOS6522 and MOS6522 macros. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Laurent Viv

[PATCH v3 49/74] swim: Rename struct SWIM to Swim

Currently we have a SWIM typedef and a SWIM type checking macro, but OBJECT_DECLARE* would transform the SWIM macro into a function, and the function name would conflict with the SWIM typedef name. Rename the struct and typedef to "Swim". This will make future conversion to OBJECT_DECLARE* easier.

[PATCH v3 29/74] vhost-user-gpu: Move QOM macro to header

Move the VHOST_USER_GPU type checking macro to virtio-gpu.h, close to the TYPE_VHOST_USER_GPU #define. This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Gerd Hoffmann Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes serie

[PATCH v3 44/74] imx_ccm: Rename IMX_GET_CLASS macro

Rename it to IMX_CCM_GET_CLASS to be consistent with the existing IMX_CCM and IXM_CCM_CLASS macro. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch added to series v3 --- Cc: Peter Chubb Cc: Peter Maydell Cc: qem

[PATCH v3 39/74] pxa2xx: Move QOM macros to header

This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes series v1 -> v2: new patch in series v2 Cc: Andrzej Zaborowski Cc: Peter Maydell Cc: qemu-...@nongnu.org Cc: qemu-devel@nongnu.org ---

[PATCH v3 67/74] [automated] Use DECLARE_*CHECKER* macros (pass 2)

$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: this is a new patch added in series v3 The script was re-run after rebase and after additional patches were added to this series. Th

[PATCH v3 25/74] armsse: Rename QOM macros to avoid conflicts

Rename TYPE_ARMSSE to TYPE_ARM_SSE, and ARMSSE*() type checking macros to ARM_SSE*(). This will avoid a future conflict between an ARM_SSE() type checking macro and the ARMSSE typedef name. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: none Changes series

[PATCH v3 43/74] nubus: Rename class type checking macros

Rename the existing class type checking macros to be consistent with the type name and instance type checking macro. Use a NUBUS_MACFB prefix instead of MACFB_NUBUS. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost --- Changes series v2 -> v3: new patch

[PATCH v3 27/74] spapr: Move typedef SpaprMachineState to spapr.h

Move the typedef from spapr_irq.h to spapr.h, and use "struct SpaprMachineState" in the spapr_*.h headers (to avoid circular header dependencies). This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v2 -> v3: non

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