On Fri, Nov 27, 2020 at 4:29 PM Stefano Garzarella wrote:
>
> On Fri, Nov 20, 2020 at 07:51:01PM +0100, Eugenio Pérez wrote:
> >Since vhost does not need to access it, it has no sense to keep it
> >mapped.
> >
> >Signed-off-by: Eugenio Pérez
> >---
> > hw/virtio/vhost.c | 1 +
> > 1 file
On 11/30/20 3:42 AM, Alexander Graf wrote:
>
> On 26.11.20 23:18, Eduardo Habkost wrote:
>> On Thu, Nov 26, 2020 at 10:50:15PM +0100, Alexander Graf wrote:
>>> When kicking another vCPU, we get an OS function that explicitly does that
>>> for us
>>> on Apple Silicon. That works better than the
On Monday, November 30, 2020 1:40 AM, Peter Maydell wrote:
> The function nios2_check_interrupts)() looks only at CPU-internal state; it
> belongs in target/nios2, not hw/nios2. Move it into the same file as its only
> caller, so it can just be local to that file.
>
> This removes the only
On Monday, November 30, 2020 1:40 AM, Peter Maydell wrote:
> The Nios2 architecture supports two different interrupt controller
> options:
>
> * The IIC (Internal Interrupt Controller) is part of the CPU itself;
>it has 32 IRQ input lines and no NMI support. Interrupt status is
>queried
v2:
Drop some package from dockerfile to make docker image more light.
v1:
Add build-system-opensuse jobs and opensuse-leap.docker dockerfile.
Use openSUSE Leap 15.2 container image in the gitlab-CI.
Signed-off-by: Cho, Yu-Chen
---
.gitlab-ci.d/containers.yml | 5 ++
From: Xuzhou Cheng
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, during which CS
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its
From: Bin Meng
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng
---
hw/ssi/imx_spi.c | 4 ++--
include/hw/ssi/imx_spi.h | 5 -
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/imx_spi.c
在 2020/11/30 上午6:09, Philippe Mathieu-Daudé 写道:
Hi Huacai,
On 6/9/20 6:28 PM, Aleksandar Markovic wrote:
From: Huacai Chen
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the
Patchew URL: https://patchew.org/QEMU/20201130030723.78326-1-ag...@csgraf.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201130030723.78326-1-ag...@csgraf.de
Subject: [PATCH v2 0/8] hvf: Implement Apple Silicon
Now that we have all logic in place that we need to handle Hypervisor.framework
on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
can build it.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Fix build on 32bit arm
---
meson.build| 11 ++-
With Apple Silicon available to the masses, it's a good time to add support
for driving its virtualization extensions from QEMU.
This patch adds all necessary architecture specific code to get basic VMs
working. It's still pretty raw, but definitely functional.
Known limitations:
- Vtimer
In macOS 11, QEMU only gets access to Hypervisor.framework if it has the
respective entitlement. Add an entitlement template and automatically self
sign and apply the entitlement in the build.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Make safe to ctrl-C
---
We will need more than a single field for hvf going forward. To keep
the global vcpu struct uncluttered, let's allocate a special hvf vcpu
struct, similar to how hax does it.
Signed-off-by: Alexander Graf
---
accel/hvf/hvf-cpus.c| 8 +-
include/hw/core/cpu.h | 3 +-
Now that Apple Silicon is widely available, people are obviously excited
to try and run virtualized workloads on them, such as Linux and Windows.
This patch set implements a fully functional version to get the ball
going on that. With this applied, I can successfully run both Linux and
Windows as
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's move common code out
into its own accel directory.
Signed-off-by: Alexander Graf
---
MAINTAINERS
In Hypervisor.framework, we just pass PSCI calls straight on to the QEMU
emulation
of it. That means, if TCG is compatible with PSCI 0.2, so are we. Let's
transpose
that fact in code too.
Signed-off-by: Alexander Graf
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git
When clearing internal state of a CPU, we should also make sure that HVF
knows about it and can push the new values down to vcpu state.
Make sure that with HVF enabled, we tell it that it should synchronize
CPU state on next entry after a reset.
This fixes PSCI handling, because now newly pushed
In the hvf init function, we prepare a signal mask for SIG_IPI, but
then fail to set it. This seems to work by chance on some systems,
where SIGUSR2 is already unmasked by default. It fails however on
ARM Big Sur.
So let's set the signal mask as intended.
Signed-off-by: Alexander Graf
---
On 2020/11/27 下午10:49, Mauro Matteo Cascella wrote:
On Fri, Nov 27, 2020 at 6:21 AM Jason Wang wrote:
On 2020/11/24 上午5:30, Mauro Matteo Cascella wrote:
On Thu, Nov 19, 2020 at 6:57 AM Jason Wang wrote:
On 2020/11/18 下午4:53, Mauro Matteo Cascella wrote:
On Wed, Nov 18, 2020 at 4:56 AM
On 2020/11/27 下午2:06, Yuri Benditovich wrote:
> After some experiments we can see that stripping of debug sections
> reduces the size of
> ELF from ~45K to ~20K (we tried to strip more but the libbpf
fails to
> load it, libbpf needs BTF and symbols)
> So I suggest to
From: Bin Meng
SST flashes require a dummy byte after the address bits.
Signed-off-by: Bin Meng
---
hw/block/m25p80.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 483925f..9b36762 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@
On 27.11.20 17:47, Peter Maydell wrote:
On Fri, 27 Nov 2020 at 16:38, Peter Maydell wrote:
Having looked a bit more closely at some of the relevant target/arm
code, I think the best approach is going to be that in virt.c
we just check the PARange ID register field (probably via
a convenience
centralize the calls to cpu->accel_cpu_interface
Signed-off-by: Claudio Fontana
---
hw/core/cpu.c | 9 +
include/hw/core/cpu.h | 6 ++
target/i386/cpu.c | 9 ++---
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index
On 2020/11/27 下午11:45, Philippe Mathieu-Daudé wrote:
Ensure no packet bigger then NET_BUFSIZE is queued via
qemu_net_queue_append*() by adding assertions.
Signed-off-by: Philippe Mathieu-Daudé
---
net/queue.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/net/queue.c b/net/queue.c
Signed-off-by: Claudio Fontana
---
MAINTAINERS| 2 +-
accel/accel-common.c | 50 ++
accel/{accel.c => accel-softmmu.c} | 27 ++--
accel/accel-user.c | 24 ++
accel/meson.build
cpu_exec_realizefn and cpu_exec_unrealizefn are
TCG-only stuff, related to accel/tcg/cpu-exec.c
Introduce cpu_accel_realize to call it (for tcg-only),
and to call the other accel-specific arch-specific
realize functions if any are registered.
The only part that is not TCG-specific is common code
On 26.11.20 23:18, Eduardo Habkost wrote:
On Thu, Nov 26, 2020 at 10:50:15PM +0100, Alexander Graf wrote:
When kicking another vCPU, we get an OS function that explicitly does that for
us
on Apple Silicon. That works better than the current signaling logic, let's make
use of it there.
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
accel/tcg/cputlb.c | 6 +++---
accel/tcg/user-exec.c | 6 +++---
include/hw/core/cpu.h | 9 -
include/hw/core/tcg-cpu-ops.h | 12
target/alpha/cpu.c | 2 +-
centralize the registration of the cpus.c module
accelerator operations in accel/accel-softmmu.c
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 3 ++-
accel/accel-common.c | 11 +
accel/accel-softmmu.c| 43 +++---
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
hw/core/cpu.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 576fa1d7ba..994a12cb35 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -199,15 +199,6 @@ static bool
On 2020/11/27 下午11:45, Philippe Mathieu-Daudé wrote:
Do not allow qemu_send_packet*() and qemu_net_queue_send()
functions to accept packets bigger then NET_BUFSIZE.
Signed-off-by: Philippe Mathieu-Daudé
---
We have to put a limit somewhere. NET_BUFSIZE is defined as:
/* Maximum GSO packet
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
accel/tcg/cpu-exec.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 890b88861a..64cba89356 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -482,7
Signed-off-by: Claudio Fontana
---
target/i386/cpu.c | 33 --
target/i386/cpu.h | 97 ++---
target/i386/helper-tcg.h | 112 ++
target/i386/helper.c | 23 ---
target/i386/meson.build
i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.ccpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/cpu.cKVM x86 AccelCPUClass
hvf/cpu.cHVF x86 AccelCPUClass
tcg/cpu.cTCG x86
From: Eduardo Habkost
This will let us simplify the code that initializes CPU class
methods, when we move cpu_exec_*() to a separate struct.
Signed-off-by: Eduardo Habkost
---
accel/tcg/cpu-exec.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Claudio Fontana
---
target/i386/meson.build | 14 +-
target/i386/{ => tcg}/bpt_helper.c | 0
target/i386/{ => tcg}/cc_helper.c | 0
target/i386/{ => tcg}/excp_helper.c | 0
target/i386/{ => tcg}/fpu_helper.c | 0
target/i386/{ => tcg}/int_helper.c
add a new optional interface to CPUClass,
which allows accelerators to extend the CPUClass
with additional accelerator-specific initializations.
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 1 +
accel/accel-common.c| 46 -
Signed-off-by: Claudio Fontana
---
target/i386/cpu-dump.c | 538
target/i386/cpu.h | 1 +
target/i386/helper.c| 514 --
target/i386/meson.build | 1 +
4 files changed, 540 insertions(+), 514 deletions(-)
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
accel/tcg/cpu-exec.c | 4 ++--
include/hw/core/cpu.h | 8
include/hw/core/tcg-cpu-ops.h | 14 +++---
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/hppa/cpu.c
Signed-off-by: Claudio Fontana
Reviewed-by: Roman Bolshakov
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 448593c904..f53f2678d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -444,7 +444,6 @@ M: Cameron Esfahani
M: Roman Bolshakov
W:
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
accel/tcg/cpu-exec.c | 4 ++--
include/hw/core/cpu.h | 2 --
include/hw/core/tcg-cpu-ops.h | 2 ++
target/arm/cpu.c | 2 +-
target/i386/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
From: Eduardo Habkost
Move invocation of CPUClass.cpu_exec_*() to separate helpers,
to make it easier to refactor that code later.
Signed-off-by: Eduardo Habkost
---
accel/tcg/cpu-exec.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
accel/tcg/cpu-exec.c| 12 ++--
include/hw/core/cpu.h | 6 --
include/hw/core/tcg-cpu-ops.h | 9 +
target/alpha/cpu.c | 3 ++-
target/arm/cpu.c| 2 +-
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 2 +-
hw/i386/fw_cfg.c | 2 +-
hw/i386/intel_iommu.c| 2 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvm/clock.c | 2 +-
hw/i386/microvm.c
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 2 +-
target/i386/{ => hax}/hax-all.c | 0
target/i386/{ => hax}/hax-cpus.c | 0
target/i386/{ => hax}/hax-cpus.h | 0
target/i386/{ => hax}/hax-i386.h | 6 +++---
target/i386/{ =>
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 5 +
target/i386/meson.build | 5 +
target/i386/whpx/meson.build | 4
target/i386/{ => whpx}/whp-dispatch.h | 0
target/i386/{ => whpx}/whpx-all.c | 0
target/i386/{ =>
Hi all, this is v7 of the i386 cleanup,
with the most interesting patches at the end.
v6 -> v7: integrate TCGCpuOperations, refactored cpu_exec_realizefn
* integrate TCGCpuOperations (Eduardo)
Taken some refactoring from Eduardo for Tcg-only operations on
CPUClass.
* refactored
We found that the hypervisor virtual-machine load and store instructions,
included HLVX/HLV/HSV, couldn't access guest userspace memory.
In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow:
"As usual when V=1, two-stage address translation is applied, and
the HS-level sstatus.SUM is
Public bug reported:
When running in a chroot with riscv32 (on x86_64; qemu git master as of
today):
The following short program forks; the child immediately returns with
exit(42). The parent checks for the return value - and obtains 40!
gcc-10.2
===
Hi Huacai,
On 6/9/20 6:28 PM, Aleksandar Markovic wrote:
> From: Huacai Chen
>
> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
> R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
> Loongson-3A R4 is the newest and its ISA is almost the superset of
Public bug reported:
Guest display resolution cannot be changed with certain virtual graphics
card (-vga) and interface (-display) combinations.
For example, resolution changing doesn't work with the following QEMU
start commands, it resets to the default resolution immediately:
QXL with SDL
On 28.11.2020 00:49, Peter Xu wrote:
On Thu, Nov 26, 2020 at 06:17:31PM +0300, Andrey Gruzdev wrote:
In this particular implementation the same single migration
thread is responsible for both normal linear dirty page
migration and procesing UFFD page fault events.
Processing write faults
Public bug reported:
When listening to music (e.g. with VLC) or watching Youtube on the
guest, there's lots of stuttering and crackling in the sound.
Tested with the following QEMU start commands:
qemu-system-x86_64 -enable-kvm -m 6G -cpu host -smp 3 -cdrom
Instead of making the ROM blob name something like:
phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf
make it a little more self-explanatory for people who don't know
ELF format details:
/home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf ELF program header
segment 0
In rom_check_and_register_reset() we detect overlaps by looking at
whether the ROM blob we're currently examining is in the same address
space and starts before the previous ROM blob ends. (This works
because the ROM list is kept sorted in order by AddressSpace and then
by address.)
Instead of
In rom_check_and_register_reset() we report to the user if there is
a "ROM region overlap". This has a couple of problems:
* the reported information is not very easy to intepret
* the function just prints the overlap to stderr (and relies on
its single callsite in vl.c to do an
Currently the load_elf code assembles the ROM blob name into a
local 128 byte fixed-size array. Use g_strdup_printf() instead so
that we don't truncate the pathname if it happens to be long.
(This matters mostly for monitor 'info roms' output and for the
error messages if ROM blobs overlap.)
(This was inspired by a conversation on IRC with a user.)
We report an error if we detect that there's an overlap in guest
memory between two ROM blobs, but the warning is pretty opaque.
Currently it looks like this:
rom: requested regions overlap (rom dtb. free=0x8000,
Public bug reported:
Sometimes mouse goes completely crazy and starts jumping around the
guest desktop by itself and becomes completely unusable.
This does not happen on every boot, only sometimes. It may be caused by
some input combination but I haven't yet found any specific cause. It
happens
On 28.11.2020 00:04, Peter Xu wrote:
On Thu, Nov 26, 2020 at 06:17:30PM +0300, Andrey Gruzdev wrote:
Implemented support for the whole RAM block memory
protection/un-protection. Introduced higher level
ram_write_tracking_start() and ram_write_tracking_stop()
to start/stop tracking guest memory
Public bug reported:
Keyboard keys get "stuck" quite often, on certain Linux guests at least,
and start repeating themselves until another key is pressed. This is
especially noticeable with key combinations like Ctrl+V for pasting.
When it happens, you get the pasted text and
Hi Alex,
On Wed, Nov 25, 2020 at 3:17 AM Alex Chen wrote:
> On 2020/11/24 23:29, Peter Maydell wrote:
> > On Tue, 24 Nov 2020 at 12:15, Alex Chen wrote:
> >>
> >> Hi everyone，
> >>
> >> Who can help me merge this patch into the master branch? This patch may
> be need for qemu-5.2
> >
> > This
The function nios2_check_interrupts)() looks only at CPU-internal
state; it belongs in target/nios2, not hw/nios2. Move it into the
same file as its only caller, so it can just be local to that file.
This removes the only remaining code from cpu_pic.c, so we can delete
that file entirely.
The Nios2 architecture supports two different interrupt controller
options:
* The IIC (Internal Interrupt Controller) is part of the CPU itself;
it has 32 IRQ input lines and no NMI support. Interrupt status is
queried and controlled via the CPU's ipending and istatus
registers.
*
In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask
operations to set the appropriate bit in the ipending register.
Signed-off-by: Peter Maydell
---
In patch 1 I left the code for this identical to the old
code from nios2_iic.c for clarity of that refactoring,
but deposit32()
The Nios2 architecture supports two different interrupt controller
options:
* The IIC (Internal Interrupt Controller) is part of the CPU itself;
it has 32 IRQ input lines and no NMI support. Interrupt status is
queried and controlled via the CPU's ipending and istatus
registers.
*
On 11/23/20 2:44 PM, Philippe Mathieu-Daudé wrote:
> Extract 600 lines of the the Toshiba TX79 multimedia
> translation routines to 'vendor-tx-mmi_translate.c.inc'.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 568 +
>
Public bug reported:
Hi,
Finding this one a bit odd, but I am loading a driver (kext) in a macOS
guest ... and it works, on the first VM (domain) startup after a full /
clean host OS boot (or reboot). However, if I even reboot the guest OS,
then the driver load fails => can be "corrected" by a
Public bug reported:
Hi,
I am seeing (consistently = always), USB Passthrough for my Logitech
Keyboard and Mouse ... they don't work / no response on domain (VM)
startup. After a reset of the VM they then work - but why are they
"dead" on initial startup of the VM? Is this a known issue?
On Fri, Nov 27, 2020 at 10:51:27PM +, Peter Maydell wrote:
> The openrisc code uses an old style of interrupt handling, where a
> separate standalone set of qemu_irqs invoke a function
> openrisc_pic_cpu_handler() which signals the interrupt to the CPU
> proper by directly calling
On Fri, Nov 27, 2020 at 10:51:26PM +, Peter Maydell wrote:
> We're about to refactor the OpenRISC pic_cpu code in a way that means
> that just grabbing the whole qemu_irq[] array of inbound IRQs for a
> CPU won't be possible any more. Abstract out a function for "return
> the qemu_irq for IRQ
On Fri, Nov 27, 2020 at 10:51:25PM +, Peter Maydell wrote:
> openrisc_sim_net_init() attempts to connect the IRQ line from the
> ethernet device to both CPUs in an SMP configuration by simply caling
> sysbus_connect_irq() for it twice. This doesn't work, because the
> second connection simply
On 11/27/20 9:43 PM, Eduardo Habkost wrote:
> On Fri, Nov 27, 2020 at 08:47:00PM +0100, Claudio Fontana wrote:
>> On 11/27/20 8:04 PM, Eduardo Habkost wrote:
> [...]
>>> Maybe we should rename CPUClass.synchronize_from_tb to
>>> CPUClass.tcg_synchronize_from_tb? Maybe we should have a
>>
>>
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