[PATCH v2 4/4] block/iscsi: Use lock guard macros

Replace manual lock()/unlock() calls with lock guard macros (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD) in block/iscsi. Signed-off-by: Gan Qixin --- Cc: Kevin Wolf Cc: Paolo Bonzini Cc: Markus Armbruster --- block/iscsi.c | 50 -- 1 file changed, 24

[PATCH v2 1/4] block/accounting: Use lock guard macros

Replace manual lock()/unlock() calls with lock guard macros (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD) in block/accounting. Signed-off-by: Gan Qixin Reviewed-by: Paolo Bonzini --- Cc: Kevin Wolf Cc: Markus Armbruster --- block/accounting.c | 32 +++- 1 file changed, 15

[PATCH v2 3/4] block/throttle-groups: Use lock guard macros

Replace manual lock()/unlock() calls with lock guard macros (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD) in block/throttle-groups. Signed-off-by: Gan Qixin --- Cc: Kevin Wolf Cc: Paolo Bonzini Cc: Markus Armbruster --- block/throttle-groups.c | 48 - 1 file c

[PATCH v2 0/4] Use lock guard macros in block

v1->v2: -Patch1: Add Paolo Bonzini reviewed tag and delete the .c suffix in the commit message. -Patch2: Add Paolo Bonzini reviewed tag and delete the .c suffix in the commit message. -Patch3: Delete the .c suffix in the commit. Changes suggested by Kevin Wolf: Fix wrong indentat

[PATCH v2 2/4] block/curl: Use lock guard macros

Replace manual lock()/unlock() calls with lock guard macros (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD) in block/curl. Signed-off-by: Gan Qixin Reviewed-by: Paolo Bonzini --- Cc: Kevin Wolf Cc: Markus Armbruster --- block/curl.c | 28 ++-- 1 file changed, 14 insertions(+),

[Bug 1906608] [NEW] [Feature request]For some ehci controller, qemu should implement using portsc[26-27] to detect the speed of device.

Public bug reported: for some ehci controller ,for example ehci controller on fsl_imx6,it using portsc[26-27] to decide a full speed device or high speed device was connected, hub-ehci.c should set the portsc[26-27] to return the right speed. line:1001 in hub-ehci.c if (dev && dev->attach

RE: [PATCH 4/4] block/iscsi.c: Use lock guard macros

> -Original Message- > From: Kevin Wolf [mailto:kw...@redhat.com] > Sent: Wednesday, December 2, 2020 7:12 PM > To: ganqixin > Cc: qemu-devel@nongnu.org; qemu-triv...@nongnu.org; > pbonz...@redhat.com; mre...@redhat.com; stefa...@redhat.com; > dnbrd...@gmail.com; Zhanghailiang ; > Chenqun

RE: [PATCH v2 01/12] pc-dimm: put it into the 'storage' category

> -Original Message- > From: Pankaj Gupta [mailto:pankaj.gupta.li...@gmail.com] > Sent: Monday, November 30, 2020 6:19 PM > To: ganqixin > Cc: Qemu Developers ; qemu-triv...@nongnu.org; > Chenqun (kuhn) ; th...@redhat.com; > Zhanghailiang ; Michael S . Tsirkin > > Subject: Re: [PATCH v2 0

Re: [PATCH 00/18] qapi/qom: QAPIfy object-add

Hi, > It would be much nicer to do the wrapper the other way round, i.e. > setting properties before the device is realized would update a > configuration struct and realize would then call .create() with that > struct. To me, this sounds much harder, though also a more useful state. Well, in s

Re: [PATCH] tests/acceptance: fix timeout for vm.wait

On 02.12.2020 18:22, John Snow wrote: On 12/2/20 1:31 AM, Pavel Dovgalyuk wrote: This patch adds timeout parameter to vm.wait() calls, because the default value is just 30 seconds, and tests may last for more time. This doesn't sound right -- the timeout isn't meant to be for the entire d

Re: [PATCH v1 1/1] security-process: update process information

+-- On Wed, 2 Dec 2020, Daniel P. Berrangé wrote --+ | > +- If issue is found to be less severe, an upstream public bug (or an | > + issue) will be created immediately. | | No need to repeat "or an issue". I think it would read more clearly as | |- If the severity of the issue is suf

Re: [PATCH v1 1/1] security-process: update process information

Hello Dan, Stefano, +-- On Wed, 2 Dec 2020, Stefano Stabellini wrote --+ | On Wed, 2 Dec 2020, Daniel P. Berrangé wrote: | > > + any third parties, including Xen Security Project, without your prior | > > + permission. | > | > Why this explicit note about the Xen project ? What if we decide

Re: [PATCH v3 07/10] arm: Add Hypervisor.framework build target

On Wed, Dec 02, 2020 at 08:04:05PM +0100, Alexander Graf wrote: > Now that we have all logic in place that we need to handle > Hypervisor.framework > on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we > can build it. > > Signed-off-by: Alexander Graf > > --- > > v1 -

Re: [PATCH v3 06/10] hvf: Add Apple Silicon support

On Wed, Dec 02, 2020 at 08:04:04PM +0100, Alexander Graf wrote: > With Apple Silicon available to the masses, it's a good time to add support > for driving its virtualization extensions from QEMU. > > This patch adds all necessary architecture specific code to get basic VMs > working. It's still p

Re: [PATCH v1 1/1] security-process: update process information

Hello Dan, +-- On Wed, 2 Dec 2020, Daniel P. Berrangé wrote --+ | > +- If issue is found to be less severe, an upstream public bug (or an | > + issue) will be created immediately. | | No need to repeat "or an issue". I think it would read more clearly as | |- If the severity of t

Re: [PATCH v1 1/1] security-process: update process information

+-- On Wed, 2 Dec 2020, Philippe Mathieu-Daudé wrote --+ | Maybe: | | 0) **Acknowledge reception** |- A non-automated response email is sent to acknowledge the | reception of the request. | This is the starting date for the maximum **60 days** required | to

[Bug 1906516] Re: [RISCV] sfence.vma need to end the translation block

** Description changed: QEMU emulator version 5.0.0 sfence.vma will flush the tlb, so after this instruction, the translation block should be end. The following code will only work in single step mode: ``` relocate: - li a0, OFFSET +  li a0, OFFSET - la t0, 1f - ad

Re: [PATCH 0/9] target/mips: Simplify MSA TCG logic

在 2020/12/3 上午2:44, Philippe Mathieu-Daudé 写道: I converted MSA opcodes to decodetree. To keep the series small I split it in 2, this is the non-decodetree specific patches (so non-decodetree experts can review it ;) ). First we stop using env->insn_flags to check for MSAi presence, then we re

Re: [PATCH v2] gitlab-ci.yml: Add openSUSE Leap 15.2 for gitlab CI/CD

On Mon, 2020-11-30 at 10:14 +0100, Philippe Mathieu-Daudé wrote: > On 11/30/20 5:26 AM, Cho, Yu-Chen wrote: > > v2: > > Drop some package from dockerfile to make docker image more light. > > > > v1: > > Add build-system-opensuse jobs and opensuse-leap.docker dockerfile. > > Use openSUSE Leap 15.2

Re: [PATCH 0/9] target/mips: Simplify MSA TCG logic

在 2020/12/3 上午2:44, Philippe Mathieu-Daudé 写道: I converted MSA opcodes to decodetree. To keep the series small I split it in 2, this is the non-decodetree specific patches (so non-decodetree experts can review it ;) ). First we stop using env->insn_flags to check for MSAi presence, then we re

Re: [PATCH v1 1/1] security-process: update process information

On Wed, 2 Dec 2020, Daniel P. Berrangé wrote: > On Mon, Nov 30, 2020 at 07:19:07PM +0530, P J P wrote: > > From: Prasad J Pandit > > > > We are about to introduce a qemu-security mailing list to report > > and triage QEMU security issues. > > > > Update the QEMU security process web page with ne

Re: [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E

Hi, Philippe, On Wed, Dec 2, 2020 at 5:16 PM Philippe Mathieu-Daudé wrote: > > On 12/2/20 2:01 AM, chen huacai wrote: > > Hi, Philippe, > > > > On Wed, Dec 2, 2020 at 3:31 AM Philippe Mathieu-Daudé > > wrote: > >> > >> Userland ELF binaries using Longsoon SIMD instructions have the > >> HWCAP_L

Re: [PATCH] scsi: allow user to set werror as report

Ping? This is a fix patch which has been reviewed, whose tree should it go via? Thanks Zihao On 2020/11/3 22:03, Zihao Chang wrote: > > > On 2020/11/3 18:52, Fam Zheng wrote: >> On Tue, 2020-11-03 at 14:12 +0800, Zihao Chang wrote: >>> 'enospc' is the default for -drive, but qemu allows user to

[Bug 1906156] Re: Host OS Reboot Required, for Guest kext to Load (Fully)

Sorry for the delay on updating this - but pulling my hair out (and I'm short enough of that already ... LOL). I can't get Ubuntu to let me run the custom qemu executable. Really is looking like apparmor. Fighting with that, but struggling to have it let me run it :-(. Thanks. -- You received th

Re: [PATCH v10 0/9] pci_expander_brdige:acpi: Support pxb-pcie for ARM

Hi Michael, On 2020/12/2 17:53, Michael S. Tsirkin wrote: > On Thu, Nov 19, 2020 at 09:48:32AM +0800, Jiahui Cen wrote: >> Changes with v9 >> v9->v10: >> Refactor patch2 to drop useless macros and variables. >> Split patch2 into two patches. > > I tagged this for after the release. To help make s

Re: [PATCH for-6.0] hw/ppc: Do not re-read the clock on pre_save if doing savevm

On Wed, Dec 02, 2020 at 06:28:26PM +0100, Greg Kurz wrote: > A guest with enough RAM, eg. 128G, is likely to detect savevm downtime > and to complain about stalled CPUs. This happens because we re-read > the timebase just before migrating it and we thus don't account for > all the time between VM s

Re: [PATCH] xive: Add more trace events

On Fri, Nov 27, 2020 at 02:36:54PM +0100, Cédric Le Goater wrote: > These are useful to understand IRQ requests from the OS. > > Signed-off-by: Cédric Le Goater > --- > > David, Feel free to merge with the previous. Done, thanks. > > hw/intc/spapr_xive.c | 6 ++ > hw/intc/spapr_xive_

Re: [PATCH v3 05/10] hvf: arm: Mark CPU as dirty on reset

On Wed, Dec 02, 2020 at 08:04:03PM +0100, Alexander Graf wrote: > When clearing internal state of a CPU, we should also make sure that HVF > knows about it and can push the new values down to vcpu state. > I'm sorry if I'm asking something dumb. But isn't cpu_synchronize_all_post_reset() is suppo

Re: [PATCH v3 04/10] arm: Set PSCI to 0.2 for HVF

On Wed, Dec 02, 2020 at 08:04:02PM +0100, Alexander Graf wrote: > In Hypervisor.framework, we just pass PSCI calls straight on to the QEMU > emulation > of it. That means, if TCG is compatible with PSCI 0.2, so are we. Let's > transpose > that fact in code too. > > Signed-off-by: Alexander Graf

Re: [PATCH v3 03/10] hvf: Introduce hvf vcpu struct

On Wed, Dec 02, 2020 at 08:04:01PM +0100, Alexander Graf wrote: > We will need more than a single field for hvf going forward. To keep > the global vcpu struct uncluttered, let's allocate a special hvf vcpu > struct, similar to how hax does it. > Reviewed-by: Roman Bolshakov Tested-by: Roman Bol

Re: [PATCH v3 02/10] hvf: Move common code out

On Wed, Dec 02, 2020 at 08:04:00PM +0100, Alexander Graf wrote: > Until now, Hypervisor.framework has only been available on x86_64 systems. > With Apple Silicon shipping now, it extends its reach to aarch64. To > prepare for support for multiple architectures, let's move common code out > into its

Re: [PATCH for-6.0 v2 1/3] spapr: Improve naming of some vCPU id related items

On Mon, Nov 30, 2020 at 05:52:56PM +0100, Greg Kurz wrote: > The machine tells the IC backend the number of vCPU ids it will be > exposed to, in order to: > - fill the "ibm,interrupt-server-ranges" property in the DT (XICS) > - size the VP block used by the in-kernel chip (XICS-on-XIVE, XIVE) > >

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

On Wed, Dec 2, 2020 at 3:26 PM Frank Yang wrote: > > > > On Wed, Dec 2, 2020 at 2:57 PM Alexander Graf wrote: >> >> >> On 02.12.20 23:46, Frank Yang wrote: >> >> >> >> On Wed, Dec 2, 2020 at 2:28 PM Alexander Graf wrote: >>> >>> >>> On 02.12.20 23:19, Frank Yang wrote: >>> >>> >>> From downstrea

Re: [PATCH v3 01/10] hvf: Add hypervisor entitlement to output binaries

On Wed, Dec 02, 2020 at 08:03:59PM +0100, Alexander Graf wrote: > In macOS 11, QEMU only gets access to Hypervisor.framework if it has the > respective entitlement. Add an entitlement template and automatically self > sign and apply the entitlement in the build. > > Signed-off-by: Alexander Graf

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

On Wed, Dec 2, 2020 at 2:57 PM Alexander Graf wrote: > > > On 02.12.20 23:46, Frank Yang wrote: > > > > On Wed, Dec 2, 2020 at 2:28 PM Alexander Graf wrote: >> >> >> On 02.12.20 23:19, Frank Yang wrote: >> >> >> From downstream: >> https://android-review.googlesource.com/c/platform/external/qemu

Re: [PATCH v1 4/9] vfio: Support for RamDiscardMgr in the !vIOMMU case

On Thu, 19 Nov 2020 16:39:13 +0100 David Hildenbrand wrote: > Implement support for RamDiscardMgr, to prepare for virtio-mem > support. Instead of mapping the whole memory section, we only map > "populated" parts and update the mapping when notified about > discarding/population of memory via the

Re: [PATCH v1 1/9] memory: Introduce RamDiscardMgr for RAM memory regions

On Thu, 19 Nov 2020 16:39:10 +0100 David Hildenbrand wrote: > We have some special RAM memory regions (managed by virtio-mem), whereby > the guest agreed to only use selected memory ranges. "unused" parts are > discarded so they won't consume memory - to logically unplug these memory > ranges. Be

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

On Wed, Dec 2, 2020 at 2:57 PM Alexander Graf wrote: > > On 02.12.20 23:46, Frank Yang wrote: > > > > On Wed, Dec 2, 2020 at 2:28 PM Alexander Graf wrote: > >> >> On 02.12.20 23:19, Frank Yang wrote: >> >> >> From downstream: >> https://android-review.googlesource.com/c/platform/external/qemu/+/

Re: [PATCH] hw/block: m25p80: Fix fast read for SST flashes

On Wed, Dec 2, 2020 at 3:09 PM Bin Meng wrote: > > Hi Alistair, > > On Thu, Dec 3, 2020 at 3:52 AM Alistair Francis wrote: > > > > On Sun, Nov 29, 2020 at 6:55 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > SST flashes require a dummy byte after the address bits. > > > > > > Signed-o

Re: [PATCH] hw/block: m25p80: Fix fast read for SST flashes

Hi Alistair, On Thu, Dec 3, 2020 at 3:52 AM Alistair Francis wrote: > > On Sun, Nov 29, 2020 at 6:55 PM Bin Meng wrote: > > > > From: Bin Meng > > > > SST flashes require a dummy byte after the address bits. > > > > Signed-off-by: Bin Meng > > I couldn't find a datasheet that says this... But

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

On 02.12.20 23:46, Frank Yang wrote: On Wed, Dec 2, 2020 at 2:28 PM Alexander Graf > wrote: On 02.12.20 23:19, Frank Yang wrote: From downstream: https://android-review.googlesource.com/c/platform/external/qemu/+/1515002

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

On Wed, Dec 2, 2020 at 2:28 PM Alexander Graf wrote: > > On 02.12.20 23:19, Frank Yang wrote: > > > From downstream: > https://android-review.googlesource.com/c/platform/external/qemu/+/1515002 > > Based on v3 of Alexander Graf's patches > > https://patchew.org/QEMU/20201202190408.2041-1-ag...@cs

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

On 02.12.20 23:19, Frank Yang wrote: From downstream: https://android-review.googlesource.com/c/platform/external/qemu/+/1515002 Based on v3 of Alexander Graf's patches https://patchew.org/QEMU/20201202190408.2041

Re: [PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

We've gotten the Android Emulator snapshots working again on M1 and noticed a time warp issue where the stopwatch app would, on a snapshot load, resume including the time the emulator wasn't running. This seems to fix it. Now we have snapshots mostly working (though file backed ram is a bit busted,

[PATCH v1 1/1] hvf: arm: Properly sync guest time on migration

>From downstream: https://android-review.googlesource.com/c/platform/external/qemu/+/1515002 Based on v3 of Alexander Graf's patches https://patchew.org/QEMU/20201202190408.2041-1-ag...@csgraf.de We need to adjust CNTVOFF_EL2 so that time doesnt warp. Even though we can set separate CNTVOFF_EL2

[PATCH-for-5.2? 0/1] Acceptance tests: bump Fedora to 32

I believe this may be a candidate for "right now" because the code changes here simply sync with external infrastructure changes, that is, the retirement of Fedora 31 from the official repository locations). The following jobs contain a validation of this bump: - https://gitlab.com/cleber.gnu/qe

[PATCH-for-5.2? 1/1] Acceptance tests: bump Fedora to 32

Currently in use Fedora 31 has been moved out of the standard download locations that are supported by the functionality provided by avocado.utils.vmimage. So right now, the boot_linux.py tests will get canceled by not being able to find those specific images. Ideally, this would be bumped to ver

Re: [PATCH v3 3/3] arm/hvf: Add a WFI handler

On Wed, Dec 2, 2020 at 10:49 AM Alexander Graf wrote: > > > On 02.12.20 05:44, Peter Collingbourne wrote: > > Sleep on WFI until the VTIMER is due but allow ourselves to be woken > > up on IPI. > > > > Signed-off-by: Peter Collingbourne > > --- > > v3: > > - move the simplified locking to a separ

Re: [DISCUSSION] How to set properties of non-pluggable devices?

Hello, On Wed, 2 Dec 2020, Doug Evans wrote: Hi. Suppose I want to set a property of a non-pluggable device that cannot be set after the device has been realized (e.g., I can't use qmp to set the property after QEMU has started). Being non-pluggable means I can't use "-device foo,bar=baz" on th

Re: [PATCH] docs: set CONFDIR when running sphinx

On Wed, Dec 02, 2020 at 10:05:50AM +0100, Paolo Bonzini wrote: > On 01/12/20 19:37, marcandre.lur...@redhat.com wrote: > > From: Marc-André Lureau > > > > The default configuration path /etc/qemu can be overriden with configure > > options, and the generated documentation used to reflect it. > >

Re: [PATCH] hw/block: m25p80: Fix fast read for SST flashes

On Sun, Nov 29, 2020 at 6:55 PM Bin Meng wrote: > > From: Bin Meng > > SST flashes require a dummy byte after the address bits. > > Signed-off-by: Bin Meng I couldn't find a datasheet that says this... But the actual code change looks fine, so: Acked-by: Alistair Francis Alistair > --- > >

Re: [PATCH 00/18] qapi/qom: QAPIfy object-add

On Wed, Dec 02, 2020 at 06:35:06PM +0100, Kevin Wolf wrote: > Am 02.12.2020 um 17:05 hat Eduardo Habkost geschrieben: > > > > Looks nice as end goal. Then, these are a few questions I would > > > > have about the transition plan: > > > > > > > > Would it require changing both device implementatio

Re: [PATCH v3 00/10] hvf: Implement Apple Silicon Support

Patchew URL: https://patchew.org/QEMU/20201202190408.2041-1-ag...@csgraf.de/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201202190408.2041-1-ag...@csgraf.de Subject: [PATCH v3 00/10] hvf: Implement Apple Silicon Su

Re: [PATCH v2 1/1] Fix to show vfio migration stat in migration status

On Wed, 2 Dec 2020 00:43:14 +0530 Kirti Wankhede wrote: > Header file where CONFIG_VFIO is defined is not included in migration.c > file. > > Moved populate_vfio_info() to hw/vfio/common.c file. Added its stub in > stubs/vfio.c file. Updated header files and meson file accordingly. > > Fixes: 3

[PATCH v3 06/10] hvf: Add Apple Silicon support

With Apple Silicon available to the masses, it's a good time to add support for driving its virtualization extensions from QEMU. This patch adds all necessary architecture specific code to get basic VMs working. It's still pretty raw, but definitely functional. Known limitations: - Vtimer ackn

[PATCH v3 10/10] hvf: arm: Implement -cpu host

Now that we have working system register sync, we push more target CPU properties into the virtual machine. That might be useful in some situations, but is not the typical case that users want. So let's add a -cpu host option that allows them to explicitly pass all CPU capabilities of their host C

[PATCH v3 07/10] arm: Add Hypervisor.framework build target

Now that we have all logic in place that we need to handle Hypervisor.framework on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we can build it. Signed-off-by: Alexander Graf --- v1 -> v2: - Fix build on 32bit arm --- meson.build| 11 ++- t

[PATCH v3 08/10] arm/hvf: Add a WFI handler

From: Peter Collingbourne Sleep on WFI until the VTIMER is due but allow ourselves to be woken up on IPI. Signed-off-by: Peter Collingbourne [agraf: Remove unused 'set' variable, always advance PC on WFX trap] Signed-off-by: Alexander Graf --- accel/hvf/hvf-cpus.c | 5 ++-- include/sysem

[PATCH v3 04/10] arm: Set PSCI to 0.2 for HVF

In Hypervisor.framework, we just pass PSCI calls straight on to the QEMU emulation of it. That means, if TCG is compatible with PSCI 0.2, so are we. Let's transpose that fact in code too. Signed-off-by: Alexander Graf --- target/arm/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a

[PATCH v3 05/10] hvf: arm: Mark CPU as dirty on reset

When clearing internal state of a CPU, we should also make sure that HVF knows about it and can push the new values down to vcpu state. Make sure that with HVF enabled, we tell it that it should synchronize CPU state on next entry after a reset. This fixes PSCI handling, because now newly pushed

Re: [RFC PATCH] configure: add --without-default-features

Alex Bennée writes: > By default QEMU enables a lot of features if it can probe and find the > support libraries. It also enables a bunch of features by default. > This patch adds the ability to build --without-default-features which > can be paired with a --without-default-devices for a barely

[PATCH v3 02/10] hvf: Move common code out

Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's move common code out into its own accel directory. Signed-off-by: Alexander Graf --- MAINTAINERS

[PATCH v3 03/10] hvf: Introduce hvf vcpu struct

We will need more than a single field for hvf going forward. To keep the global vcpu struct uncluttered, let's allocate a special hvf vcpu struct, similar to how hax does it. Signed-off-by: Alexander Graf --- accel/hvf/hvf-cpus.c| 8 +- include/hw/core/cpu.h | 3 +- include/sys

[PATCH v3 09/10] hvf: arm: Add support for GICv3

We currently only support GICv2 emulation. To also support GICv3, we will need to pass a few system registers into their respective handler functions. This patch adds handling for all of the required system registers, so that we can run with more than 8 vCPUs. Signed-off-by: Alexander Graf ---

[PATCH v3 00/10] hvf: Implement Apple Silicon Support

Now that Apple Silicon is widely available, people are obviously excited to try and run virtualized workloads on them, such as Linux and Windows. This patch set implements a fully functional version to get the ball going on that. With this applied, I can successfully run both Linux and Windows as

[PATCH v3 01/10] hvf: Add hypervisor entitlement to output binaries

In macOS 11, QEMU only gets access to Hypervisor.framework if it has the respective entitlement. Add an entitlement template and automatically self sign and apply the entitlement in the build. Signed-off-by: Alexander Graf --- v1 -> v2: - Make safe to ctrl-C --- accel/hvf/entitlements.plist

[DISCUSSION] How to set properties of non-pluggable devices?

Hi. Suppose I want to set a property of a non-pluggable device that cannot be set after the device has been realized (e.g., I can't use qmp to set the property after QEMU has started). Being non-pluggable means I can't use "-device foo,bar=baz" on the command line. [But I can use "-device foo,help

Re: [PATCH v3 3/3] arm/hvf: Add a WFI handler

On 02.12.20 05:44, Peter Collingbourne wrote: Sleep on WFI until the VTIMER is due but allow ourselves to be woken up on IPI. Signed-off-by: Peter Collingbourne --- v3: - move the simplified locking to a separate patch - spin on sleep <2ms v2: - simplify locking further - wait indefinitely o

[PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods

The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 57 - 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/target/mips/translate.c b/ta

[PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init()

Extract the logic initialization of the MSA registers from the generic initialization. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 35 --- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/mips/translate.c b/target/mips

[PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers

Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. While this might be the case for CPU implementing MSA, this makes QEMU code incoh

[PATCH 4/9] target/mips: Simplify MSA TCG logic

Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception.

[PATCH 5/9] target/mips: Remove now unused ASE_MSA definition

We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 1 - target/mips/translate_init.c.inc | 8 2 files changed, 4 insertions(+), 5 deletions(-) diff --

[PATCH 3/9] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA

MSA presence is expressed by the MSAP bit of CP0_Config3. We don't need to check anything else. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index f882ac1580c..

[PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()

In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD]-> BxZ(true) Signed-off-by: Philippe Mathieu-Daudé --- target/mips/transl

[PATCH 2/9] target/mips: Simplify msa_reset()

Call msa_reset() inconditionally, but only reset the MSA registers if MSA is implemented. Signed-off-by: Philippe Mathieu-Daudé --- Maybe not very useful. --- target/mips/translate.c | 5 + target/mips/translate_init.c.inc | 4 2 files changed, 5 insertions(+), 4 deletions(-)

[PATCH 1/9] target/mips: Introduce ase_msa_available() helper

Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 6 ++ target/mips/kvm.c | 12 ++-- target/mips/translate.c | 8 +++--

[PATCH 0/9] target/mips: Simplify MSA TCG logic

I converted MSA opcodes to decodetree. To keep the series small I split it in 2, this is the non-decodetree specific patches (so non-decodetree experts can review it ;) ). First we stop using env->insn_flags to check for MSAi presence, then we restrict TCG functions to DisasContext*. Based-on: <2

[PATCH v13 09/10] stream: skip filters when writing backing file name to QCOW2 header

Avoid writing a filter JSON file name and a filter format name to QCOW2 image when the backing file is being changed after the block stream job. It can occur due to a concurrent commit job on the same backing chain. A user is still able to assign the 'backing-file' parameter for a block-stream job

[PATCH v13 10/10] block: apply COR-filter to block-stream jobs

This patch completes the series with the COR-filter applied to block-stream operations. Adding the filter makes it possible for copied regions to be discarded in backing files during the block-stream job, what will reduce the disk overuse. The COR-filter insertion incurs changes in the test case 24

[PATCH v13 03/10] copy-on-read: add filter drop function

Provide API for the COR-filter removal. Also, drop the filter child permissions for an inactive state when the filter node is being removed. To insert the filter, the block generic layer function bdrv_insert_node() can be used. The new function bdrv_cor_filter_drop() may be considered as an interme

[PATCH v13 01/10] copy-on-read: support preadv/pwritev_part functions

Add support for the recently introduced functions bdrv_co_preadv_part() and bdrv_co_pwritev_part() to the COR-filter driver. Signed-off-by: Andrey Shinkevich Reviewed-by: Vladimir Sementsov-Ogievskiy --- block/copy-on-read.c | 28 1 file changed, 16 insertions(+), 1

[PATCH v13 05/10] qapi: create BlockdevOptionsCor structure for COR driver

Create the BlockdevOptionsCor structure for COR driver specific options splitting it off form the BlockdevOptionsGenericFormat. The only option 'bottom' node in the structure denotes an image file that limits the COR operations in the backing chain. We are going to use the COR-filter for a block-st

[PATCH v13 00/10] Apply COR-filter to the block-stream permanently

The previous version 12 was discussed in the email thread: Message-Id: <1603390423-980205-1-git-send-email-andrey.shinkev...@virtuozzo.com> v13: 02: The bdrv_remove_node() was dropped. 05: Three patches with fixes were merged into one. 06: Minor changes based on Vladimir's suggestions. 08:

[PATCH v13 07/10] block: include supported_read_flags into BDS structure

Add the new member supported_read_flags to the BlockDriverState structure. It will control the flags set for copy-on-read operations. Make the block generic layer evaluate supported read flags before they go to a block driver. Suggested-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Andrey Shink

[PATCH v13 02/10] block: add API function to insert a node

Provide API for insertion a node to backing chain. Suggested-by: Max Reitz Signed-off-by: Andrey Shinkevich Reviewed-by: Vladimir Sementsov-Ogievskiy --- block.c | 25 + include/block/block.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/block.c

[PATCH v13 06/10] iotests: add #310 to test bottom node in COR driver

The test case #310 is similar to #216 by Max Reitz. The difference is that the test #310 involves a bottom node to the COR filter driver. Signed-off-by: Andrey Shinkevich Reviewed-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/310 | 114 +

[PATCH v13 04/10] qapi: add filter-node-name to block-stream

Provide the possibility to pass the 'filter-node-name' parameter to the block-stream job as it is done for the commit block job. Signed-off-by: Andrey Shinkevich Reviewed-by: Vladimir Sementsov-Ogievskiy --- block/monitor/block-hmp-cmds.c | 4 ++-- block/stream.c | 4 +++- block

[PATCH v13 08/10] copy-on-read: skip non-guest reads if no copy needed

If the flag BDRV_REQ_PREFETCH was set, skip idling read/write operations in COR-driver. It can be taken into account for the COR-algorithms optimization. That check is being made during the block stream job by the moment. Add the BDRV_REQ_PREFETCH flag to the supported_read_flags of the COR-filter

Re: [PATCH v12 14/14] block: apply COR-filter to block-stream jobs

On 27.10.2020 21:24, Andrey Shinkevich wrote: On 27.10.2020 20:57, Vladimir Sementsov-Ogievskiy wrote: 27.10.2020 20:48, Andrey Shinkevich wrote: On 27.10.2020 19:13, Vladimir Sementsov-Ogievskiy wrote: 22.10.2020 21:13, Andrey Shinkevich wrote: This patch completes the series with the CO

Re: [Bug 1906463] [NEW] "-device help" does not report all devices

On Wed, Dec 2, 2020 at 9:41 AM Peter Maydell wrote: > On Wed, 2 Dec 2020 at 16:51, Doug Evans wrote: > > > > Btw, if I may ask another dumb question, I get this: > > > > @ruffy:build-arm$ ./qemu-system-arm -M virt -monitor stdio > > Unable to init server: Could not connect: Connection refused >

Re: Plans to bring QMP 'x-blockdev-reopen' out of experimental?

Am 02.12.2020 um 17:40 hat Alberto Garcia geschrieben: > On Wed 02 Dec 2020 05:28:08 PM CET, Kevin Wolf wrote: > > >> So x-blockdev-reopen sees that we want to replace the current > >> bs->file ("hd0-file") with a new one ("throttle0"). The problem here > >> is that throttle0 has hd0-file as its c

[Bug 1906536] Re: Unable to set SVE VL to 1024 bits or above since 7b6a2198

Yes, we should by default do what the Linux kernel does, but we should also provide a mechanism for allowing guest software to use a higher vector length than that kernel default. On a real kernel you can do that by either setting the /proc/sys/abi/sve_default_vector_length, or by having process A

Re: [PATCH] linux-user/elfload: Fix handling of pure BSS segments

On Wed, 25 Nov 2020 at 09:39, Alex Bennée wrote: > How hairy is the generation of these binaries? If it's all doable with > standard gcc/ldd command lines it would be useful to add them as a > tcg/multiarch test case. Rather than using C it might be simpler just to create a failing binary by-hand

[Bug 1906536] Re: Unable to set SVE VL to 1024 bits or above since 7b6a2198

Hi Philippe, I'm aware of the prctl workaround. It seems to me that this is clearly a regression in functionality. Prior to the change, I could test any executable with any vector length without having to modify the executable. Now I have to insert a prctl to test with 1024 or 2048-bit SVE vector

Re: [Bug 1906463] [NEW] "-device help" does not report all devices

On Wed, 2 Dec 2020 at 16:51, Doug Evans wrote: > > Btw, if I may ask another dumb question, I get this: > > @ruffy:build-arm$ ./qemu-system-arm -M virt -monitor stdio > Unable to init server: Could not connect: Connection refused > QEMU 5.1.93 monitor - type 'help' for more information > (qemu) gt

[Bug 1906536] Re: Unable to set SVE VL to 1024 bits or above since 7b6a2198

** Changed in: qemu Status: Invalid => New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1906536 Title: Unable to set SVE VL to 1024 bits or above since 7b6a2198 Status in QEMU: New Bug

Re: [PATCH 1/6] migration: Add multi-thread compress method

* Zeyu Jin (jinz...@huawei.com) wrote: > On 2020/11/30 16:35, Markus Armbruster wrote: > > Zeyu Jin writes: > > > >> On 2020/11/27 17:48, Markus Armbruster wrote: > >>> Kevin, Max, suggest to skip right to Qcow2CompressionType. > >>> > >>> Zeyu Jin writes: > >>> > A multi-thread compress me

Re: [PATCH 00/18] qapi/qom: QAPIfy object-add

Am 02.12.2020 um 17:05 hat Eduardo Habkost geschrieben: > > > Looks nice as end goal. Then, these are a few questions I would > > > have about the transition plan: > > > > > > Would it require changing both device implementation and device > > > users in lockstep? Should we have a compatibility

[PATCH for-6.0] hw/ppc: Do not re-read the clock on pre_save if doing savevm

A guest with enough RAM, eg. 128G, is likely to detect savevm downtime and to complain about stalled CPUs. This happens because we re-read the timebase just before migrating it and we thus don't account for all the time between VM stop and pre-save. A very similar situation was already addressed f

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