Loongson is next step in the "MIPS decodetree conversion" epic.
Start with the simplest extension.
The diffstat addition comes from the TCG functions expanded.
The code is easier to review now.
IMO this is also a good template to show how easy a decodetree
conversion can be (and how nice the
On 1/12/21 11:01 AM, Philippe Mathieu-Daudé wrote:
> Trivial patches to sanitize MIPS CPU definitions.
>
> Based-on: mips-next
>
> Philippe Mathieu-Daudé (3):
> target/mips: Remove CPU_R5900 definition
> target/mips: Remove CPU_NANOMIPS32 definition
> target/mips: Remove vendor specific
On 1/12/21 12:45 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> This adds handling for the SCR_EL3.EEL2 bit.
>
> Signed-off-by: Rémi Denis-Courmont
The patch title seems to have gone awry.
> @@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode
> }
>
On Tue, 12 Jan 2021 at 21:27, Taylor Simpson wrote:
>
> Signed-off-by: Taylor Simpson
What's the motivation for adding this test? Did we have
a bug we fixed which this would be the regression test for?
Some other reason why it seems like a good test case?
This is the sort of thing that it's
Signed-off-by: Taylor Simpson
---
tests/tcg/multiarch/testthread.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/tests/tcg/multiarch/testthread.c b/tests/tcg/multiarch/testthread.c
index 810ba5d..0da1f61 100644
--- a/tests/tcg/multiarch/testthread.c
+++
'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11
15:15:35 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210112-1
for you to fetch changes up to 1ff5a063d60c7737de11465516331b8ca8700865
[CCing John, Wainer]
On Fri, Jan 08, 2021 at 05:51:41PM -0500, Daniele Buono wrote:
> I had a similar issue in the past with the acceptance tests.
> Some VMs send UTF-8 output in their console and the acceptance test
> script would bail out if the locale was not UTF-8.
>
> I sent a patch on the
On 1/11/21 6:47 AM, Stefan Hajnoczi wrote:
Dear QEMU, KVM, and rust-vmm community,
QEMU will apply for Google Summer of Code
(https://summerofcode.withgoogle.com/) again this year. This internship
program offers paid, 10-week, remote work internships for
contributing to open source. QEMU can
On Tue, Jan 12, 2021 at 07:41:56PM +0100, Philippe Mathieu-Daudé wrote:
> Some ISA use a dot in their opcodes. Allow the decodetree
> script to process them. The dot is replaced by an underscore
> in the generated code.
Will something break if we just use underscores instead of dots
in the input
When checking whether there is a live gdb connection, code shouldn't
use 'gdbserver_state.init' as that value is set when the
gdbserver_state structure is initialized in init_gdbserver_state, not
when the gdb socket has a valid connection.
I've created two new functions to manage the gdb
There are two cases that need to be accounted for when compiling QEMU
for MinGW32:
1) A standalone distribution, where QEMU is self contained and
extracted by the user, such as a user would download from the QEMU
website. In this case, all the QEMU executable files should be
rooted in
On 1/12/21 12:45 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to
> the upper (64-bit) EL. With Secure EL2 support, we can no longer assume
> that that is always EL3, so make room for the value to be
On 1/12/21 12:45 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
Reviewed-by: Richard Henderson
r~
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h| 5 -
target/mips/cpu-defs.c.inc | 12 +++-
2 files
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h| 3 ---
target/mips/cpu-defs.c.inc | 4 ++--
2
Commit 823f2897bdd ("target/mips: Disable R5900 support")
removed the single CPU using the CPU_R5900 definition.
As it is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/mips/mips-defs.h
Trivial patches to sanitize MIPS CPU definitions.
Based-on: mips-next
Philippe Mathieu-Daudé (3):
target/mips: Remove CPU_R5900 definition
target/mips: Remove CPU_NANOMIPS32 definition
target/mips: Remove vendor specific CPU definitions
target/mips/mips-defs.h| 9 -
Alex Bennée writes:
> It would be better to wrap the test in a function (static bool
> is_connected()?) so the semantic meaning is clear in the code and we can
> fix things in one place if needed.
That makes good sense to me.
> How exactly did you create the segfault? Just starting with -s and
On 1/12/21 8:41 AM, Philippe Mathieu-Daudé wrote:
> Some ISA use a dot in their opcodes. Allow the decodetree
> script to process them. The dot is replaced by an underscore
> in the generated code.
Given that you then have to remember to use '_' on the C side, what advantage
does this give?
r~
On Tue, 12 Jan 2021, Stefan Hajnoczi wrote:
It is possible to repeat the --trace option to specify multiple
patterns. This may be preferrable to users who do not want to create a
file with a list of patterns.
Suggested-by: BALATON Zoltan
Signed-off-by: Stefan Hajnoczi
---
On 1/12/21 5:40 PM, Thomas Huth wrote:
> Let's gather the POWER-related tests in a separate file.
>
> Signed-off-by: Thomas Huth
> ---
> MAINTAINERS| 1 +
> tests/acceptance/boot_linux_console.py | 19 --
> tests/acceptance/machine_ppc.py| 34
Taylor Simpson writes:
> ---
> tests/tcg/multiarch/testthread.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/tests/tcg/multiarch/testthread.c
> b/tests/tcg/multiarch/testthread.c
> index 810ba5d..b30b4b5 100644
> --- a/tests/tcg/multiarch/testthread.c
> +++
Le 12/01/2021 à 12:29, Philippe Mathieu-Daudé a écrit :
> Replace fprintf() calls by qemu_log_mask(LOG_GUEST_ERROR).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/ahci.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>
Le 12/01/2021 à 12:27, Gan Qixin a écrit :
> When running device-introspect-test, a memory leak occurred in the
> mos6522_init
> function, this patch use timer_free() in the finalize function to fix it.
>
> ASAN shows memory leak stack:
>
> Direct leak of 96 byte(s) in 2 object(s) allocated
Le 12/01/2021 à 12:27, Gan Qixin a écrit :
> When running device-introspect-test, a memory leak occurred in the pl031_init
> function, this patch use timer_free() in the finalize function to fix it.
>
> ASAN shows memory leak stack:
>
> Direct leak of 48 byte(s) in 1 object(s) allocated from:
>
Le 26/11/2020 à 07:57, Alex Chen a écrit :
> Free the 'sioc' when the qio_channel_socket_connect_sync() fails.
>
> Reported-by: Euler Robot
> Signed-off-by: Alex Chen
> ---
> ui/vnc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/ui/vnc.c b/ui/vnc.c
> index 49235056f7..dae56e9493
Le 10/12/2020 à 18:28, Philippe Mathieu-Daudé a écrit :
> Replace I/O write error reported with error_report() by
> qemu_log_mask(GUEST_ERROR) which allow filtering.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/virtio/virtio-pci.c | 6 --
> 1 file changed, 4 insertions(+), 2
On 12/01/21 18:04, Dave wrote:
Thanks Paola,
We are still in testing and that's the only thing we've uncovered so far
with the new 5.2.0. I will post if the ops guys find anything else.
Hmm, that's weird though. The path to the default bridge helper is
relocated:
net/tap.c:helper
Le 26/11/2020 à 07:57, Alex Chen a écrit :
> Free the 'sioc' when the qio_channel_socket_connect_sync() fails.
>
> Reported-by: Euler Robot
> Signed-off-by: Alex Chen
> ---
> ui/vnc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/ui/vnc.c b/ui/vnc.c
> index 49235056f7..dae56e9493
Taylor Simpson writes:
> This series adds support for the Hexagon processor with Linux user support
>
> See patch 02/33 Hexagon README for detailed information.
>
> This series assumes int128_or() is implemented.
> https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg06004.html
>
> The
Hello,
For you information using a Debian 10 distribution resolve the problem.
I don't know why but using a CentOS 7 distribution cause this error
"qemu:handle_cpu_signal received signal outside vCPU context @
pc=0x82f29b0e"
You can close this case if you want, but still I guess it's
On 1/12/21 1:48 PM, Bin Meng wrote:
> On Tue, Jan 12, 2021 at 6:46 PM Peter Maydell
> wrote:
>>
>> On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote:
>>>
>>> From: Bin Meng
>>>
>>> The endianness of data exchange between tx and rx fifo is incorrect.
>>> Earlier bytes are supposed to show up on MSB
Some ISA use a dot in their opcodes. Allow the decodetree
script to process them. The dot is replaced by an underscore
in the generated code.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/decodetree.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Bin Meng
Current implementation of the imx spi controller expects the burst
length to be multiple of 8, which is the most common use case.
In case the burst length is not what we expect, log it to give user
a chance to notice it, and round it up to be multiple of 8.
Signed-off-by: Bin
On Tue, Jan 12, 2021 at 09:19:43AM +0100, Cornelia Huck wrote:
> On Mon, 11 Jan 2021 11:58:30 -0800
> Ram Pai wrote:
>
> > On Mon, Jan 11, 2021 at 05:59:14PM +0100, Cornelia Huck wrote:
> > > On Tue, 5 Jan 2021 12:41:25 -0800
> > > Ram Pai wrote:
> > >
> > > > On Tue, Jan 05, 2021 at
On 1/12/21 1:40 PM, Thomas Huth wrote:
We can use the "Stupid creek" image to test the mpc8544ds ppc machine.
Signed-off-by: Thomas Huth
---
tests/acceptance/machine_ppc.py | 17 +
1 file changed, 17 insertions(+)
Reviewed-by: Wainer dos Santos Moschetta
diff --git
When the block is disabled, it stay it is 'internal reset logic'
(internal clocks are gated off). Reading any register returns
its reset value. Only update this value if the device is enabled.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
chapter 21.7.3: Control Register
Patchew URL:
https://patchew.org/QEMU/1610476384-13760-1-git-send-email-tsimp...@quicinc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1610476384-13760-1-git-send-email-tsimp...@quicinc.com
Subject: [PATCH]
From: Bin Meng
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210112145526.31095-2-bmeng...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
Hi,
On 1/12/21 1:40 PM, Thomas Huth wrote:
Let's gather the POWER-related tests in a separate file.
Did you consider having others ppc/ppc64 boot tests together too?
Some candidates:
tests/acceptance/boot_linux.py:BootLinuxPPC64.test_pseries_tcg
On 1/12/21 1:40 PM, Thomas Huth wrote:
The "And a hippo new year" image from the QEMU advent calendar 2020
can be used to test the virtex-ml507 ppc machine.
Signed-off-by: Thomas Huth
---
tests/acceptance/machine_ppc.py | 18 ++
1 file changed, 18 insertions(+)
From: Bin Meng
The endianness of data exchange between tx and rx fifo is incorrect.
Earlier bytes are supposed to show up on MSB and later bytes on LSB,
ie: in big endian. The manual does not explicitly say this, but the
U-Boot and Linux driver codes have a swap on the data transferred
to tx
Hi,
As it is sometimes harder for me to express myself in plain
English, I found it easier to write the patches I was thinking
about. I know this doesn't scale.
So this is how I understand the ecSPI reset works, after
looking at the IMX6DQRM.pdf datasheet.
This is a respin of Ben's v5 series
On 1/12/21 5:58 PM, Stefan Hajnoczi wrote:
> It is possible to repeat the --trace option to specify multiple
> patterns. This may be preferrable to users who do not want to create a
> file with a list of patterns.
>
> Suggested-by: BALATON Zoltan
> Signed-off-by: Stefan Hajnoczi
> ---
>
From: Bin Meng
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second
word.
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second
word.
Current logic uses either s->burst_length
---
tests/tcg/multiarch/testthread.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/tests/tcg/multiarch/testthread.c b/tests/tcg/multiarch/testthread.c
index 810ba5d..b30b4b5 100644
--- a/tests/tcg/multiarch/testthread.c
+++ b/tests/tcg/multiarch/testthread.c
@@ -50,8
From: Xuzhou Cheng
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, but chip select
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its
When the block is disabled, all registers are reset with the
exception of the ECSPI_CONREG. It is initialized to zero
when the instance is created.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
chapter 21.7.3: Control Register (ECSPIx_CONREG)
Signed-off-by: Philippe
On Mon, Dec 7, 2020 at 5:58 PM Stefan Hajnoczi wrote:
>
> On Fri, Nov 20, 2020 at 07:50:44PM +0100, Eugenio Pérez wrote:
> > This function is just used for a few commits, so SW LM is developed
> > incrementally, and it is deleted after it is useful.
> >
> > For a few commits, only the events
When the block is disabled, only the ECSPI_CONREG register can
be modified. Setting the EN bit enabled the device, clearing it
"disables the block and resets the internal logic with the
exception of the ECSPI_CONREG" register.
Move the imx_spi_is_enabled() check earlier.
Ref: i.MX 6DQ
Convert some DPRINTF() to trace events.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ssi/imx_spi.c| 8
hw/ssi/trace-events | 7 +++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 40f72c36b61..35ab33c0511 100644
---
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ssi/imx_spi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 35ab33c0511..bcc535f2893 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -303,7 +303,6 @@ static void
'burst_length' is cleared in imx_spi_reset(), which is called
after imx_spi_realize(). Remove the initialization to simplify.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ssi/imx_spi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index
this improves over the workaround in commit
5af415b7d5fd ("cpu: move cc->transaction_failed to tcg_ops")
by moving the tcg cpu operations into a separate file, which is
only included by target-specific code.
The context is that code in ss_common and ss_specific modules
might see different data
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana
---
softmmu/physmem.c | 141 +++---
1 file changed, 72 insertions(+), 69 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[claudio: replaced !CONFIG_USER_ONLY with CONFIG_SOFTMMU in cpu.h]
this is working around a dangerous issue of different parts of the code
seeing the struct
Patchew URL:
https://patchew.org/QEMU/20210112171450.791427-1-pbonz...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210112171450.791427-1-pbonz...@redhat.com
Subject: [PULL 00/20] Misc patches for
move away TCG-only code, make it compile only on TCG.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
---
include/exec/cpu-all.h | 11 +--
include/hw/core/cpu.h | 2 ++
Alessandro Di Federico writes:
> On Tue, 12 Jan 2021 11:58:30 +
> Alex Bennée wrote:
>
>> > -for filename in args.extra_files or []:
>> > +extra_files = args.extra_files or []
>> > +extra_files += glob(basename + ".*")
>> > +for filename in
Hello, this is version 12 of the cleanup, PART 2.
v11 -> v12: reordered patches and improved tcg_ops
* reordered all TcgCpuOperations stuff so it is at the beginning
* added patches for ARM-specific tcg ops
debug_check_watchpoint and adjust_watchpoint_address
* added a patch that puts a
move the call to qemu_init_vcpu inside cpu_common_realizefn,
so it does not need to be done explicitly in each target cpu.
Despite this, the way cpu realize is done continues to be not ideal;
ideally the cpu_list_add would be done in common_cpu,
and in this case we could avoid even more
i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.ccpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/kvm-cpu.cKVM x86 AccelCPUClass
hvf/hvf-cpu.cHVF x86 AccelCPUClass
tcg/tcg-cpu.cTCG x86
move the call to accel_cpu->cpu_realizefn to the general
cpu_exec_realizefn from target/i386, so it does not need to be
called for every target explicitly as we enable more targets.
Signed-off-by: Claudio Fontana
---
cpu.c | 6 ++
target/i386/cpu.c | 20 +++-
2
On Tue, Jan 12, 2021 at 6:36 AM Maxim Uvarov
wrote:
> Implement gpio-pwr driver to allow reboot and poweroff machine.
> This is simple driver with just 2 gpios lines. Current use case
> is to reboot and poweroff virt machine in secure mode. Secure
> pl066 gpio chip is needed for that.
>
>
avoid open coding the accesses to cpu->accel_cpu interfaces,
and instead introduce:
accel_cpu_instance_init,
accel_cpu_realizefn
to be used by the targets/ initfn code,
and by cpu_exec_realizefn respectively.
Add warnings about the use of target-specific headers.
Signed-off-by: Claudio Fontana
add a new optional interface to CPUClass,
which allows accelerators to extend the CPUClass
with additional accelerator-specific initializations.
Add the field before tcg_ops, and mark tcg_ops as
needing to be last in the struct until we rework this
further in a later patch.
Signed-off-by:
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana
---
include/hw/boards.h| 2 +-
include/{sysemu => qemu}/accel.h | 14 +
include/sysemu/hvf.h | 2 +-
also centralize the registration of the cpus.c module
accelerator operations in accel/accel-softmmu.c
Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to
tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the
object type names.
Signed-off-by: Claudio Fontana
---
accel/accel-softmmu.h
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claudio Fontana
---
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Claudio Fontana
---
Am 09.01.2021 um 13:26 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Just use classes introduced in previous three commits. Behavior
> difference is described in these three commits.
>
> Drop group file, as it becomes unused.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
>
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 22 +-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 21 -
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c| 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 4 ++--
target/arm/cpu_tcg.c|
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 12 ++--
accel/tcg/cpu-exec.c
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
---
include/hw/core/cpu.h | 20 +++-
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 4 +++-
target/avr/cpu.c | 2 +-
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
The cocoa UI code currently assumes it is always the active UI
and does not interact well with other UI frontend code. Move
the relevant checks to Meson now that all other frontends
have become Meson options. This way, SDL/GTK+/Cocoa can be
parsed entirely by
CONFIG_GTK_GL is defined if OpenGL is present and GTK+
is 3.16 or newer. Since GTK+ 3.22 is the minimum supported
version, just use CONFIG_OPENGL instead.
Signed-off-by: Paolo Bonzini
---
configure | 7 ---
meson.build| 1 -
ui/gtk.c | 16
ui/meson.build |
From: Keqian Zhu
Correct sample code to avoid confusing readers.
Signed-off-by: Keqian Zhu
Cc: qemu-triv...@nongnu.org
Reviewed-by: Paolo Bonzini
Reviewed-by: Peter Xu
Message-Id: <20210106071710.15836-1-zhukeqi...@huawei.com>
Signed-off-by: Paolo Bonzini
---
docs/devel/rcu.txt | 2 +-
1
From: Chris Hofstaedtler
Cocoa support was always shown as "no", even it if was enabled.
Fixes: b4e312e953b ("configure: move cocoa option to Meson")
Cc: Paolo Bonzini
Cc: Peter Maydell
Cc: Philippe Mathieu-Daudé
Signed-off-by: Chris Hofstaedtler
Message-Id:
From: Yonggang Luo
Signed-off-by: Yonggang Luo
Message-Id: <20210107101919.80-3-luoyongg...@gmail.com>
Signed-off-by: Paolo Bonzini
---
.cirrus.yml | 117 ++--
1 file changed, 68 insertions(+), 49 deletions(-)
diff --git a/.cirrus.yml
On Tue, 12 Jan 2021 05:37:29 -0500
"Michael S. Tsirkin" wrote:
> Looks good to me. Igor, want to ack before I apply this?
Looks good to me too, so
Acked-by: Igor Mammedov
>
> On Tue, Jan 12, 2021 at 06:19:03PM +0800, Jiahui Cen wrote:
> > Kindly ping...
> >
> > Thanks,
> > Jiahui
> >
> >
On Sat 09 Jan 2021 01:57:59 PM CET, Vladimir Sementsov-Ogievskiy wrote:
> Now bdrv_append returns status and we can drop all the local_err things
> around it.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
Berto
Am 09.01.2021 um 13:26 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Add TestEnv class, which will handle test environment in a new python
> iotests running framework.
>
> Difference with current ./check interface:
> - -v (verbose) option dropped, as it is unused
>
> - -xdiff option is
This also allows removing CONFIG_NEED_X11, all the ingredients
can be computed easily in meson.build.
Signed-off-by: Paolo Bonzini
---
configure | 55 ++-
meson.build | 29 ++---
meson_options.txt | 2 ++
Rename the file in preparation for moving more implementation-internal
definitions to it. The build is still broken though.
Signed-off-by: Paolo Bonzini
Reviewed-by: Marc-André Lureau
Message-Id: <20201219090637.1700900-2-pbonz...@redhat.com>
---
target/i386/whpx/whpx-all.c
Hi,
tl;dr: I have some troubles debugging what’s wrong with iotest 129. It
wants to check that 'stop' does not drain a block job, but to me it
seems like that’s exactly what’s happening with the mirror job.
For quite some time, I’ve had 129 disabled in my test branch because it
fails all
> -Original Message-
> From: Alex Bennée
> Sent: Tuesday, January 12, 2021 6:04 AM
> To: Taylor Simpson
> Cc: a...@rev.ng; Brian Cain ;
> richard.hender...@linaro.org; laur...@vivier.eu; phi...@redhat.com;
> qemu-devel@nongnu.org
> Subject: Re: [PATCH v6 31/35] Hexagon
From: Hannes Reinecke
Add trace events for virtio command and response tracing.
Signed-off-by: Hannes Reinecke
Message-Id: <20201116183114.55703-2-h...@suse.de>
Signed-off-by: Paolo Bonzini
---
hw/scsi/trace-events | 9 +
hw/scsi/virtio-scsi.c | 30 +-
2
Ben Widawsky writes:
> On 21-01-12 09:27:39, Alex Bennée wrote:
>>
>> Ben Widawsky writes:
>>
>> > On 21-01-08 22:30:59, Alex Bennée wrote:
>> >>
>> >> Ben Widawsky writes:
>> >>
>> >> > On 21-01-08 12:19:35, Alex Bennée wrote:
>> >> >> GNU Global is another tags engine which is more
From: Yonggang Luo
This struct only used in whpx-apic.c, there is no need
expose it in whpx.h.
Signed-off-by: Yonggang Luo
Message-Id: <20210107101919.80-6-luoyongg...@gmail.com>
Signed-off-by: Paolo Bonzini
---
target/i386/whpx/whpx-apic.c | 7 +++
target/i386/whpx/whpx-internal.h |
On Sat 09 Jan 2021 01:57:58 PM CET, Vladimir Sementsov-Ogievskiy wrote:
> -void bdrv_set_backing_hd(BlockDriverState *bs, BlockDriverState *backing_hd,
> +int bdrv_set_backing_hd(BlockDriverState *bs, BlockDriverState *backing_hd,
> Error **errp)
The indentation of the
Signed-off-by: Alberto Garcia
Suggested-by: Maxim Levitsky
Reviewed-by: Maxim Levitsky
---
v2: Rebase on top of the latest master
tests/qemu-iotests/313 | 103 +
tests/qemu-iotests/313.out | 29 +++
tests/qemu-iotests/group | 1 +
3 files
Make config.status generation a bit more robust. (The quote_sh
function will also be reused to parse configure's command line
arguments in an external script driven by Meson build option
introspection).
Signed-off-by: Paolo Bonzini
---
configure | 6 +-
1 file changed, 5 insertions(+), 1
From: Yonggang Luo
Signed-off-by: Yonggang Luo
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210107101919.80-4-luoyongg...@gmail.com>
Signed-off-by: Paolo Bonzini
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
For now move the logic verbatim. GTK+ actually has a hard requirement
on X11 if gtk+x11 is present, but we will sort that out later.
Signed-off-by: Paolo Bonzini
---
configure | 14 ++
meson.build| 9 +
ui/meson.build | 4 ++--
3 files changed, 9 insertions(+),
101 - 200 of 481 matches
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