[PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- target/riscv/vector_helper.c| 12 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git

[PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 +

[PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR

From: Frank Chang * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. Signed-off-by: Frank Chang -- Perhaps we can remove the probe functions in vector_helper.c

[PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index

[PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- gdb-xml/riscv-32bit-csr.xml | 7 ++ gdb-xml/riscv-64bit-csr.xml | 7 ++ target/riscv/cpu.c | 1 + target/riscv/cpu.h | 25 + target/riscv/gdbstub.c

[PATCH v6 47/72] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 8 1 file changed, 8 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5622fb23f85..93ed6f54e99 100644 ---

[PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 5 + target/riscv/helper.h | 1

[PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c| 52

[PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/csr.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 28c1ce7928a..176010674e8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -301,7 +301,7 @@

[PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.c.inc | 2 -- target/riscv/vector_helper.c| 7 --- 4 files

[PATCH v6 50/72] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 16 +++

[PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and

[PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode

[PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson ---

[PATCH v6 49/72] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24

[PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +- target/riscv/insn_trans/trans_rvv.c.inc | 30 -

[PATCH] hw/block/nvme: fix zone write finalize

From: Klaus Jensen The zone write pointer is unconditionally advanced, even for write faults. Make sure that the zone is always transitioned to Full if the write pointer reaches zone capacity. Signed-off-by: Klaus Jensen Cc: Dmitry Fomichev --- hw/block/nvme.c | 10 +- 1 file

[PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 + target/riscv/insn32.decode | 8 +++

[PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert

From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 + target/riscv/insn32.decode

[PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 20 ++--

[PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.c.inc | 25 + 2 files changed, 29 insertions(+) diff --git

[PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.c.inc | 9 -- target/riscv/vector_helper.c| 205

[PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 32 + 1 file changed, 22 insertions(+), 10 deletions(-)

[PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(+), 8 deletions(-) diff --git

[PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 45 - 2 files

[PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 39 + target/riscv/internals.h| 5

[PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 022530697ec..8467dfc84b1 100644 ---

[PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 6 +++--- 4 files

[PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 27 ++--- target/riscv/vector_helper.c

[PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 129 +++--- target/riscv/insn32.decode | 43 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 227 +++- target/riscv/vector_helper.c| 190

[PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files

[PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fae5ea3fa63..a593938e5c8 100644 ---

[PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 10 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode

[PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 53 + target/riscv/vector_helper.c| 14 ++- 2 files changed, 31 insertions(+), 36 deletions(-) diff --git

[PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c0053cfb828..a0a47dbceb3 100644 ---

[PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e11666f16df..c0053cfb828 100644 ---

[PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 43 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 12

[PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c

[PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 21 target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.c.inc | 69 +

[PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++-- target/riscv/vector_helper.c| 90 ++--- 2 files changed, 74 insertions(+), 48 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v6 22/72] target/riscv: rvv-1.0: amo operations

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 100 +++--- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 36 +++- target/riscv/insn_trans/trans_rvv.c.inc | 229 +++

[PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 69 - target/riscv/translate.c| 33 2 files changed, 90 insertions(+), 12 deletions(-)

[PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-)

[PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 27 +++- target/riscv/insn32.decode | 14 +++ target/riscv/insn_trans/trans_rvv.c.inc | 33 --- target/riscv/vector_helper.c

[PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting.

[PATCH v6 19/72] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 67 target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.c.inc | 209 target/riscv/vector_helper.c| 89 +- 4 files

[PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v6 14/72] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 732 1 file changed, 499 insertions(+), 233 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index

[PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW)

[PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/csr.c | 13 - 1 file changed, 13

[PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 ++- target/riscv/csr.c| 25 - 4 files

[PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 17 + target/riscv/translate.c | 16

[PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 35 +--- target/riscv/internals.h| 9 +-

[PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d281..bc3f212ceac 100644 ---

[PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index

[PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/csr.c | 2 +- 1 file

[PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v6 00/72] support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. As vector extension specification is near to be ratified, this patchset is sent as formal patchset for review. The port is available here: https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v6 You can

Re: [PATCH v6 05/35] Hexagon (disas) disassembler

On Mon, Jan 11, 2021 at 11:20:27PM +0100, Philippe Mathieu-Daudé wrote: > +Thomas/Daniel/Peter. > > On 1/11/21 10:14 PM, Taylor Simpson wrote: > >> -Original Message- > >> From: Qemu-devel >> bounces+tsimpson=quicinc@nongnu.org> On Behalf Of Philippe > >> Mathieu-Daudé > >> Sent:

Re: [PATCH] shippable.yml: Remove jobs duplicated on Gitlab-CI

Philippe Mathieu-Daudé writes: > The following jobs are duplicated on Gitlab-CI since commit > 6bcb5fc0f7a ("gitlab-ci: Add cross-compiling build tests"): Queued to testing/next, thanks. -- Alex Bennée

Re: [RFC PATCH] Makefile: add GNU global tags support

Ben Widawsky writes: > On 21-01-08 22:30:59, Alex Bennée wrote: >> >> Ben Widawsky writes: >> >> > On 21-01-08 12:19:35, Alex Bennée wrote: >> >> GNU Global is another tags engine which is more like cscope in being >> >> able to support finding both references and definitions. You will be

Re: [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode

On 1/11/21 7:43 PM, Claudio Fontana wrote: > Hi Richard, > > happy new year, > > this change of mine breaks with --enable-debug, after your changes related to > "splitrw" in tcg/, > I am a bit at a loss at what could be going wrong.. any hints? > > I am getting assertion failures with

Re: What's the correct way to implement rfi and related instruction.

> QEMU 5.2.x, an e300 based machine ppc603 are impacted. > Here is my fix, narrowed down to  MSR_TGPR and  MSR_ILE > ``` > From 42ce41671f1e6c4dd44e6fb481bbda9df09320bd Mon Sep 17 00:00:00 2001 > From: Yonggang Luo mailto:luoyongg...@gmail.com>> > Date: Sun, 10 Jan 2021 00:08:00 -0800 > Subject:

Re: [PATCH] cirrus.yml: Replace the hard-coded python-sphinx version with the generic one

On 11/01/2021 21.16, 罗勇刚(Yonggang Luo) wrote: On Mon, Jan 11, 2021 at 6:34 PM Thomas Huth > wrote: > > The mingw-w64-x86_64-python-sphinx-2.3.1 package has been removed from > the server, so the windows_msys2_task is currently failing. Replace the > old version

[Bug 1911075] Re: [OSS-Fuzz] ahci: stack overflow in ahci_cond_start_engines

** Changed in: qemu Assignee: (unassigned) => John Snow (jnsnow) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1911075 Title: [OSS-Fuzz] ahci: stack overflow in ahci_cond_start_engines

Re: [PATCH v2 2/2] s390x: Use strpadcpy for copying vm name

On 11/01/2021 18.09, Miroslav Rezanina wrote: When using strncpy with lenght equal to size of target array, s/lenght/length/ GCC 11 produce following warning: warning: '__builtin_strncpy' specified bound 256 equals destination size [-Wstringop-truncation] To prevent this warning, use

Re: [PATCH v6 10/13] spapr: Add PEF based confidential guest support

On Tue, Jan 12, 2021 at 08:56:53AM +0100, Christian Borntraeger wrote: > > > On 12.01.21 05:45, David Gibson wrote: > [...] > > diff --git a/include/hw/ppc/pef.h b/include/hw/ppc/pef.h > > new file mode 100644 > > index 00..7c92391177 > > --- /dev/null > > +++ b/include/hw/ppc/pef.h > >

Re: [PATCH v2 0/3] Fix up sam460ex fixes

On Fri, Jan 08, 2021 at 11:07:38PM +0100, BALATON Zoltan wrote: > Accidentally the wrong version of this series was committed, this > series fixes that up to the last version that was meant to be merged. > This v2 is rebased on Peter's UIC series and clarifies commit message > of last patch. > >

Re: [for-6.0 v5 11/13] spapr: PEF: prevent migration

On Mon, 11 Jan 2021 11:58:30 -0800 Ram Pai wrote: > On Mon, Jan 11, 2021 at 05:59:14PM +0100, Cornelia Huck wrote: > > On Tue, 5 Jan 2021 12:41:25 -0800 > > Ram Pai wrote: > > > > > On Tue, Jan 05, 2021 at 11:56:14AM +0100, Halil Pasic wrote: > > > > On Mon, 4 Jan 2021 10:40:26 -0800 > > >

Re: [PATCH v3 4/5] tests/tcg/s390x: Fix EXRL tests

On 12/01/2021 08.47, David Hildenbrand wrote: Am 12.01.2021 um 08:41 schrieb Thomas Huth : On 11/01/2021 17.38, David Hildenbrand wrote: The current EXRL tests crash on real machines: we must not use r0 as a base register for trt/trtr, otherwise the content gets ignored. Also, we must not

Re: [PATCH v6 13/13] s390: Recognize confidential-guest-support option

On 12.01.21 05:45, David Gibson wrote: > At least some s390 cpu models support "Protected Virtualization" (PV), > a mechanism to protect guests from eavesdropping by a compromised > hypervisor. > > This is similar in function to other mechanisms like AMD's SEV and > POWER's PEF, which are

Re: [PATCH 6/6] get_maintainer: update repo URL to GitLab

On 11/01/2021 12.50, Stefan Hajnoczi wrote: qemu.org is running out of bandwidth and the QEMU project is moving towards a gating CI on GitLab. Use the GitLab repos instead of qemu.org (they will become mirrors). Signed-off-by: Stefan Hajnoczi --- scripts/get_maintainer.pl | 2 +- 1 file

Re: [PATCH 5/6] pc-bios: update mirror URLs to GitLab

On 11/01/2021 12.50, Stefan Hajnoczi wrote: qemu.org is running out of bandwidth and the QEMU project is moving towards a gating CI on GitLab. Use the GitLab repos instead of qemu.org (they will become mirrors). Signed-off-by: Stefan Hajnoczi --- pc-bios/README | 4 ++-- 1 file changed, 2

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