From: Klaus Jensen
nvme_ns_attachment() does not verify the contents of the host-supplied
16 bit "Number of Identifiers" field in the command payload.
Make sure the value is capped at 2047 and fix the out-of-bounds read.
Fixes: 645ce1a70cb6 ("hw/block/nvme: support namespace attachment command"
From: Klaus Jensen
nvme_subsys_ctrl() is used in contexts where the given controller
identifier is from an untrusted source. Like its friends nvme_ns() and
nvme_subsys_ns(), nvme_subsys_ctrl() should just return NULL if an
invalid identifier is given.
Fixes: 645ce1a70cb6 ("hw/block/nvme: support
From: Klaus Jensen
Prior to this patch, if a private nvme-ns device (that is, a namespace
that is not linked to a subsystem) is wired up to an nvme-subsys linked
nvme controller device, the device fails to verify that the namespace id
is unique within the subsystem. NVM Express v1.4b, Section 6.1
From: Klaus Jensen
Add missing license/copyright headers to the nvme-dif.{c,h} files.
Signed-off-by: Klaus Jensen
Reviewed-by: Keith Busch
---
hw/block/nvme-dif.h | 10 ++
hw/block/nvme-dif.c | 10 ++
2 files changed, 20 insertions(+)
diff --git a/hw/block/nvme-dif.h b/hw/blo
From: Klaus Jensen
Remove the unused BlockConf from the controller structure and fix the
constraint checking to actually check the right BlockConf and issue the
warning.
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme.h | 1 -
hw/block/nv
From: Klaus Jensen
The Non-MDTS DMSRL limit must be recomputed when namespaces are
detached.
Fixes: 645ce1a70cb6 ("hw/block/nvme: support namespace attachment command")
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme.c | 17 ++
From: Klaus Jensen
nvme_subsys_ns() is used in contexts where the namespace identifier is
taken from an untrusted source. Commit 3921756dee6d ("hw/block/nvme:
assert namespaces array indices") tried to guard against this by
introducing an assert on the namespace identifier.
This is wrong since i
From: Klaus Jensen
The `nvme_nsid()` function returns '-1' (h) when the given
namespace is NULL. Since h is actually a valid namespace
identifier (the "broadcast" value), change this to be '0' since that
actually *is* the invalid value.
Signed-off-by: Klaus Jensen
Reviewed-by: G
From: Klaus Jensen
Add the missing nvme_adm_opc_str entry for the Namespace Attachment
command.
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index
From: Klaus Jensen
Protection Information can only be enabled if there is at least 8 bytes
of metadata.
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme-ns.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme
From: Klaus Jensen
Hi Peter,
My apologies that these didn't make it for -rc2!
I botched v1, so please pull this v2 instead.
The following changes since commit d0d3dd401b70168a353450e031727affee828527:
Update version for v6.0.0-rc2 release (2021-04-06 18:34:34 +0100)
are available in the G
On Wed, Apr 7, 2021 at 7:26 AM Howard Spoelstra wrote:
>
> On Wed, Apr 7, 2021 at 3:53 AM Programmingkid
> wrote:
> >
> >
> >
> > > On Apr 6, 2021, at 7:18 PM, BALATON Zoltan wrote:
> > >
> > > On Tue, 6 Apr 2021, Programmingkid wrote:
> > >>> On Apr 6, 2021, at 12:53 PM, BALATON Zoltan wrote:
On Wed, Apr 7, 2021 at 3:53 AM Programmingkid wrote:
>
>
>
> > On Apr 6, 2021, at 7:18 PM, BALATON Zoltan wrote:
> >
> > On Tue, 6 Apr 2021, Programmingkid wrote:
> >>> On Apr 6, 2021, at 12:53 PM, BALATON Zoltan wrote:
> >>> On Tue, 6 Apr 2021, Programmingkid wrote:
> > On Apr 6, 2021, at 1
On Tue, Apr 06, 2021 at 06:38:21PM +, Bruno Piazera Larsen wrote:
> > t's usually best to focus on logical changes, rather than
> > file-by-file. That said, I'd probably suggest changing the .c files
> > first, then changing the meson file.
>
> OK, will do!
>
> > I'd lean towards building a
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
From: Cupertino Miranda
Add the most generic parts of TCG constructions. It contains the
basic infrastructure for fundamental ARC features, such as
ZOL (zero overhead loops) and delay-slots.
Also includes hand crafted TCG for more intricate i
On Tue, Apr 6, 2021, at 9:06 PM, Alex Bennée wrote:
> Hi,
>
> I was trying to bootstrap a Loongson3 Debian image but ran into some
> roadblocks. Philippe pointed me at:
>
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg768848.html
>
> which gives a bit of detail but elides over deta
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, April 6, 2021 5:12 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@redhat.com; a...@rev.ng; Brian Cain
> Subject: Re: [PATCH v2 17/21] Hexagon (target/hexagon) circular addressing
>
> On 3/31/21 8:53 PM, Taylor
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+static inline target_ulong
+carry_add_flag(target_ulong dest, target_ulong b, target_ulong c, uint8_t size)
+{
+target_ulong t1, t2, t3;
+
+t1 = b & c;
+t2 = b & (~dest);
+t3 = c & (~dest);
+t1 = t1 | t2 | t3;
+return (
Expose AVX (VEX-encoded) versions of the Vector Neural Network
Instructions to guest.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 4] AVX_VNNI
The following instructions are available when this feature is
present in the guest.
1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
2. VPDPB
在 2021/4/7 上午7:27, Dongli Zhang 写道:
This will answer your question that "Can it bypass the masking?".
For vhost-scsi, virtio-blk, virtio-scsi and virtio-net, to write to eventfd is
not able to bypass masking because masking is to unregister the eventfd. To
write to eventfd does not take effect
在 2021/4/6 下午4:43, Dongli Zhang 写道:
On 4/5/21 6:55 PM, Jason Wang wrote:
在 2021/4/6 上午4:00, Dongli Zhang 写道:
On 4/1/21 8:47 PM, Jason Wang wrote:
在 2021/3/30 下午3:29, Dongli Zhang 写道:
On 3/28/21 8:56 PM, Jason Wang wrote:
在 2021/3/27 上午5:16, Dongli Zhang 写道:
Hi Jason,
On 3/26/21 12:24 AM
If the scratch vCPU is initialized without PMU feature, we receive
error on reading PMCR_EL0 as it's invisible in this case. It leads
to host probing failure.
This fixes the issue by initializing the scratch vcpu with the PMU
feature enabled and reading PMCR_EL0 from host. Otherwise, its value
is
@init->target is always -1 and preferred target is retrieved from
host when @init isn't NULL in kvm_arm_create_scratch_host_vcpu().
So we can have the assumption that preferred target retrived from
host is tried prior to the specified target list.
Signed-off-by: Gavin Shan
---
target/arm/kvm.c
> On Apr 6, 2021, at 7:18 PM, BALATON Zoltan wrote:
>
> On Tue, 6 Apr 2021, Programmingkid wrote:
>>> On Apr 6, 2021, at 12:53 PM, BALATON Zoltan wrote:
>>> On Tue, 6 Apr 2021, Programmingkid wrote:
> On Apr 6, 2021, at 10:01 AM, Howard Spoelstra wrote:
> On Tue, Apr 6, 2021 at 3:44
On Wed, Apr 7, 2021 at 6:51 AM Alistair Francis
wrote:
>
> Update the RISC-V maintainers by removing Sagar and Bastian who haven't
> been involved recently.
>
> Also add Bin who has been helping with reviews.
>
> Signed-off-by: Alistair Francis
> ---
> I have run this by all of the people involve
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+static long long int
+extract_uimm6_20(unsigned long long insn ATTRIBUTE_UNUSED,
global replace long long int with int64_t,
and unsigned long long int with uint64_t.
+{
+ unsigned value = 0;
+
+ value |= ((insn >> 6) & 0x003f) << 0;
+
+
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+DEFINE_PROP_BOOL("byte-order", ARCCPU, cfg.byte_order, false),
"byte-order" makes no sense as a bool.
"little-endian" or "big-endian" would.
+info->endian = BFD_ENDIAN_LITTLE;
Not using the setting?
+/*-*-indent-tabs-mode:nil;t
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
In order to simplify the review process, we have separated the patches
for ARCv3 from the previous emailed ARCv2 ones. Being the patches from
1 to 16 for ARCv2 and 17 to 27 for ARCv3.
How may one find the arcv3 documentation on the synopsis w
On Tue, Apr 06, 2021, Michael Tokarev wrote:
> Hi!
>
> It looks like this commit:
>
> commit 87fa7f3e98a1310ef1ac1900e7ee7f9610a038bc
> Author: Thomas Gleixner
> Date: Wed Jul 8 21:51:54 2020 +0200
>
> x86/kvm: Move context tracking where it belongs
>
> Context tracking for KVM happe
On Tue, Apr 06, 2021 at 03:21:18PM -0700, Patrick Venture wrote:
> On Tue, Apr 6, 2021 at 11:36 AM Corey Minyard wrote:
> >
> > On Tue, Apr 06, 2021 at 08:55:14AM -0700, Patrick Venture wrote:
> > > On Tue, Apr 6, 2021 at 8:41 AM Patrick Venture wrote:
> > > >
> > > > On Mon, Apr 5, 2021 at 12:58
On 4/6/21 1:43 AM, Dongli Zhang wrote:
>
>
> On 4/5/21 6:55 PM, Jason Wang wrote:
>>
>> 在 2021/4/6 上午4:00, Dongli Zhang 写道:
>>>
>>> On 4/1/21 8:47 PM, Jason Wang wrote:
在 2021/3/30 下午3:29, Dongli Zhang 写道:
> On 3/28/21 8:56 PM, Jason Wang wrote:
>> 在 2021/3/27 上午5:16, Dongli Zhang
On Tue, 6 Apr 2021, Programmingkid wrote:
On Apr 6, 2021, at 12:53 PM, BALATON Zoltan wrote:
On Tue, 6 Apr 2021, Programmingkid wrote:
On Apr 6, 2021, at 10:01 AM, Howard Spoelstra wrote:
On Tue, Apr 6, 2021 at 3:44 PM Programmingkid wrote:
Hi Gerd,
I was wondering if you had access to a M
On 4/6/21 1:28 PM, Philippe Mathieu-Daudé wrote:
Fix a TCG temporary leak when translating CACHE opcode.
Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 2 ++
1 file changed, 2 insertions(+)
Reviewe
On 3/31/21 8:53 PM, Taylor Simpson wrote:
The following instruction is added
S2_cabacdecbinRdd32=decbin(Rss32,Rtt32)
Test cases added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 91 +++
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.
Also add Bin who has been helping with reviews.
Signed-off-by: Alistair Francis
---
I have run this by all of the people involved and they are all ok with
the change.
MAINTAINERS | 5 ++---
1 file c
On 3/31/21 8:53 PM, Taylor Simpson wrote:
Test cases in tests/tcg/hexagon/load_align.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 66 ++
target/hexagon/imported/encode_pp.def | 3 +
target/hexagon/imported/ldst.idef | 19 ++
tests/tcg/hexagon/Makef
On 3/31/21 8:53 PM, Taylor Simpson wrote:
Test cases in tests/tcg/hexagon/load_unpack.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 108
target/hexagon/genptr.c | 13 +
target/hexagon/imported/encode_pp.def | 6 +
target/hexagon/import
On 3/31/21 8:53 PM, Taylor Simpson wrote:
The following instructions are added
L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev)
L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev)
L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev)
L2_loadrh_pbr Rd32 = memh(Rx32
On Tue, Apr 6, 2021 at 11:36 AM Corey Minyard wrote:
>
> On Tue, Apr 06, 2021 at 08:55:14AM -0700, Patrick Venture wrote:
> > On Tue, Apr 6, 2021 at 8:41 AM Patrick Venture wrote:
> > >
> > > On Mon, Apr 5, 2021 at 12:58 PM Corey Minyard wrote:
> > > >
> > > > On Sat, Apr 03, 2021 at 03:28:08PM
On 4/6/21 2:55 PM, Taylor Simpson wrote:
-Original Message-
From: Richard Henderson
Sent: Tuesday, April 6, 2021 3:46 PM
To: Taylor Simpson ; qemu-devel@nongnu.org
Cc: phi...@redhat.com; a...@rev.ng; Brian Cain
Subject: Re: [PATCH v2 12/21] Hexagon (target/hexagon) add F2_sfrecipa
ins
On 3/31/21 8:53 PM, Taylor Simpson wrote:
+static inline TCGv gen_read_reg(TCGv result, int num)
The unnecessary inlines are back, just after having removed them in patch 2.
+#ifdef QEMU_GENERATE
+static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
+{
+/*
+ * Section 2
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, April 6, 2021 4:12 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@redhat.com; a...@rev.ng; Brian Cain
> Subject: Re: [PATCH v2 16/21] Hexagon (target/hexagon) add
> A4_addp_c/A4_subp_c
>
> On 3/31/21 8:53 PM,
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, April 6, 2021 3:46 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@redhat.com; a...@rev.ng; Brian Cain
> Subject: Re: [PATCH v2 12/21] Hexagon (target/hexagon) add F2_sfrecipa
> instruction
>
> On 3/31/21 8:53 P
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, April 6, 2021 3:51 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@redhat.com; a...@rev.ng; Brian Cain
> Subject: Re: [PATCH v2 14/21] Hexagon (target/hexagon) add A5_ACS
> (vacsh)
>
> On 3/31/21 8:53 PM, Taylor
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 6.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-6.0.0-rc2.tar.xz
http://downl
On 3/31/21 8:53 PM, Taylor Simpson wrote:
+#define fGEN_TCG_A4_addp_c(SHORTCODE) \
+do { \
+TCGv_i64 carry = tcg_temp_new_i64(); \
+TCGv_i64 zero = tcg_const_i64(0); \
+tcg_gen_extu_i32_i64(carry, PxV); \
+tcg_gen_andi_i64(carry, carry, 1); \
+tcg_gen_a
On 3/31/21 8:53 PM, Taylor Simpson wrote:
Rdd32,Pe4 = vminub(Rtt32, Rss32)
Vector min of bytes
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 27 +++
target/hexagon/genptr.c |
Bruno Piazera Larsen writes:
>> You'll probably also need changes in hw/ppc/spapr_hcall.c and maybe
>> some other parts of the spapr code: there are a number of hypercalls
>> that we implement in qemu for TCG, but which are (and must be)
>> implemented in KVM when KVM is in use. So, I expect you
From: Klaus Jensen
The Non-MDTS DMSRL limit must be recomputed when namespaces are
detached.
Fixes: 645ce1a70cb6 ("hw/block/nvme: support namespace attachment command")
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme.c | 17 ++
From: Klaus Jensen
Remove the unused BlockConf from the controller structure and fix the
constraint checking to actually check the right BlockConf and issue the
warning.
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme.h | 1 -
hw/block/nv
On 3/31/21 8:53 PM, Taylor Simpson wrote:
+#define fGEN_TCG_A5_ACS(SHORTCODE) \
+do { \
+gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \
+gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
+} while (0)
You've modified RxxV before its last use.
I think just
On 3/31/21 8:53 PM, Taylor Simpson wrote:
+int arch_invsqrt_lookup(int index)
+{
+index &= 0x7f;
+const uint8_t roundrom[128] = {
+0x069, 0x066, 0x063, 0x061, 0x05e, 0x05b, 0x059, 0x057,
+0x054, 0x052, 0x050, 0x04d, 0x04b, 0x049, 0x047, 0x045,
+0x043, 0x041, 0x03f,
From: Klaus Jensen
Add missing license/copyright headers to the nvme-dif.{c,h} files.
Signed-off-by: Klaus Jensen
Reviewed-by: Keith Busch
---
hw/block/nvme-dif.h | 10 ++
hw/block/nvme-dif.c | 10 ++
2 files changed, 20 insertions(+)
diff --git a/hw/block/nvme-dif.h b/hw/blo
From: Klaus Jensen
The `nvme_nsid()` function returns '-1' (h) when the given
namespace is NULL. Since h is actually a valid namespace
identifier (the "broadcast" value), change this to be '0' since that
actually *is* the invalid value.
Signed-off-by: Klaus Jensen
Reviewed-by: G
From: Klaus Jensen
Hi Peter,
My apologies that these didn't make it for -rc2!
The following changes since commit d0d3dd401b70168a353450e031727affee828527:
Update version for v6.0.0-rc2 release (2021-04-06 18:34:34 +0100)
are available in the Git repository at:
git://git.infradead.org/qe
From: Klaus Jensen
Prior to this patch, if a private nvme-ns device (that is, a namespace
that is not linked to a subsystem) is wired up to an nvme-subsys linked
nvme controller device, the device fails to verify that the namespace id
is unique within the subsystem. NVM Express v1.4b, Section 6.1
From: Klaus Jensen
Protection Information can only be enabled if there is at least 8 bytes
of metadata.
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme-ns.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme
From: Klaus Jensen
Add the missing nvme_adm_opc_str entry for the Namespace Attachment
command.
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Keith Busch
---
hw/block/nvme.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index
On 3/31/21 8:53 PM, Taylor Simpson wrote:
+int arch_recip_lookup(int index)
+{
+index &= 0x7f;
+const uint8_t roundrom[128] = {
+0x0fe, 0x0fa, 0x0f6, 0x0f2, 0x0ef, 0x0eb, 0x0e7, 0x0e4,
+0x0e0, 0x0dd, 0x0d9, 0x0d6, 0x0d2, 0x0cf, 0x0cc, 0x0c9,
+0x0c6, 0x0c2, 0x0bf, 0
Ouch, yes indeed. Will fix.
** Changed in: qemu
Status: New => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net
Public bug reported:
I'm running a machine learning model on qemu riscv32 and I ran into
illegal instruction exception for some reason. I wasn't sure if this is
a bug and if so whether it is related to zephyr or qemu, however I'll
try to provide as much as information to get a better understanding
On 3/31/21 8:53 PM, Taylor Simpson wrote:
+int arch_recip_lookup(int index)
+{
+index &= 0x7f;
+const uint8_t roundrom[128] = {
static. Otherwise,
Reviewed-by: Richard Henderson
r~
Fix a TCG temporary leak when translating CACHE opcode.
Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate
Hi!
It looks like this commit:
commit 87fa7f3e98a1310ef1ac1900e7ee7f9610a038bc
Author: Thomas Gleixner
Date: Wed Jul 8 21:51:54 2020 +0200
x86/kvm: Move context tracking where it belongs
Context tracking for KVM happens way too early in the vcpu_run()
code. Anything after guest_
On Tue, 6 Apr 2021 at 20:49, Taylor Simpson wrote:
> On the other hand, isn't python3 standard for building qemu now? This page
> https://wiki.qemu.org/Hosts/Linux#Required_additional_packages
> lists python3 as an additional required package for RHEL8.
Python 3 is required, but there's no guara
On 3/31/21 8:53 PM, Taylor Simpson wrote:
Use the proper return for helpers that convert to unsigned
Remove target/hexagon/conv_emu.[ch]
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/conv_emu.c | 177
target/hex
Hi Kunkun,
On 3/27/21 3:24 AM, Kunkun Jiang wrote:
> Hi all,
>
> Recently, I did some tests on SMMU nested mode. Here is
> a question about the translation granule size supported by
> vSMMU.
>
> There is such a code in SMMUv3_init_regs():
>
>> /* 4K and 64K granule support */
>> s->idr[5
> -Original Message-
> From: John Snow
> Sent: Tuesday, April 6, 2021 2:38 PM
> To: Dr. David Alan Gilbert ; Taylor Simpson
>
> Cc: qemu-devel@nongnu.org
> Subject: Re: dectree.py uses env python3 rather than configured python
>
> On 4/6/21 2:50 PM, Dr. David Alan Gilbert wrote:
> > Hi T
On 4/6/21 2:50 PM, Dr. David Alan Gilbert wrote:
Hi Taylor,
I tripped over dectree.py using 'env python3'; the qemu configure
script lets you specify a python with e.g.:
--with-python=/usr/libexec/platform-python
and I think everywhere else in qemu uses the configured python.
(This host,
Le 06/04/2021 à 19:40, Richard Henderson a écrit :
> Unfortuately, the elements of PAGE_* were not in numerical
> order and so PAGE_ANON was added to an "unused" bit.
> As an arbitrary choice, move PAGE_TARGET_{1,2} together.
>
> Cc: Laurent Vivier
> Fixes: 26bab757d41b ("linux-user: Introduce PA
On Mon, 8 Feb 2021 15:57:55 -0500
Eric DeVolder wrote:
> This change implements the support for the ACPI ERST feature[1,2].
>
> The size of the ACPI ERST storage is declared via the QEMU
> global parameter acpi-erst.size. The size can range from 64KiB
> to to 64MiB. The default is 64KiB.
>
> T
> On Apr 6, 2021, at 12:53 PM, BALATON Zoltan wrote:
>
> On Tue, 6 Apr 2021, Programmingkid wrote:
>>> On Apr 6, 2021, at 10:01 AM, Howard Spoelstra wrote:
>>> On Tue, Apr 6, 2021 at 3:44 PM Programmingkid
>>> wrote:
Hi Gerd,
I was wondering if you had access to a Mac
On Mon, 8 Feb 2021 15:57:56 -0500
Eric DeVolder wrote:
> This change includes ERST in the build of ACPI support.
>
> Signed-off-by: Eric DeVolder
> ---
> hw/acpi/meson.build | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build
> index dd69577..26
❦ 6 avril 2021 21:05 +02, Igor Mammedov:
>> >>> This can be invoked with:
>> >>>
>> >>> $QEMU -netdev user,id=internet
>> >>> -device
>> >>> virtio-net-pci,mac=50:54:00:00:00:42,netdev=internet,id=internet-dev \
>> >>> -smbios type=41,designation='Onboard
>> >>> LAN',i
On Fri, 02 Apr 2021 19:40:03 +0200
Vincent Bernat wrote:
> ❦ 1 avril 2021 23:07 +02, Vincent Bernat:
>
> >>> This can be invoked with:
> >>>
> >>> $QEMU -netdev user,id=internet
> >>> -device
> >>> virtio-net-pci,mac=50:54:00:00:00:42,netdev=internet,id=internet-dev \
> >>>
On Tue, Apr 06, 2021 at 08:36:13PM +0200, Igor Mammedov wrote:
> On Tue, 6 Apr 2021 09:42:50 +0200
> Andrew Jones wrote:
>
> > On Thu, Apr 01, 2021 at 11:32:25PM +0200, Igor Mammedov wrote:
> > > On Thu, 01 Apr 2021 23:07:06 +0200
> > > Vincent Bernat wrote:
> > >
> > > > ❦ 1 avril 2021 22:
On Sat, 03 Apr 2021 16:52:13 -
Christian Ehrhardt <1915...@bugs.launchpad.net> wrote:
> That is awesome David,
> qemu64 is like a very low common denominator with only very basic CPU
> features.
> While "copy host" means "enable all you can".
Also it's worth to try setting real CPU topolog
Hi Taylor,
I tripped over dectree.py using 'env python3'; the qemu configure
script lets you specify a python with e.g.:
--with-python=/usr/libexec/platform-python
and I think everywhere else in qemu uses the configured python.
(This host, like most standard rhel8, doesn't have a python3 bin
> t's usually best to focus on logical changes, rather than
> file-by-file. That said, I'd probably suggest changing the .c files
> first, then changing the meson file.
OK, will do!
> I'd lean towards building a whole series, since I think the individual
> file changes won't make a lot of sense
On Tue, 6 Apr 2021 09:42:50 +0200
Andrew Jones wrote:
> On Thu, Apr 01, 2021 at 11:32:25PM +0200, Igor Mammedov wrote:
> > On Thu, 01 Apr 2021 23:07:06 +0200
> > Vincent Bernat wrote:
> >
> > > ❦ 1 avril 2021 22:58 +02, Igor Mammedov:
> > >
> > > >> This can be invoked with:
> > > >>
>
On Tue, Apr 06, 2021 at 08:55:14AM -0700, Patrick Venture wrote:
> On Tue, Apr 6, 2021 at 8:41 AM Patrick Venture wrote:
> >
> > On Mon, Apr 5, 2021 at 12:58 PM Corey Minyard wrote:
> > >
> > > On Sat, Apr 03, 2021 at 03:28:08PM -0700, Patrick Venture wrote:
> > > > The i2c mux device pca954x imp
On Tue, Apr 06, 2021 at 10:06:09AM -0700, Patrick Venture wrote:
> On Tue, Apr 6, 2021 at 9:54 AM Corey Minyard wrote:
> >
> > On Tue, Apr 06, 2021 at 09:04:35AM -0700, Patrick Venture wrote:
> > > Corey;
> > >
> > > I saw you have a branch that is working on adding smbus IPMI support
> > > (the s
Le 06/04/2021 à 19:40, Richard Henderson a écrit :
> Unfortuately, the elements of PAGE_* were not in numerical
> order and so PAGE_ANON was added to an "unused" bit.
> As an arbitrary choice, move PAGE_TARGET_{1,2} together.
>
> Cc: Laurent Vivier
> Fixes: 26bab757d41b ("linux-user: Introduce PA
On Apr 6 09:28, Klaus Jensen wrote:
> On Apr 6 09:01, Philippe Mathieu-Daudé wrote:
> > On 4/5/21 7:54 PM, Klaus Jensen wrote:
> > > From: Klaus Jensen
> > >
> > > The controller namespaces array being 0-indexed requires 'nsid - 1'
> > > everywhere. Something that is easy to miss. Align the con
On Tue, 6 Apr 2021 16:07:25 +0100
Daniel P. Berrangé wrote:
> On Tue, Apr 06, 2021 at 03:54:24PM +0100, Daniel P. Berrangé wrote:
> > On Mon, Mar 22, 2021 at 07:00:18PM -0400, Michael S. Tsirkin wrote:
> > > From: Igor Mammedov
> > >
> > > it helps to avoid device naming conflicts when guest
On Fri, 19 Mar 2021 10:47:11 -0700
Ben Widawsky wrote:
> On 21-03-19 18:07:05, Igor Mammedov wrote:
> > On Wed, 17 Mar 2021 14:40:58 -0700
> > Ben Widawsky wrote:
> >
> > > Phil, Igor, Markus
> > >
> > > TL;DR: What to do about multiple capacities in a single device, and what
> > > to do
>
Bastian Koppelmann writes:
> On Fri, Mar 05, 2021 at 06:00:30PM +0100, Bastian Koppelmann wrote:
>> Hi Alex,
>>
>> after a long while and thanks to Thomas reminder, I finally came back to this
>> series. I addressed most of your comments except for the timeout --foreground
>> problem (see
>>
Patchew URL:
https://patchew.org/QEMU/20210406174031.64299-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210406174031.64299-1-richard.hender...@linaro.org
Subject: [PATCH v4 00/12] ta
Unfortuately, the elements of PAGE_* were not in numerical
order and so PAGE_ANON was added to an "unused" bit.
As an arbitrary choice, move PAGE_TARGET_{1,2} together.
Cc: Laurent Vivier
Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON")
Buglink: https://bugs.launchpad.net/bugs/1922617
Sign
The log2_esize parameter is not used except trivially.
Drop the parameter and the deferral to gen_mte_check1.
This fixes a bug in that the parameters as documented
in the header file were the reverse from those in the
implementation. Which meant that translate-sve.c was
passing the parameters in
The mte_check1 and mte_checkN functions are now identical.
Drop mte_check1 and rename mte_checkN to mte_check.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 3 +--
target/arm/internals.h | 5 +
target/arm/mte_helper.c| 26 +++---
target/arm/s
Buglink: https://bugs.launchpad.net/bugs/1921948
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/mte-5.c | 44 +++
tests/tcg/aarch64/Makefile.target | 2 +-
2 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/aarch64/mte-5.c
For consistency with the mte_check1 + mte_checkN merge
to mte_check, rename the probe function as well.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 +-
target/arm/mte_helper.c | 6 +++---
target/arm/sve_helper.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
d
We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags. But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses. So by the time we reach the
actual MTE check in the ARM pseudocode, all accesses are aligned.
Therefore, the first
We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags. But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses. So by the time we reach the
actual MTE check in the ARM pseudocode, all accesses are aligned.
We cannot tell a pri
After recent changes, mte_checkN does not use ESIZE,
and mte_check1 never used TSIZE. We can combine the
two into a single field: SIZEM1.
Choose to pass size - 1 because size == 0 is never used,
our immediate need in mte_probe_int is for the address
of the last byte (ptr + size - 1), and since al
Using mprotect() to change PROT_* does not change the MAP_ANON
previously set with mmap(). Our linux-user version of MTE only
works with MAP_ANON pages, so losing PAGE_ANON caused MTE to
stop working.
Reported-by: Stephen Long
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/mte.h
Split out a helper function from mte_checkN to perform
all of the checking and address manpulation. So far,
just use this in mte_checkN itself.
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 52 +++--
1 file changed, 40 insertions(+), 12 delet
We can remove PAGE_WRITE when (internally) marking a page
read-only because it contains translated code.
This can be triggered by tests/tcg/aarch64/bti-2, after
having serviced SIGILL trampolines on the stack.
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 2 +-
1 file changed,
Now that mte_check1 and mte_checkN have been merged, we can
merge sve_cont_ldst_mte_check1 and sve_cont_ldst_mte_checkN.
Which means that we can eliminate the function pointer into
sve_ldN_r and sve_stN_r, calling sve_cont_ldst_mte_check directly.
Signed-off-by: Richard Henderson
---
target/arm
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