Instead of delaying tcg_region_init until after tcg_prologue_init
is complete, do tcg_region_init first and let tcg_prologue_init
shrink the first region by the size of the generated prologue.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 11 -
Remove the ifdef ladder and move each define into the
appropriate header file.
Signed-off-by: Richard Henderson
---
v2: Retain comment about M_C_G_B_S constraint (balaton)
---
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 2 ++
Supercedes: <20210314212724.1917075-1-richard.hender...@linaro.org>
("tcg: Workaround macOS 11.2 mprotect bug")
Since I ran out of time at softfreeze, I put in a much smaller
patch to workaround the macOS bug. But I think the cleanup is
still a good thing.
r~
Richard Henderson (28):
meson:
On Sun, 2 May 2021 at 21:31, Philippe Mathieu-Daudé wrote:
>
> The OR_IRQ device is bus-less, thus isn't reset automatically.
> Manually reset the OR IRQs in the armsse_reset() handler.
>
> Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
> Signed-off-by: Philippe Mathieu-Daudé
On Sun, 2 May 2021 at 21:31, Philippe Mathieu-Daudé wrote:
>
> The OR_IRQ device is bus-less, thus isn't reset automatically.
> Add the raven_pcihost_reset() handler to manually reset the OR IRQ.
>
> Fixes: f40b83a4e31 ("40p: use OR gate to wire up raven PCI interrupts")
> Signed-off-by: Philippe
On Sun, 2 May 2021 at 21:31, Philippe Mathieu-Daudé wrote:
>
> The TYPE_NAND device is bus-less, thus isn't reset automatically.
> Register a reset handler to get reset with the machine.
>
> Fixed: 7426aa72c36 ("nand: Don't inherit from Sysbus")
> Signed-off-by: Philippe Mathieu-Daudé
> ---
The OR_IRQ device is bus-less, thus isn't reset automatically.
Add the raven_pcihost_reset() handler to manually reset the OR IRQ.
Fixes: f40b83a4e31 ("40p: use OR gate to wire up raven PCI interrupts")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/prep.c | 11 +++
1 file
The OR_IRQ device is bus-less, thus isn't reset automatically.
Manually reset the OR IRQs in the armsse_reset() handler.
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/armsse.c | 4
1 file changed, 4 insertions(+)
diff
The TYPE_NAND device is bus-less, thus isn't reset automatically.
Register a reset handler to get reset with the machine.
Fixed: 7426aa72c36 ("nand: Don't inherit from Sysbus")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/nand.c | 14 ++
1 file changed, 14 insertions(+)
diff
Hi,
This series is the result of a code audit of the DeviceClass::reset()
method uses, having Markus following explanation in mind [1]:
"Propagating reset from the root of the qtree to the leaves
won't reach a bus-less device, because the qtree contains
only the devices that plug into a
ping?
On 4/25/21 12:41 AM, Philippe Mathieu-Daudé wrote:
> Not all targets use USB: allow the build system to not
> build it if not selected.
>
> Philippe Mathieu-Daudé (2):
> hw/usb/host-stub: Remove unused header
> hw/usb: Do not build USB subsystem if not required
>
> hw/usb/host-stub.c
Signed-off-by: Michael Rolnik
---
hw/avr/Kconfig| 1 +
hw/avr/atmega.c | 15 ++-
hw/avr/atmega.h | 2 +
hw/watchdog/Kconfig | 3 +
hw/watchdog/avr_wdt.c | 190 ++
hw/watchdog/meson.build |
1. Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks
Michael Rolnik (1):
1. Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks
Michael Rolnik (1):
1. Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks
Michael Rolnik (1):
Running the WDR opcode triggers a segfault:
$ cat > foo.S << EOF
> __start:
> wdr
> EOF
$ avr-gcc -nostdlib -nostartfiles -mmcu=avr6 foo.S -o foo.elf
$ qemu-system-avr -serial mon:stdio -nographic -no-reboot \
-M mega -bios foo.elf -d in_asm --singlestep
IN:
0x:
On 5/2/21 7:48 PM, Thomas Huth wrote:
> When compiling the s390-ccw bios with Clang, the compiler emits a warning:
>
> pc-bios/s390-ccw/main.c:210:5: warning: variable 'found' is used
> uninitialized
> whenever switch default is taken [-Wsometimes-uninitialized]
> default:
> ^~~
** Changed in: qemu
Status: Incomplete => New
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https://bugs.launchpad.net/bugs/1860575
Title:
qemu64 CPU model is incorrect
Status in QEMU:
New
Bug description:
At the
On 5/2/21 7:48 PM, Thomas Huth wrote:
> Clang unfortunately does not support generating code for the z900
> architecture level and starts with the z10 instead. Thus to be able
> to support compiling with Clang, we have to check for the supported
> compiler flags. The disadvantage is of course that
Remove the sun4m_hwdefs[] array by moving assigning the
structure fields directly in each machine class_init()
function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 245 ++-
1 file changed, 112 insertions(+), 133 deletions(-)
diff
Factor out the class_init code common to all machines
to sun4m_machine_class_init().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 103 ---
1 file changed, 8 insertions(+), 95 deletions(-)
diff --git a/hw/sparc/sun4m.c
Introduce the TYPE_SUN4M_MACHINE and have all sun4m
machines inherit it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 30 +-
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index a625c41cd37..956216591b0 100644
--- a/hw/sparc/sun4m.c
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 100 +--
1 file changed, 36 insertions(+), 64 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 56f927e66ca..a625c41cd37 100644
--- a/hw/sparc/sun4m.c
+++
Instead of passing the sun4m_hwdef structure via
machine_init(), store it into the MachineClass.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 50 +---
1 file changed, 39 insertions(+), 11 deletions(-)
diff --git a/hw/sparc/sun4m.c
Hi Mark,
This series QOM'ify the sun4m machines.
I need it for a further memory maxsize check.
It is mostly code movement (and the diff-stat is good).
Since v1:
- Full rewrite after Mark review
Philippe Mathieu-Daudé (6):
hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE
The QEMU project is currently considering to move its bug tracking to
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and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
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and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
Le 02/05/2021 à 18:27, Philippe Mathieu-Daudé a écrit :
> Hi Laurent, could you take this patch via your Trivial tree please?
>
> On 4/8/21 12:30 AM, Philippe Mathieu-Daudé wrote:
>> We check the amount of RAM is enough, warn when it is
>> not, but if so we neglect to bail out. Fix that by
>>
Since everything now boots fine for you, I think we can close this
ticket now, right? If not, feel free to open again.
** Changed in: qemu
Status: New => Invalid
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The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
If you still think this bug report here is valid, then please switch
the
If I got that right, this has been fixed by this commit here:
https://gitlab.com/qemu-project/qemu/-/commit/8d745875c28528a3015
... so I'm closing this now. If you disagree, feel free to open it again.
** Changed in: qemu
Status: New => Fix Released
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The QEMU project is currently considering to move its bug tracking to
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and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.
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the
FWIW, seems like Peter's patch got included here:
https://gitlab.com/qemu-project/qemu/-/commit/5b30c53041d8f4c26ed3cf
... but I guess we still need a patch for the Networking section?
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The cc-option macro is not doing what it should - compared with the
original from the rules.mak file that got removed with commit
660f793093 ("Makefile: inline the relevant parts of rules.mak"),
the arguments got changed and thus the macro is rather doubling
the QEMU_CFLAGS than adding the flag
From: Philippe Mathieu-Daudé
When building on Fedora 34 (gcc version 11.0.0 20210210) we get:
In file included from pc-bios/s390-ccw/main.c:11:
In function ‘memset’,
inlined from ‘boot_setup’ at pc-bios/s390-ccw/main.c:185:5,
inlined from ‘main’ at pc-bios/s390-ccw/main.c:288:5:
When compiling the s390-ccw bios with Clang, the compiler emits a warning:
pc-bios/s390-ccw/main.c:210:5: warning: variable 'found' is used uninitialized
whenever switch default is taken [-Wsometimes-uninitialized]
default:
^~~
pc-bios/s390-ccw/main.c:214:16: note: uninitialized
Clang unfortunately does not support generating code for the z900
architecture level and starts with the z10 instead. Thus to be able
to support compiling with Clang, we have to check for the supported
compiler flags. The disadvantage is of course that the bios image
will only run with z10 guest
Clang can provide some additional warnings compared to GCC which can
sometimes help to catch some more bugs. So it would be good to be
able to build the s390-ccw bios with Clang, too. Only caveat: Clang
does not support the z900 anymore which is the lowest guest CPU that
could be used in QEMU, so
On 5/2/21 1:20 PM, Mark Cave-Ayland wrote:
> On 07/04/2021 18:53, Philippe Mathieu-Daudé wrote:
>
>> Hi Mark,
>>
>> This series QOM'ify a bit more the sun4m machines.
>> I need it for a further memory maxsize check.
>> It is mostly code movement (and the diff-stat is good).
>>
>> Philippe
TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).
Convert the generic reset to a enter/hold resettable ones, and
remove the qemu_register_reset() call.
Signed-off-by: Philippe
Remove qemu_register_reset() when a qdev type has a qbus parent,
implementing the 3-phase Resettable interface.
Since v2:
- Lower IRQ in 'hold' phase, not 'exit' one (Edgar)
Since v1:
- Use 3-phase reset interface instead of qdev one (Laurent)
Supersedes:
Hi Peter,
Could you take this patch via the ARM tree?
It has been reviewed twice.
Thanks,
Phil.
On 4/8/21 12:56 AM, Philippe Mathieu-Daudé wrote:
> The i.MX25 PDK board has 2 banks for SDRAM, each can
> address up to 256 MiB. So the total RAM usable for this
> board is 512M. When we ask for
Hi Laurent, could you take this patch via your Trivial tree please?
On 4/8/21 12:30 AM, Philippe Mathieu-Daudé wrote:
> We check the amount of RAM is enough, warn when it is
> not, but if so we neglect to bail out. Fix that by
> adding the missing exit() call.
>
> Fixes: bda19d7bb56 ("hw/rx: Add
Patchew URL: https://patchew.org/QEMU/20210502161538.534038-1-f4...@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210502161538.534038-1-f4...@amsat.org
Subject: [PULL 00/36] MIPS patches for 2021-05-02
ping?
On 4/22/21 8:41 AM, Philippe Mathieu-Daudé wrote:
> include/exec/gen-icount.h is listed as unmaintained.
> Add it to Main Loop (or should it be TCG? softmmu/icount.c
> is already there).
>
> Add the missing "exec/exec-all.h" header.
>
> Philippe Mathieu-Daudé (2):
> MAINTAINERS: Add
Move TLB management helpers to tcg/sysemu/tlb_helper.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-26-f4...@amsat.org>
---
target/mips/helper.h| 10 -
target/mips/internal.h | 7 -
Move the Special opcodes helpers to tcg/sysemu/special_helper.c.
Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()
Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.
TYPE_MC146818_RTC is an ISA device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).
We have 2 reset() methods: a generic one and the qdev one.
Merge them into a reset_enter handler (keeping the IRQ lowering
to a
mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-21-f4...@amsat.org>
---
target/mips/internal.h | 3 ---
target/mips/tcg/tcg-internal.h | 2
Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.
Update the KVM MIPS entry in MAINTAINERS.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-17-f4...@amsat.org>
---
target/mips/{ => sysemu}/addr.c
We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.
To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe
On 4/21/21 11:41 PM, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (2):
MAINTAINERS: Add include/exec/gen-icount.h to 'Main Loop' section
exec/gen-icount.h: Add missing "exec/exec-all.h" include
Queued, thanks.
r~
tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().
Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.
This will allow us to restrict tlb_helper.c to sysemu.
Reviewed-by: Richard Henderson
Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).
Only build the mips64el target which is known to work
and has users.
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
Reviewed-by: Willian Rampazzo
Signed-off-by: Philippe
The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-23-f4...@amsat.org>
---
target/mips/internal.h | 6 --
Currently cpu_mips_translate_address() calls raise_mmu_exception(),
and do_translate_address() calls cpu_loop_exit_restore().
This API split is dangerous, we could call cpu_mips_translate_address
without returning to the main loop.
As there is only one caller, it is trivial (and safer) to merge
To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.
The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard
Since all entries are no more than 4 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 4 const char.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
The #ifdef'ry hides that the user-mode implementation of
mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE.
Add this simple implementation to tcg/user/tlb_helper.c, and
the corresponding Meson machinery to build this file when user
emulation is configured.
Reviewed-by: Richard
Only the malta and loongson3-virt machines support KVM.
Restrict the other machines to TCG:
- mipssim
- magnum
- pica61
- fuloong2e
- boston
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-30-f4...@amsat.org>
---
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-27-f4...@amsat.org>
---
target/mips/internal.h | 13 ---
target/mips/tcg/tcg-internal.h | 14 +++
target/mips/cpu.c | 113 --
We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-2-f4...@amsat.org>
---
target/mips/meson.build | 5 ++---
We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-28-f4...@amsat.org>
---
target/mips/internal.h | 9 +--
Move helper_cache() to tcg/sysemu/special_helper.c.
The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub helper to satisfy linking,
which abort if ever called.
Reviewed-by: Richard
To avoid callers to emit dead code if check_cp0_enabled()
raise an exception, let it return a boolean value, whether
CP0 is enabled or not.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'target_user_arch' set for user emulation.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.
Move the opcode definitions to tcg/sysemu_helper.h.inc.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-20-f4...@amsat.org>
---
When running with '-d unimp' all MTHC0 opcode executed
are logged as unimplemented... Add the proper 'return'
statement missed from commit 5204ea79ea7.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210422081055.2349216-1-f4...@amsat.org>
---
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-19-f4...@amsat.org>
---
target/mips/internal.h | 4
target/mips/tcg/tcg-internal.h | 9 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-11-f4...@amsat.org>
---
target/mips/ldst_helper.c | 288 ++
target/mips/op_helper.c | 259 --
target/mips/meson.build |
Rename set_pc() as mips_env_set_pc(), declare it inlined
and use it in cpu.c and op_helper.c.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210428170410.479308-9-f4...@amsat.org>
---
target/mips/internal.h | 10 ++
Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":
The Read/Write Previous GPR opcodes "require CP0 privilege".
Add the missing CP0 checks.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-18-f4...@amsat.org>
---
target/mips/internal.h |
Turn printfpr() macro into a proper function: fpu_dump_fpr().
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-8-f4...@amsat.org>
---
target/mips/cpu.c | 50 ++-
The CPU/FPU regnames[] arrays is used in mips_tcg_init() and
mips_cpu_dump_state(), which while being in translate.c is
not specific to TCG.
To be able to move mips_cpu_dump_state() to cpu.c, which is
compiled for all accelerator, we need to make the regnames[]
arrays global to target/mips/ by
Add various missing fields to the CPU migration vmstate:
- CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03)
- CMGCRBase (c870e3f52ca 2016-03-15)
- CP0_ErrCtl(0d74a222c27 2016-03-25)
- MXU GPR[] & CR
As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe
mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.
Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.
Reviewed-by: Richard
Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller")
the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias.
Use this alias to get IRQ for the power management PCI function.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson
restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.
kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.
Except this tiny
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