On Wed, Jun 16, 2021 at 7:29 PM Lukas Jünger
wrote:
>
> This QOMifies the SiFive UART model. Migration and reset have been
> implemented.
>
> Signed-off-by: Lukas Jünger
> Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/char/sifive_uart.h | 11 ++--
> hw/cha
On Sun, Jun 13, 2021 at 2:09 AM Anup Patel wrote:
>
> The RISC-V ACLINT is more modular and backward compatible with
> original SiFive CLINT so instead of duplicating the orignal
> SiFive CLINT implementation we upgrade the current SiFive CLINT
> implementation to RISC-V ACLINT implementation.
>
>
On Tue, Jun 15, 2021 at 6:51 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Since commit 605def65 ("target/riscv: Use the RISCVException enum for CSR
> operations")
> the CSR predicate() function was changed to return RISCV_EXCP_NONE
> instead of 0 for a valid CSR, but it forgot to update the dyn
On Mon, Jun 14, 2021 at 6:54 PM Richard Henderson
wrote:
>
> TCG_TARGET_HAS_MEMORY_BSWAP is already unset for this backend,
> which means that MO_BSWAP be handled by the middle-end and
> will never be seen by the backend. Thus the indexes used with
> qemu_{ld,st}_helpers will always be zero.
>
>
Hi Mark,
On Wed, 16 Jun 2021, Mark Cave-Ayland wrote:
> On 16/06/2021 04:09, Finn Thain wrote:
>
> > With "qemu-system-mips -M magnum ..." I was able to boot both Linux
> > and NetBSD. That was after commit 89ae0ff9b7 ("net/dp8393x: add PROM
> > to store MAC address"). But that's not to say th
Eduardo Habkost writes:
> On Thu, Jun 17, 2021 at 05:53:11PM +0200, Claudio Fontana wrote:
>> On 6/17/21 5:39 PM, Valeriy Vdovin wrote:
>> > On Thu, Jun 17, 2021 at 04:14:17PM +0200, Markus Armbruster wrote:
>> >> Claudio Fontana writes:
>> >>
>> >>> On 6/17/21 1:09 PM, Markus Armbruster wrote:
Add module annotations for tcg so autoloading works.
Signed-off-by: Gerd Hoffmann
---
accel/tcg/tcg-accel-ops.c | 1 +
accel/tcg/tcg-all.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 7191315aeed4..1a8e8390bd60 100644
---
Add module annotations for qtest so autoloading works.
Signed-off-by: Gerd Hoffmann
---
accel/qtest/qtest.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index edb29f6fa4c0..7e6b8110d52b 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
Call module_object_class_by_name() instead of object_class_by_name()
for objects possibly implemented as module
Signed-off-by: Gerd Hoffmann
---
accel/accel-common.c | 2 +-
accel/accel-softmmu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/accel-common.c b/accel
One for module load and one for qom type lookup.
Signed-off-by: Gerd Hoffmann
---
util/module.c | 3 +++
util/trace-events | 4
2 files changed, 7 insertions(+)
diff --git a/util/module.c b/util/module.c
index a9ec2da9972e..acaaecad56c9 100644
--- a/util/module.c
+++ b/util/module.c
@@
Use module database to figure which module adds given QemuOpts group.
Signed-off-by: Gerd Hoffmann
---
softmmu/vl.c| 17 -
stubs/module-opts.c | 4
util/module.c | 19 +++
3 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/softmmu
Use module database to figure which module implements a given QOM type.
Drop hard-coded object list.
Signed-off-by: Gerd Hoffmann
---
util/module.c | 77 ---
1 file changed, 24 insertions(+), 53 deletions(-)
diff --git a/util/module.c b/util/modul
Signed-off-by: Gerd Hoffmann
---
block/iscsi-opts.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/iscsi-opts.c b/block/iscsi-opts.c
index afaf8837d6c1..4f2da405e645 100644
--- a/block/iscsi-opts.c
+++ b/block/iscsi-opts.c
@@ -68,3 +68,4 @@ static void iscsi_block_opts_init(void)
}
Use module database for module dependencies.
Drop hard-coded dependency list.
Signed-off-by: Gerd Hoffmann
---
util/module.c | 55 ---
1 file changed, 21 insertions(+), 34 deletions(-)
diff --git a/util/module.c b/util/module.c
index 8d3e8275b9f7.
Signed-off-by: Gerd Hoffmann
---
hw/s390x/virtio-ccw-gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/s390x/virtio-ccw-gpu.c b/hw/s390x/virtio-ccw-gpu.c
index 75a9e4bb3908..5868a2a07093 100644
--- a/hw/s390x/virtio-ccw-gpu.c
+++ b/hw/s390x/virtio-ccw-gpu.c
@@ -59,6 +59,7 @@ static
Signed-off-by: Gerd Hoffmann
---
ui/egl-headless.c | 4
ui/gtk.c | 4
ui/sdl2.c | 4
ui/spice-app.c| 3 +++
ui/spice-core.c | 5 +
5 files changed, 20 insertions(+)
diff --git a/ui/egl-headless.c b/ui/egl-headless.c
index da377a74af69..75404e0e8700 10064
Build tcg accel ops as module.
Which is only a small fraction of tcg.
Also only x86 for now.
Signed-off-by: Gerd Hoffmann
---
accel/tcg/meson.build | 5 -
meson.build | 14 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/meson.build b/accel
Signed-off-by: Gerd Hoffmann
---
hw/display/vhost-user-gpu-pci.c | 1 +
hw/display/vhost-user-gpu.c | 1 +
hw/display/vhost-user-vga.c | 1 +
hw/display/virtio-gpu-base.c| 1 +
hw/display/virtio-gpu-gl.c | 3 +++
hw/display/virtio-gpu-pci-gl.c | 3 +++
hw/display/virtio-gpu-pci.
Allow building accelerators as module.
Start with qtest as first user.
Signed-off-by: Gerd Hoffmann
---
accel/qtest/meson.build | 8 ++--
meson.build | 6 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/accel/qtest/meson.build b/accel/qtest/meson.build
index
Signed-off-by: Gerd Hoffmann
---
hw/usb/ccid-card-emulated.c | 1 +
hw/usb/ccid-card-passthru.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c
index 5c76bed77aa0..6c8c0355e099 100644
--- a/hw/usb/ccid-card-emulated.c
+++ b/hw/usb/cc
Add module_allow_arch() to set the target architecture.
In case a module is limited to some arch verify arches
match and ignore the module if not.
Signed-off-by: Gerd Hoffmann
---
include/qemu/module.h | 1 +
softmmu/vl.c | 3 +++
util/module.c | 29 +++
Signed-off-by: Gerd Hoffmann
---
chardev/baum.c | 1 +
chardev/spice.c | 4
2 files changed, 5 insertions(+)
diff --git a/chardev/baum.c b/chardev/baum.c
index 5deca778bc44..79d618e35045 100644
--- a/chardev/baum.c
+++ b/chardev/baum.c
@@ -680,6 +680,7 @@ static const TypeInfo char_braille
Signed-off-by: Gerd Hoffmann
---
meson.build | 36
1 file changed, 36 insertions(+)
diff --git a/meson.build b/meson.build
index 9cf50a50d39a..e822477a231a 100644
--- a/meson.build
+++ b/meson.build
@@ -1781,6 +1781,7 @@ user_ss = ss.source_set()
util_ss = s
Add script to generate C source with a small
database containing the module meta-data.
Signed-off-by: Gerd Hoffmann
---
scripts/modinfo-generate.py | 84 +
include/qemu/module.h | 17
softmmu/vl.c| 4 ++
util/module.c
Signed-off-by: Gerd Hoffmann
---
hw/usb/redirect.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index 6a75b0dc4ab2..4ec9326e0582 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -2608,6 +2608,7 @@ static const TypeInfo usbredir_dev_info = {
Signed-off-by: Gerd Hoffmann
---
hw/display/qxl.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index 6e1f8ff1b2a7..84f99088e0a0 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -2522,6 +2522,7 @@ static const TypeInfo qxl_primary_info = {
Add script to collect the module meta-data from the source code,
store the results in *.modinfo files.
Signed-off-by: Gerd Hoffmann
---
scripts/modinfo-collect.py | 67 ++
meson.build| 11 +++
2 files changed, 78 insertions(+)
create mode
With target-specific modules we can have multiple modules implementing
the same object. Therefore we have to check the target arch on lookup
to find the correct module.
Signed-off-by: Gerd Hoffmann
---
util/module.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/util/module.c b/util/
Signed-off-by: Gerd Hoffmann
---
audio/spiceaudio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/audio/spiceaudio.c b/audio/spiceaudio.c
index 999bfbde47c5..a8d370fe6f31 100644
--- a/audio/spiceaudio.c
+++ b/audio/spiceaudio.c
@@ -317,3 +317,5 @@ static void register_audio_spice(void)
This patch series adds support for module meta-data. Today this is
either hard-coded in qemu (see qemu_load_module_for_opts) or handled
with manually maintained lists in util/module (see module_deps[] and
qom_modules[]). This series replaced that scheme with annotation
macros, so the meta-data ca
Add macros for module info annotations.
Instead of having that module meta-data stored in lists in util/module.c
place directly in the module source code.
Signed-off-by: Gerd Hoffmann
---
include/qemu/module.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/includ
On 6/17/21 21:29, BALATON Zoltan wrote:
On Thu, 17 Jun 2021, Alexey Kardashevskiy wrote:
On 17/06/2021 19:16, BALATON Zoltan wrote:
On Thu, 17 Jun 2021, Alexey Kardashevskiy wrote:
On 16/06/2021 20:34, BALATON Zoltan wrote:
On Wed, 16 Jun 2021, Alexey Kardashevskiy wrote:
On 6/15/21 20:29
On 5/18/21 9:33 AM, Zhang, Chen wrote:
-Original Message-
From: Lukas Straub
Sent: Tuesday, May 18, 2021 3:47 AM
To: Rao, Lei
Cc: Zhang, Chen ; lizhij...@cn.fujitsu.com;
jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
pbonz...@redhat.com; qemu-devel@nongnu.org
Subject
On Thu, Jun 17, 2021 at 04:15:18PM +0200, Greg Kurz wrote:
> A well behaved FUSE client uses FUSE_CREATE to create files. It isn't
> supposed to pass O_CREAT along a FUSE_OPEN request, as documented in
> the "fuse_lowlevel.h" header :
>
> /**
> * Open a file
> *
> * Open flags a
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss wrote:
>
> New mini-kernel test for STM32VLDISCOVERY USART1.
>
> Signed-off-by: Alexandre Iooss
Acked-by: Alistair Francis
Alistair
> ---
> tests/qtest/boot-serial-test.c | 37 ++
> 1 file changed, 37 insertions(
On Wed, Jun 16, 2021 at 11:22 AM Richard Henderson
wrote:
>
> Create and record the rt signal trampoline.
>
> This fixes a bug wrt libgcc fallback unwinding. It expects
> the stack pointer to point to the siginfo_t, whereas we had
> inexplicably placed our private signal trampoline at the start
>
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss wrote:
>
> This adds the target guide for Netduino 2, Netduino Plus 2 and
> STM32VLDISCOVERY.
>
> Signed-off-by: Alexandre Iooss
Reviewed-by: Alistair Francis
Alistair
> ---
> MAINTAINERS| 1 +
> docs/system/arm/stm32.rst | 6
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss wrote:
>
> This is a Cortex-M3 based machine. Information can be found at:
> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>
> Signed-off-by: Alexandre Iooss
Reviewed-by: Alistair Francis
Alistair
> ---
> MAINTAINERS
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss wrote:
>
> This SoC is similar to stm32f205 SoC.
> This will be used by the STM32VLDISCOVERY to create a machine.
>
> Signed-off-by: Alexandre Iooss
Please keep any Reviewed by tags for a patch between versions if you
don't make large changes.
Rev
在 2021/6/17 23:34, Peter Xu 写道:
On Thu, Jun 17, 2021 at 10:12:07PM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
since main thread may "query dirty rate" at any time, it's better
to move init step into main thead so that synchronization overhead
between "main" and "get_dirtyr
在 2021/6/17 23:29, Peter Xu 写道:
On Thu, Jun 17, 2021 at 10:12:04PM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
dirty rate measurement may start or stop dirty tracking during
calculation. this conflict with migration because stop dirty
tracking make migration leave dirty pag
在 2021/6/17 23:29, Peter Xu 写道:
On Thu, Jun 17, 2021 at 10:12:04PM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
dirty rate measurement may start or stop dirty tracking during
calculation. this conflict with migration because stop dirty
tracking make migration leave dirty pag
在 2021/6/17 23:27, Peter Xu 写道:
On Thu, Jun 17, 2021 at 10:12:05PM +0800, huang...@chinatelecom.cn wrote:
##
+# @DirtyRateMeasureMode:
+#
+# An enumeration of mode of measuring dirtyrate.
+#
+# @page-sampling: calculate dirtyrate by sampling pages.
+#
+# @dirty-ring: calculate dirtyrate by
On Thu, 17 Jun 2021, Philippe Mathieu-Daudé wrote:
To ease reviewing code using the I2C bus API, introduce the
i2c_start_recv() and i2c_start_send() helpers which don't
take the confusing 'is_recv' boolean argument.
In defence of this is_recv I'd like to mention that I2C has such a bit in
devi
On Thu, 17 Jun 2021, Philippe Mathieu-Daudé wrote:
To allow further simplications, extract i2c_do_start_transfer()
from i2c_start_transfer(). This is mostly the same function,
but the former is static and takes an enum argument.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Dau
On Wed, 16 Jun 2021, Philippe Mathieu-Daudé wrote:
On 6/16/21 10:01 PM, BALATON Zoltan wrote:
On Wed, 16 Jun 2021, Philippe Mathieu-Daudé wrote:
On 6/16/21 9:16 PM, Corey Minyard wrote:
On Wed, Jun 16, 2021 at 06:14:11PM +0200, Philippe Mathieu-Daudé wrote:
Instead of using the confuse i2c_se
On Thu, 17 Jun 2021, Philippe Mathieu-Daudé wrote:
Instead of using the confuse i2c_send_recv(), rewrite to directly
call i2c_recv() & i2c_send(), resulting in code easier to review.
Reviewed-by: Richard Henderson
Acked-by: Corey Minyard
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BA
On Thu, 17 Jun 2021, Philippe Mathieu-Daudé wrote:
Instead of using the confuse i2c_send_recv(), rewrite to directly
call i2c_recv() & i2c_send(), resulting in code easier to review.
Reviewed-by: Richard Henderson
Acked-by: Corey Minyard
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BA
Conny, et al,
Here is a quick update to the series for fixing passthrough
sense data in the irb, using a subchannel-specific callback.
As before, the first three patches are code refactoring.
Since patch 3 doesn't implement the callback for vfio-ccw
subchannels, it fixes the problem encountered w
Wire in the subchannel callback for building the IRB
ESW and ECW space for passthrough devices, and copy
the hardware's ESW into the IRB we are building.
If the hardware presented concurrent sense, then copy
that sense data into the IRB's ECW space.
Signed-off-by: Eric Farman
---
hw/s390x/css.c
The Interrupt Response Block is comprised of several other
structures concatenated together, but only the 12-byte
Subchannel-Status Word (SCSW) is defined as a proper struct.
Everything else is a simple array of 32-bit words.
Let's define a proper struct for the 20-byte Extended-Status
Word (ESW)
Let's move this logic into its own routine,
so it can be reused later.
Signed-off-by: Eric Farman
Reviewed-by: Thomas Huth
---
hw/s390x/css.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 59d935570e..a54e384566 100
Currently, all subchannel types have "sense data" copied into
the IRB.ECW space, and a couple flags enabled in the IRB.SCSW
and IRB.ESW. But for passthrough (vfio-ccw) subchannels,
this data isn't populated in the first place, so enabling
those flags leads to unexpected behavior if the guest tries
Previously the store-conditional code was writing to hex_pred[prednum].
Then, the fGEN_TCG override was reading from there to the destination
variable so that the packet commit logic would handle it properly.
The correct implementation is to write to the destination variable
and don't have the ext
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c| 6 --
target/hexagon/translate.c | 11 ++-
2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index bd18cb1..5dbabe0 100644
--
Change fLSBNEW/fLSBNEW0/fLSBNEW1 from copy to "x & 1"
Remove gen_logical_not function
Clean up fLSBNEWNOT to use andi-1 followed by xori-1
Test cases added to tests/tcg/hexagon/misc.c
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h| 27 ++---
Y4_l2fetch == l2fetch(Rs32, Rt32)
Y5_l2fetch == l2fetch(Rs32, Rtt32)
The semantics for these instructions are present, but the encodings
are missing.
Note that these are treated as nops in qemu, so we add overrides.
Test case added to tests/tcg/hexagon/misc.c
Reviewed-by: Richard Henderson >
Si
On Wed, Jun 16, 2021 at 03:38:13PM +0200, Max Reitz wrote:
> On 11.06.21 22:04, Vivek Goyal wrote:
> > On Wed, Jun 09, 2021 at 05:55:49PM +0200, Max Reitz wrote:
> > > Currently, lo_inode.fhandle is always NULL and so always keep an O_PATH
> > > FD in lo_inode.fd. Therefore, when the respective in
On Thu, Jun 17, 2021 at 09:07:32PM +0200, Julia Suvorova wrote:
> The patch set consists of two parts:
> patches 1-4: introduce new feature
> 'acpi-pci-hotplug-with-bridge-support' on Q35
> patches 5-7: make the feature default along with changes in ACPI tables
>
> With the feature di
On Thu, Jun 17, 2021 at 09:07:36PM +0200, Julia Suvorova wrote:
> Instead of changing the hot-plug type in _OSC register, do not
> set the 'Hot-Plug Capable' flag. This way guest will choose ACPI
> hot-plug if it is preferred and leave the option to use SHPC with
> pcie-pci-bridge.
>
> The ability
On Wed, Jun 16, 2021 at 10:43:05PM +0200, Philippe Mathieu-Daudé wrote:
> Hi,
>
> While testing James & Dov patch:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg810571.html
> I wasted some time trying to figure out how OVMF was supposed to
> behave until realizing the binary I was using
On Wed, Jun 16, 2021 at 10:43:25PM +0200, Philippe Mathieu-Daudé wrote:
> ACPI core routines (in core.c) are not really x86-specific.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/acpi/meson.build | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/acpi/meson.bu
On Thu, Jun 17, 2021 at 3:17 PM Dov Murik wrote:
>
>
>
> On 17/06/2021 20:22, Eduardo Habkost wrote:
> > On Thu, Jun 17, 2021 at 03:48:52PM +0300, Dov Murik wrote:
> >>
> >>
> >> On 15/06/2021 22:53, Philippe Mathieu-Daudé wrote:
> >>> Hi Dov, James,
> >>>
> >>> +Connor who asked to be reviewer.
>
On 6/17/21 8:01 PM, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> On 6/4/21 8:52 AM, Alex Bennée wrote:
>>> From: Claudio Fontana
>>> Cortex-A15 is the only ARM cpu class we need in KVM too.
>>> We will be able to move it to tcg/ once the board code and
>>> configurations
>>> are fixed.
Using a custom timeout is useful to continue fuzzing complex devices,
even after we run into some slow code-path. However, simply adding a
fixed timeout to each input effectively caps the maximum input
length/number of operations at some artificial value. There are two
major problems with this:
1.
Hello,
These patches
1.) Change generic-fuzzer timeouts so they are reconfigured prior to
each individual IO command, to allow for longer-running inputs
2.) Add an instrumentation filter to prevent libfuzzer from tracking
noisy/irrelevant parts of the code.
3.) Fix the AC97 and ES1370 fuzzer config
TYPE_ES1370 is "ES1370", capitalized. Fix the config to account for
that.
Signed-off-by: Alexander Bulekov
---
tests/qtest/fuzz/generic_fuzz_configs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/fuzz/generic_fuzz_configs.h
b/tests/qtest/fuzz/generic_fuzz_conf
Add ACPI hot-plug registers to DSDT Q35 tables.
Changes in the tables:
+Scope (_SB.PCI0)
+{
+OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)
+Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+{
+PCIU, 32,
+PCID, 32
+}
+
+Operat
By default, -fsanitize=fuzzer instruments all code with coverage
information. However, this means that libfuzzer will track coverage over
hundreds of source files that are unrelated to virtual-devices. This
means that libfuzzer will optimize inputs for coverage observed in timer
code, memory APIs e
TYPE_AC97 is "AC97", capitalized. Fix the config to account for that.
Signed-off-by: Alexander Bulekov
---
tests/qtest/fuzz/generic_fuzz_configs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/fuzz/generic_fuzz_configs.h
b/tests/qtest/fuzz/generic_fuzz_configs.
On 17/06/2021 18.56, Alexandre Iooss wrote:
New mini-kernel test for STM32VLDISCOVERY USART1.
Signed-off-by: Alexandre Iooss
---
tests/qtest/boot-serial-test.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest
Recently we added support of zstd to qcow2 format, as zstd seems to be
better than zlib in general, and which is important (as qcow2
compression used mostly for backups) compressed writes are faster with
zstd.
Let's add a build option to use zstd by default.
Signed-off-by: Vladimir Sementsov-Ogie
Instead of changing the hot-plug type in _OSC register, do not
set the 'Hot-Plug Capable' flag. This way guest will choose ACPI
hot-plug if it is preferred and leave the option to use SHPC with
pcie-pci-bridge.
The ability to control hot-plug for each downstream port is retained,
while 'hotplug=of
Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h| 4
include/hw/acpi/ich9.h | 2 ++
include/hw/acpi/pcihp.h | 3 ++-
hw/acpi/p
From: Klaus Jensen
Prior to this patch, the aios associated with broadcast format are
submitted anonymously (no aiocb reference saved from the blk_aio call).
Fix this by formatting the namespaces one after another, saving a
reference to the aiocb for each.
Signed-off-by: Klaus Jensen
---
hw/n
From: Klaus Jensen
Prior to this patch, the aios associated with zone reset are submitted
anonymously (no reference saved to the aiocb from the blk_aio call).
Fix this by resetting the zones one after another, saving a reference to
the aiocb for each reset.
Signed-off-by: Klaus Jensen
---
hw/
From: Klaus Jensen
Some commands report additional useful information in dw0 and dw1 of the
completion queue entry.
Add them to the trace.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 2 ++
hw/nvme/trace-events | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw
On Tue, 15 Jun 2021 at 18:01, Alex Bennée wrote:
>
> The previous numbers were a guess at best and rather arbitrary without
> taking into account anything that might be loaded. Instead of using
> guesses based on the state of registers implement a new function that
> scans MemoryRegions for the RA
From: Klaus Jensen
The nvme_check_prinfo() and nvme_dif_check() functions operate on the
16 bit "control" member of the NvmeCmd. These functions do not otherwise
operate on an NvmeCmd or an NvmeRequest, so change them to expect the
actual 4 bit PRINFO field and add constants that work on this fie
On Jun 7 11:47, Klaus Jensen wrote:
From: Klaus Jensen
Qiang Liu reported that an access on an unknown address is triggered in
memory_region_set_enabled because a check on CAP.PMRS is missing for the
PMRCTL register write when no PMR is configured.
Cc: qemu-sta...@nongnu.org
Fixes: 75c3c9de96
Q35 has three different types of PCI devices hot-plug: PCIe Native,
SHPC Native and ACPI hot-plug. This patch changes the default choice
for cold-plugged bridges from PCIe Native to ACPI Hot-plug with
ability to use SHPC and PCIe Native for hot-plugged bridges.
This is a list of the PCIe Native ho
All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h | 1 +
include/hw/acpi/ich9.h | 3 ++
hw/acpi/ich9.c | 67 +
From: Klaus Jensen
Pull the gist of nvme_check_dulbe() into a helper function. This is in
preparation for dsm refactoring.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 41 -
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/hw/nvme/ctrl
The patch set consists of two parts:
patches 1-4: introduce new feature
'acpi-pci-hotplug-with-bridge-support' on Q35
patches 5-7: make the feature default along with changes in ACPI tables
With the feature disabled Q35 falls back to the native hot-plug.
Pros
* no racy behavior d
PCI Express does not allow hot-plug on pcie.0. Check for Q35 in
acpi_pcihp_disable_root_bus() to be able to forbid hot-plug using the
'acpi-root-pci-hotplug' flag.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/acpi/pcihp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-
On 17/06/2021 20:22, Eduardo Habkost wrote:
> On Thu, Jun 17, 2021 at 03:48:52PM +0300, Dov Murik wrote:
>>
>>
>> On 15/06/2021 22:53, Philippe Mathieu-Daudé wrote:
>>> Hi Dov, James,
>>>
>>> +Connor who asked to be reviewer.
>>>
>>> On 6/15/21 5:20 PM, Eduardo Habkost wrote:
On Tue, May 25
From: Klaus Jensen
This partially reverts commit 98f84f5a4eca5c03e32fff20f246d9b4b96d6422.
Since all "multi aio" commands are now reimplemented to properly track
the nested aiocbs, we can revert the "hack" that was introduced to make
sure all requests we're properly drained upon sq deletion.
Th
From: Klaus Jensen
Make nvme_get_zone_by_slba() return NULL if the slba is out of range.
This allows the function to be used without guarding the call with a
call to nvme_check_bounds(), in preparation for the next patch.
Add asserts after calling nvme_get_zone_by_slba() instead.
Signed-off-by:
From: Klaus Jensen
Prior to this patch, a broadcast flush would result in submitting
multiple "fire and forget" aios (no reference saved to the aiocbs
returned from the blk_aio_flush calls).
Fix this by issuing the flushes one after another.
Signed-off-by: Klaus Jensen
---
hw/nvme/nvme.h
From: Klaus Jensen
Before this patch the code would issue several aios simultaneously
without saving a reference to the aiocb. Without the aiocb reference the
individual copies cannot be canceled.
Fix this by issuing copies of the ranges one after another.
Signed-off-by: Klaus Jensen
---
hw/n
From: Klaus Jensen
Prior to this patch, a loop was used to issue multiple "fire and forget"
aios for each range in the command. Without a reference to the aiocb
returned from the blk_aio_pdiscard calls, the aios cannot be canceled.
Fix this by processing the ranges one after another.
As a bonus
From: Klaus Jensen
This series reimplements flush, dsm, copy, zone reset and format nvm to
allow cancellation. I posted an RFC back in March ("hw/block/nvme:
convert ad-hoc aio tracking to aiocb") and I've applied some feedback
from Stefan and reimplemented the remaining commands.
The basic idea
From: Klaus Jensen
Prepare nvme_dif_pract_generate_dif() and nvme_dif_check() to be
callable in smaller increments by making the reftag a pointer parameter
updated by the function.
Signed-off-by: Klaus Jensen
---
hw/nvme/nvme.h | 4 ++--
hw/nvme/ctrl.c | 10 +-
hw/nvme/dif.c | 22 +++
From: Klaus Jensen
Jakub noticed[1] that, when using pin-based interrupts, the device will
unconditionally deasssert when any CQEs are acknowledged. However, the
pin should not be deasserted if other completion queues still holds
unacknowledged CQEs.
The bug is an artifact of commit ca247d35098d
On 6/17/21 8:44 PM, shashi.mall...@linaro.org wrote:
> Hi Andrey,
>
> The issue doesnt seem related to ITS patchset as the implementation has
> no changes around MTTCG or vCPU configurations.
>
> if this patchset were not applied(with only commit 3e9f48b),do you
> still see the hang issue?
No, I
On Jun 17 07:50, Keith Busch wrote:
On Thu, Jun 17, 2021 at 12:08:20PM +0200, Klaus Jensen wrote:
if (cq->tail != cq->head) {
+if (!pending) {
+n->cq_pending++;
+}
You should check cq->irq_enabled before incrementing cq_pending. You
don't want to leave the irq
17.06.2021 12:42, Peter Maydell wrote:
On Tue, 15 Jun 2021 at 21:50, Eric Blake wrote:
The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2:
Merge remote-tracking branch
'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14
15:59:13 +0100)
15.06.2021 23:47, Eric Blake wrote:
From: Vladimir Sementsov-Ogievskiy
block/nbd doesn't need underlying sioc channel anymore. So, we can
update nbd/client-connection interface to return only one top-most io
channel, which is more straight forward.
Signed-off-by: Vladimir Sementsov-Ogievskiy
On 6/17/21 7:49 PM, Philippe Mathieu-Daudé wrote:
> To be able to extract the DSP ASE translation routines to
> different source file, declare few TCG helpers, MASK_SPECIAL3
> and a DSP register in "translate.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/tcg/translate.h | 7
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