Frank Chang 於 2021年7月13日 週二 下午2:53寫道：
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new Selective Hardware Vectoring feature
>> that allow users to
On 2021/7/12 23:30, Daniel P. Berrangé wrote:
On Mon, Jul 12, 2021 at 05:00:48PM +0200, Andrew Jones wrote:
On Fri, Jul 02, 2021 at 06:07:35PM +0800, Yanan Wang wrote:
We currently perform zero-check (default the value to 1 if zeroed)
for the computed values of cores/threads, to make sure they
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
> res
On 2021/7/12 23:27, Andrew Jones wrote:
On Mon, Jul 12, 2021 at 05:05:43PM +0200, Andrew Jones wrote:
On Mon, Jul 12, 2021 at 05:04:04PM +0200, Andrew Jones wrote:
On Fri, Jul 02, 2021 at 06:07:36PM +0800, Yanan Wang wrote:
It's possible that dies parameter is explicitly specified as "dies=0"
The code mistakenly relied on address_space_translate to store the
length remaining until the next memory-region. We care about this
because when there is RAM or sparse-memory neighboring on an MMIO
region, we should only write up to the border, to prevent inadvertently
invoking MMIO handlers withi
We have some configs for devices such as the AC97 and ES1370 that were
not matching memory-regions correctly, because the configs provided
lowercase names. To resolve these problems and prevent them from
occurring again in the future, convert both the pattern and names to
lower-case, prior to check
Using a custom timeout is useful to continue fuzzing complex devices,
even after we run into some slow code-path. However, simply adding a
fixed timeout to each input effectively caps the maximum input
length/number of operations at some artificial value. There are two
major problems with this:
1.
Hello Paolo,
The following changes since commit 711c0418c8c1ce3a24346f058b001c4c5a2f0f81:
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210702' into staging
(2021-07-04 14:04:12 +0100)
are available in the Git repository at:
https://gitlab.com/a1xndr/qemu tags/pull-request-2021-
From: Klaus Jensen
The new PMR test unearthed a long-standing issue with MMIO reads on
big-endian hosts.
Fix by using the ldn_he_p helper instead of memcpy.
Cc: Gollu Appalanaidu
Reported-by: Peter Maydell
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 14 +++---
1 file changed, 7
On Mon, Jul 12, 2021 at 12:03:27PM +0100, Stefan Hajnoczi wrote:
> Why did you decide to implement -device nvme-mi as a device on
> TYPE_NVME_BUS? If the NVMe spec somehow requires this then I'm surprised
> that there's no NVMe bus interface (callbacks). It seems like this could
> just as easily be
On Fri, Jul 9, 2021 at 9:06 AM Alistair Francis
wrote:
>
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_plic.h | 4
> hw/intc/sifive_plic.c
Hello Stefan/all,
I was reading your blog post on the QEMU overall architecture (link - "
http://blog.vmsplice.net/2011/03/qemu-internals-overall-architecture-and.html";)
and I have a few questions with regards to executing I/O operations (block
I/O) in the middle of guest code execution.
I am ru
On Fri, Jul 9, 2021 at 9:06 AM Alistair Francis
wrote:
>
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_plic.h | 4
> hw/intc/sifive_plic.c
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
x86_64 cmpx
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
KVM interna
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
QEMU proces
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
qemu-img cr
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
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Title:
TCG: QEMU i
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Title:
User mode n
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
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Title:
-bios edk2-
[Expired for QEMU because there has been no activity for 60 days.]
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Title:
i386-linux-
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
qemu-system
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Title:
make check-
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Title:
qemu-i386 u
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Title:
qemu gdb wr
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Title:
Windows 10
On Fri, Jul 9, 2021 at 2:32 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 45 +++--
> 1 file changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/target/risc
On Fri, Jul 9, 2021 at 2:47 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 17 +
> 1 file changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/r
On Tue, Jul 13, 2021 at 02:42:04AM +0200, Julia Suvorova wrote:
> Q35 has three different types of PCI devices hot-plug: PCIe Native,
> SHPC Native and ACPI hot-plug. This patch changes the default choice
> for cold-plugged bridges from PCIe Native to ACPI Hot-plug with
> ability to use SHPC and PC
在 2021/7/13 上午7:58, Dongli Zhang 写道:
This patch is to implement the device specific interface to dump the
mapping between virtio queues and vectors.
(qemu) info msix -d /machine/peripheral/vscsi0
Msg L.Addr Msg U.Addr Msg Data Vect Ctrl
0xfee0 0x 0x4041 0x
0xfee0
On Fri, Jul 9, 2021 at 2:39 PM Richard Henderson
wrote:
>
> Narrow the scope of t0 in trans_jalr.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 25 ++---
> 1 file changed, 10 insertions(+), 15
在 2021/7/13 上午7:58, Dongli Zhang 写道:
While the previous patch is to dump the MSI-X table, sometimes we may
need to dump device specific data, e.g., to help match the vector with
the specific device queue.
This patch is to add the PCI device specific interface to help dump
those information. An
On Tue, Jul 13, 2021 at 02:42:01AM +0200, Julia Suvorova wrote:
> Add acpi_pcihp to ich9_pm as part of
> 'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
>
> Signed-off-by: Julia Suvorova
> Signed-off-by: Marcel Apfelbaum
> Reviewed-by: Igor Mammedov
Reviewed-by: David Gibs
On Tue, Jul 13, 2021 at 02:42:00AM +0200, Julia Suvorova wrote:
> Implement notifications and gpe to support q35 ACPI PCI hot-plug.
> Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
>
> Signed-off-by: Julia Suvorova
> Reviewed-by: Igor Mammedov
> Reviewed-by: Marcel Apfelbaum
Reviewed
On Fri, Jul 9, 2021 at 2:44 PM Richard Henderson
wrote:
>
> Allocate new temps to hold the source extensions, and
> extend directly from the source registers.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 46 +++
On Fri, Jul 9, 2021 at 2:43 PM Richard Henderson
wrote:
>
> These operations are slightly more complicated since
> we need to crop the shift operand.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 68 +++-
On Fri, Jul 9, 2021 at 9:01 AM Alistair Francis
wrote:
>
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the timer and soft MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_clint.h | 2 +
> hw/intc/sifive_clint.c
在 2021/7/13 上午7:58, Dongli Zhang 写道:
This patch is to add the HMP interface to dump MSI-X table and PBA, in
order to help diagnose the loss of IRQ issue in VM (e.g., if an MSI-X
vector is erroneously masked permanently). Here is the example with
vhost-scsi:
(qemu) info msix /machine/peripheral
On Tue, Jul 13, 2021 at 1:15 PM Qiang Liu wrote:
>
> xlnx_dp_read allows an out-of-bounds read at its default branch because
> of an improper index.
>
> According to
> https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
> (DP Module), registers 0x3A4/0x3A4/0x3AC
On 26-05-21, 13:13, Alex Bennée wrote:
>
> Viresh Kumar writes:
>
> > Update .gitignore to ignore .swp and .patch files.
> >
> > Signed-off-by: Viresh Kumar
>
> Reviewed-by: Alex Bennée
No one picked it up yet, do I need to do something here ?
--
viresh
xlnx_dp_read allows an out-of-bounds read at its default branch because
of an improper index.
According to
https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
(DP Module), registers 0x3A4/0x3A4/0x3AC are allowed.
DP_INT_MASK 0x03A4 32 mixed
On Fri, 9 Jul 2021, at 16:59, Philippe Mathieu-Daudé wrote:
> On 7/9/21 7:31 AM, Andrew Jeffery wrote:
> > The logic in the handling for the control register required toggling the
> > enable state for writes to stick. Rework the condition chain to allow
> > sequential writes that do not update t
qemu can't start a xen vm after commit d8fb7d0969d5
"vl: switch -M parsing to keyval" with:
$ ./qemu-system-i386 -M xenfv
Unexpected error in object_property_find_err() at ../qom/object.c:1298:
qemu-system-i386: Property 'xenfv-3.1-machine.accel' not found
Aborted (core dumped)
The default_machin
From: BALATON Zoltan
Linux needs setprop to fix up the device tree, otherwise it's not
finding devices and cannot boot. Since recent VOF change now we need
to add a callback to allow this which is what this patch does.
Signed-off-by: BALATON Zoltan
Message-Id: <20210709132920.6544e745...@zero.e
The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320:
Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708' into
staging (2021-07-12 19:15:11 +0100)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.1-2021071
From: BALATON Zoltan
The switch case of writing PCI 1 IO base address had an extra break
statement that made part of the code unreachable. This did not cause a
problem as guests ususally leave this register at its default value.
Fixes: dcdf98a9015 ("Add emulation of Marvell MV64361 PPC system
On Mon, Jul 12, 2021 at 03:11:01PM +0200, BALATON Zoltan wrote:
> The switch case of writing PCI 1 IO base address had an extra break
> statement that made part of the code unreachable. This did not cause a
> problem as guests ususally leave this register at its default value.
>
> Reported-by: Cov
On Mon, Jul 12, 2021 at 02:55:30PM -0700, Richard Henderson wrote:
> >From clang-13:
> hw/ppc/spapr_events.c:937:14: error: variable 'xinfo' set but not used \
> [-Werror,-Wunused-but-set-variable]
>
> Cc: qemu-...@nongnu.org
> Cc: Greg Kurz
> Cc: David Gibson
> Signed-off-by: Richard Hender
On Mon, Jul 12, 2021 at 02:55:31PM -0700, Richard Henderson wrote:
> >From clang-13:
> hw/pci-host/pnv_phb4.c:375:18: error: variable 'v' set but not used \
> [-Werror,-Wunused-but-set-variable]
>
> It's pretty clear that we meant to write back 'v' after
> all that computation and not 'val'.
>
Since we don't have an encoding like the previous quirk,
we can use vfio_pci_is().
Signed-off-by: Cai Huoqing
---
hw/vfio/pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index ab4077aad2..971273fd45 100644
--- a/hw/vfio/pci.c
+++ b/hw/v
From: Philippe Mathieu-Daudé
Add a pair of tests for the Pegasos2 machine following the steps from:
https://lists.nongnu.org/archive/html/qemu-devel/2021-01/msg01553.html
$ AVOCADO_ALLOW_UNTRUSTED_CODE=1 avocado --show=app,console,tesseract \
run -t machine:pegasos2 tests/acceptance/
Sure I will check these issue in our hardware
Then ,send patch-v2
-Original Message-
From: Alex Williamson
Sent: 2021年7月13日 3:49
To: Cai,Huoqing
Cc: m...@redhat.com; marcel.apfelb...@gmail.com; qemu-devel@nongnu.org
Subject: Re: [PATCH] vfio/pci: Add pba_offset PCI quirk for BAIDU KUNL
>From source code, the 'devid' of x-remote-object should be one of devices
in remote QEMU process.
Signed-off-by: Dongli Zhang
Reviewed-by: Jagannathan Raman
---
Resend to be applied as trivial patch.
I have verified by reading the code and playing with below orchestrator.
https://github.com/fi
Q35 has three different types of PCI devices hot-plug: PCIe Native,
SHPC Native and ACPI hot-plug. This patch changes the default choice
for cold-plugged bridges from PCIe Native to ACPI Hot-plug with
ability to use SHPC and PCIe Native for hot-plugged bridges.
This is a list of the PCIe Native ho
Add ACPI hot-plug registers to DSDT Q35 tables.
Changes in the tables:
+Scope (_SB.PCI0)
+{
+OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)
+Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+{
+PCIU, 32,
+PCID, 32
+}
+
+Operat
Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
---
hw/i386/acpi-build.h| 4
include/hw/acpi/ich9.h | 2 ++
include/hw/a
Instead of changing the hot-plug type in _OSC register, do not
set the 'Hot-Plug Capable' flag. This way guest will choose ACPI
hot-plug if it is preferred and leave the option to use SHPC with
pcie-pci-bridge.
The ability to control hot-plug for each downstream port is retained,
while 'hotplug=of
All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/qtest/
Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
Signed-off-by: Julia Suvorova
Signed-off-by: Marcel Apfelbaum
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h| 1 +
include/hw/acpi/ich9.h | 3 ++
hw/acpi/acpi-x86-stub.c | 6 +
The patch set consists of two parts:
patches 1-3: introduce new feature
'acpi-pci-hotplug-with-bridge-support' on Q35
patches 4-6: make the feature default along with changes in ACPI tables
With the feature disabled Q35 falls back to the native hot-plug.
Pros
* no racy behavior d
On 7/12/21 2:30 PM, Cole Robinson wrote:
On 7/12/21 11:59 AM, Richard Henderson wrote:
The first two patches are not strictly required, but they
were useful in tracking down the root problem here.
I understand the logic behind the clang-12 warning, but I think
it's a clear mistake that it shoul
This patch is to implement the device specific interface to dump the
mapping between virtio queues and vectors.
(qemu) info msix -d /machine/peripheral/vscsi0
Msg L.Addr Msg U.Addr Msg Data Vect Ctrl
0xfee0 0x 0x4041 0x
0xfee0 0x 0x4051 0x
0xfee000
This patch is to add the HMP interface to dump MSI-X table and PBA, in
order to help diagnose the loss of IRQ issue in VM (e.g., if an MSI-X
vector is erroneously masked permanently). Here is the example with
vhost-scsi:
(qemu) info msix /machine/peripheral/vscsi0
Msg L.Addr Msg U.Addr Msg Data
I have just rebased the v2 patchset on top of most recent qemu to resend.
This patch is to introduce the new HMP command to dump the MSI-X table/PBA.
Here is the RFC v1:
https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg04673.html
The idea was inspired by below discussion:
https://lists
While the previous patch is to dump the MSI-X table, sometimes we may
need to dump device specific data, e.g., to help match the vector with
the specific device queue.
This patch is to add the PCI device specific interface to help dump
those information. Any PCI device class may implement this
PCI
On Tue, Jul 6, 2021 at 5:49 AM Vladimir Sementsov-Ogievskiy <
vsement...@virtuozzo.com> wrote:
> 25.06.2021 21:20, John Snow wrote:
> > This turns run_linters() into a bit of a hybrid test; returning non-zero
> > on failed execution while also printing diffable information. This is
> > done for th
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, July 6, 2021 5:49 PM
> To: qemu-devel@nongnu.org
> Cc: laur...@vivier.eu; alex.ben...@linaro.org; Taylor Simpson
> ; Philippe Mathieu-Daudé
> Subject: [PATCH v2 19/36] linux-user/hexagon: Implement setup_sigtramp
>
> Conti
On Mon, Jul 5, 2021 at 1:57 PM Bin Meng wrote:
>
> On Mon, Jul 5, 2021 at 12:21 PM Jason Wang wrote:
> >
> >
> > 在 2021/7/2 下午5:24, Bin Meng 写道:
> > > From: Christina Wang
> > >
> > > The initial value of VLAN Ether Type (VET) register is 0x8100, as per
> > > the manual and real hardware.
> > >
On Mon, Jul 12, 2021 at 11:03 PM Anup Patel wrote:
>
> On Mon, Jul 12, 2021 at 6:41 PM Bin Meng wrote:
> >
> > On Mon, Jul 12, 2021 at 6:54 PM Anup Patel wrote:
> > >
> > > On Mon, Jul 12, 2021 at 11:45 AM Bin Meng wrote:
> > > >
> > > > On Mon, Jul 12, 2021 at 1:39 PM Anup Patel wrote:
> > >
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.fran...@wdc.com
---
include/hw/riscv/opentitan.h | 1 +
hw/riscv/opentitan.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/riscv/openti
From: Jose Martins
The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.
Signed-off-by: Jose Martins
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-id: 20210522155902.374439-1-josemartin...@gmail.com
[ C
From: Bin Meng
This adds detailed documentation for RISC-V `virt` machine,
including the following information:
- Supported devices
- Hardware configuration information
- Boot options
- Running Linux kernel
- Running U-Boot
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Messa
From: Bin Meng
This adds a new section in the documentation to demonstrate how to
use the new direct kernel boot feature for Microchip Icicle Kit,
other than the HSS bootflow, using an upstream U-Boot v2021.07 image
as an example.
It also updates the truth table to have a new '-dtb' column which
OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.fran...@wdc.com
---
include/hw/riscv/opentitan.h |
Update the register layout to match the latest OpenTitan bitstream.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.fran...@wdc.com
---
hw/char/ibex_uart.c | 19 ++-
1 file changed, 10 insertions
From: Bin Meng
It's Core *Local* Interruptor, not 'Level'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210627142816.19789-1-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
docs/system/riscv/sifive_u.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
From: Bin Meng
Currently the firmware dynamic info (fw_dyn) is put right after
the reset vector, which is not 8-byte aligned on RV64. OpenSBI
fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
which expects fw_dyn to be on the 8-byte boundary, otherwise the
misaligned load excepti
l-riscv-to-apply-20210712
for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d:
hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000)
Fourth RISC-V PR for 6.1 release
- Code cleanups
- Doc
From: Bin Meng
The following check:
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message
From: Bin Meng
%s/CSP/CSR
%s/thie/the
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 20210627115716.3552-1-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/pmp.c | 10 +-
1 file changed, 5 insertions(+), 5 del
From: Bin Meng
At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210706102616.1922469-1-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
hw/ri
Alex Bennée writes:
> Alex Bennée writes:
>
>> The following changes since commit 86108e23d798bcd3fce35ad271b198f8a8611746:
>>
>> Merge remote-tracking branch
>> 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging
>> (2021-07-11 18:49:25 +0100)
>>
>> are available in th
Wainer dos Santos Moschetta writes:
> Hi,
>
> On 5/15/21 10:45 AM, Philippe Mathieu-Daudé wrote:
>> Add a pair of tests for the Pegasos2 machine following the steps from:
>> https://lists.nongnu.org/archive/html/qemu-devel/2021-01/msg01553.html
>>
>>$ PEGASOS2_ROM_PATH=/tmp/pegasos2.rom AVOC
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
the ABI for ppc32. Make a good guess based on other symbols.
Reported-by: Brad Smith
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
di
>From clang-13:
hw/ppc/spapr_events.c:937:14: error: variable 'xinfo' set but not used \
[-Werror,-Wunused-but-set-variable]
Cc: qemu-...@nongnu.org
Cc: Greg Kurz
Cc: David Gibson
Signed-off-by: Richard Henderson
---
hw/ppc/spapr_events.c | 5 -
1 file changed, 5 deletions(-)
diff --g
If __APPLE__, ensure that _CALL_DARWIN is set, then remove
our local TCG_TARGET_CALL_DARWIN.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index e0f4665
>From clang-13:
linux-user/syscall.c:8503:17: error: variable 'total_size' set but not used \
[-Werror,-Wunused-but-set-variable]
Cc: Laurent Vivier
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/linux-user/syscall.c b/linux-u
>From clang-13:
util/selfmap.c:26:21: error: variable 'errors' set but not used \
[-Werror,-Wunused-but-set-variable]
Quite right of course, but there's no reason not to check errors.
First, incrementing errors is incorrect, because qemu_strtoul
returns an errno not a count -- just or them to
>From clang-13:
tests/unit/test-iov.c:161:26: error: variable 't' set but not used \
[-Werror,-Wunused-but-set-variable]
Signed-off-by: Richard Henderson
---
tests/unit/test-iov.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/tests/unit/test-iov.c b/tests/unit/test-
>From clang-13:
nbd/server.c:976:22: error: variable 'bitmaps' set but not used \
[-Werror,-Wunused-but-set-variable]
Cc: qemu-bl...@nongnu.org
Cc: Eric Blake
Cc: Vladimir Sementsov-Ogievskiy
Signed-off-by: Richard Henderson
---
nbd/server.c | 4
1 file changed, 4 deletions(-)
diff -
>From clang-13:
hw/pci-host/pnv_phb4.c:375:18: error: variable 'v' set but not used \
[-Werror,-Wunused-but-set-variable]
It's pretty clear that we meant to write back 'v' after
all that computation and not 'val'.
Cc: qemu-...@nongnu.org
Cc: Greg Kurz
Cc: David Gibson
Signed-off-by: Richard
>From clang-13:
../qemu/net/checksum.c:189:23: error: variable 'buf_off' set but not used \
[-Werror,-Wunused-but-set-variable]
Cc: Jason Wang
Signed-off-by: Richard Henderson
---
net/checksum.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/net/checksum.c b/net/chec
>From clang-13:
accel/tcg/cpu-exec.c:783:15: error: variable 'cc' set but not used \
[-Werror,-Wunused-but-set-variable]
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index e22bcb99f
The goal here was to address Brad's report for clang vs ppc32.
Somewhere in between here and there I forgot about the ppc32 part,
needed a newer clang for gcc135, accidentally built master instead
of the clang-12 release branch, fixed a bunch of buggy looking
things, and only then remembered I was
>From clang-13:
hw/audio/adlib.c:189:18: error: variable 'net' set but not used \
[-Werror,-Wunused-but-set-variable]
Cc: Gerd Hoffmann
Signed-off-by: Richard Henderson
---
hw/audio/adlib.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/audio/adlib.c b/hw/audio/adl
On 7/12/21 11:59 AM, Richard Henderson wrote:
> The first two patches are not strictly required, but they
> were useful in tracking down the root problem here.
>
> I understand the logic behind the clang-12 warning, but I think
> it's a clear mistake that it should be enabled by default for a
> ta
On 2021-07-12 4:02 pm, Laurent Vivier wrote:
Le 09/07/2021 à 18:04, Jonathan Albrecht a écrit :
qemu-s390x signals with SIGILL on compare-and-trap instructions. This
breaks OpenJDK which expects SIGFPE in its implementation of implicit
exceptions.
This patch depends on [PATCH v6 0/2] target/s39
On Mon, 2021-07-12 at 10:59 -0400, jonathan.albrecht wrote:
> On 2021-07-02 8:01 am, Laurent Vivier wrote:
> > Le 02/07/2021 à 12:34, Cornelia Huck a écrit :
> > > On Wed, Jun 23 2021, Ilya Leoshkevich wrote:
> > >
> > >
> > > What's the status of this and
> > > <20210621141452.2045-1-jonathan.a
The following changes since commit bd38ae26cea0d1d6a97f930248df149204c210a2:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into
staging (2021-07-12 11:02:39 +0100)
are available in the Git repository at:
https://github.com/stsquad/qemu.git tags/pull-testing-and-pl
The TCPA.tis.tpm12 file contains the following:
[000h 4]Signature : "TCPA"[Trusted Computing
Platform Alliance table]
[004h 0004 4] Table Length : 0032
[008h 0008 1] Revision : 02
[009h 0009 1] Checks
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