There are some issues in the checks for libfdt in meson.build which
get fixed with the first two patches.
And while we're at it, also update the dtc submodule to a proper release
version (in the third patch).
Thomas Huth (3):
meson.build: Fix the check for a usable libfdt
meson.build: Don't u
If the users ran configure with --enable-libfdt=system, they likely did
that on purpose. We should not silently fall back to the internal libfdt
if the system libfdt is not usable, but report the problem with a proper
message instead.
Signed-off-by: Thomas Huth
---
meson.build | 2 ++
1 file cha
The check for libfdt currently has a flaw: If there is a system libfdt, the
meson.build code initialized the fdt variable with fdt = cc.find_library(...).
However, if this libfdt is too old and there is no internal dtc module
available, it continues with "fdt" pointing to the old and unusable versi
On 27/08/2021 11:14, Peter Maydell wrote:
On Fri, 27 Aug 2021 at 10:14, Mark Cave-Ayland
wrote:
Ah so the plan moving forward is to always have an explicit MR passed in for
DMA use.
Sorry if I missed that in earlier versions of the patchset, I'm still getting
back up
to speed on QEMU hacking
The virtio IDs depends on Linux tree...
Signed-off-by: Pierre Morel
---
include/standard-headers/linux/virtio_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/standard-headers/linux/virtio_ids.h
b/include/standard-headers/linux/virtio_ids.h
index 4fe842c3a3..bf61801eeb 100644
-
This VIRTIO device receives data on its input channel
and emit a simple checksum for these data on its
output channel.
This allows a simple VIRTIO device driver to check the
VIRTIO initialization and various data transfer.
Signed-off-by: Pierre Morel
---
hw/s390x/meson.build| 1 +
Hello All,
This series presents a VIRTIO test device which receives data on its
input channel and sends back a simple checksum for the data it received
on its output channel.
The goal is to allow a simple VIRTIO device driver to check the VIRTIO
initialization and various data transfer.
For th
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/569
** Tags added: scsi
** Bug watch added: gitlab.com/qemu-projec
Hi,
I am working to add the PCIe root complex event collector support to Qemu.
I want to test the AER error injection by using the QMP shell. However I am
unable to use the pcie_aer_inject_error command on the QMP shell. I see
this error: "id or pci device path is invalid or device not found ".
I
On Sun, 15 Aug 2021 at 17:31, Kevin Townsend wrote:
>
> This commit adds emulation of the magnetometer on the LSM303DLHC.
> It allows the magnetometer's X, Y and Z outputs to be set via the
> mag_x, mag_y and mag_z properties, as well as the 12-bit
> temperature output via the temperature property
On Fri, 27 Aug 2021 at 05:50, Markus Armbruster wrote:
>
> The following changes since commit c83fcfaf8a54d0d034bd0edf7bbb3b0d16669be9:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-08-26'
> into staging (2021-08-26 13:42:34 +0100)
>
> are available in the Git repository
On Fri, Aug 6, 2021 at 8:00 AM Bin Meng wrote:
>
> On Sat, Jul 24, 2021 at 8:27 PM Anup Patel wrote:
> >
> > We extend virt machine to emulate ACLINT devices only when "aclint=on"
> > parameter is passed along with machine name in QEMU command-line.
> >
> > Signed-off-by: Anup Patel
> > ---
> >
On Fri, 27 Aug 2021 at 10:14, Mark Cave-Ayland
wrote:
> Ah so the plan moving forward is to always have an explicit MR passed in for
> DMA use.
> Sorry if I missed that in earlier versions of the patchset, I'm still getting
> back up
> to speed on QEMU hacking.
>
> Was there a decision as to wha
On Fri, Aug 6, 2021 at 7:55 AM Bin Meng wrote:
>
> On Sat, Jul 24, 2021 at 8:27 PM Anup Patel wrote:
> >
> > The RISC-V ACLINT is more modular and backward compatible with
> > original SiFive CLINT so instead of duplicating the original
> > SiFive CLINT implementation we upgrade the current SiFiv
On Fri, Aug 27, 2021 at 08:30:07AM +, ishii.shuuic...@fujitsu.com wrote:
>
> Thank you, Andrew, for creating the patches.
> And thank you all for your comments.
>
> I have applied the suggested v2 patch series by andrew locally,
> and reviewed the next version of the a64fx patch series as fo
FORM2 NUMA affinity is prepared to deal with memory/cpu less
NUMA nodes. This is used by the DAX KMEM driver to locate a
PAPR SCM device that has a different latency than the original
NUMA node from the regular memory.
Move this verification to FORM1 affinity code.
Signed-off-by: Daniel Henrique
The main feature of FORM2 affinity support is the separation of NUMA
distances from ibm,associativity information. This allows for a more
flexible and straightforward NUMA distance assignment without relying on
complex associations between several levels of NUMA via
ibm,associativity matches. Anoth
When spapr_numa_associativity_init() was introduced it was being
called from spapr_machine_init(), where we have pointers to a
SpaprMachineState and a MachineState. Having both being passed
as params spared us from calling a macro to get the MachineState.
Previous patches moved the function away f
The upcoming FORM2 NUMA affinity will support asymmetric NUMA topologies
and doesn't need be concerned with all the legacy support for older
pseries FORM1 guests.
We're also not going to calculate associativity domains based on numa
distance (via spapr_numa_define_associativity_domains) since the
Hi,
This new version contains changes suggested by Greg from his v3 review.
Changes from v3:
- patch 1: added due to a need of having a MachineClass attribute for tne
yet to be added 6.2 machine type. Can be dropped if someone already did this
in an yet to be merged tree. Can also be enhanced t
Signed-off-by: Daniel Henrique Barboza
---
hw/core/machine.c | 3 +++
hw/ppc/spapr.c | 15 +--
include/hw/boards.h | 3 +++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 54e040587d..067f42b528 100644
--- a/hw/core/
On 27/08/2021 09:54, Peter Maydell wrote:
In a way I could see why you may wish to explicitly set the DMA memory region,
but a
quick look around suggests that devices where the memory region is unspecified
(typically using a link property called "dma_mr") then the default is assumed
to be
get_
Hi
On Fri, Aug 27, 2021 at 1:03 PM Daniel P. Berrangé
wrote:
> On Wed, Aug 25, 2021 at 07:12:10PM +0100, Peter Maydell wrote:
> > On Wed, 25 Aug 2021 at 14:28, Philippe Mathieu-Daudé
> wrote:
> > >
> > > On 8/25/21 2:43 PM, marcandre.lur...@redhat.com wrote:
> > > > From: Marc-André Lureau
> >
On Wed, Aug 25, 2021 at 07:12:10PM +0100, Peter Maydell wrote:
> On Wed, 25 Aug 2021 at 14:28, Philippe Mathieu-Daudé wrote:
> >
> > On 8/25/21 2:43 PM, marcandre.lur...@redhat.com wrote:
> > > From: Marc-André Lureau
> > >
> > > DTC is widely available, we could consider to stop bundling it.
> >
On Fri, 27 Aug 2021 at 09:30, ishii.shuuic...@fujitsu.com
wrote:
>
>
> Thank you, Andrew, for creating the patches.
> And thank you all for your comments.
>
> I have applied the suggested v2 patch series by andrew locally,
FYI, Andrew's patches are now upstream so you'll be able to base your
next
On Thu, 26 Aug 2021 at 22:15, Mark Cave-Ayland
wrote:
>
> On 26/08/2021 21:07, Philippe Mathieu-Daudé wrote:
>
> > Simplify by always passing a MemoryRegion property to the device.
> > Doing so we can move the AddressSpace field to the device struct,
> > removing need for heap allocation.
> >
> >
Thank you, Andrew, for creating the patches.
And thank you all for your comments.
I have applied the suggested v2 patch series by andrew locally,
and reviewed the next version of the a64fx patch series as follows.
I would appreciate if you could comment on whether there are
any problems with th
On 13/07/2021 23.01, Willian Rampazzo wrote:
Although it is possible to run a specific test using the avocado
command-line, a user may want to use a specific tag while running the
``make check-acceptance`` during the development or debugging.
This allows using the AVOCADO_TAGS environment variab
This patch add support for disassembling via option '-d in_asm'.
Acked-by: Richard Henderson
Signed-off-by: Song Gao
---
MAINTAINERS |1 +
disas/loongarch.c | 2511 +++
disas/meson.build |1 +
include/disas/dis-asm.h |
This patch add build loongarch-linux-user target support.
Signed-off-by: Song Gao
---
target/loongarch/meson.build | 18 ++
target/meson.build | 1 +
2 files changed, 19 insertions(+)
create mode 100644 target/loongarch/meson.build
diff --git a/target/loongarch/meson
Add loongarch64 linux-user default configs file.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
configs/targets/loongarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 configs/targets/loongarch64-linux-user.mak
diff --git a/configs/targets/loongarch6
This patch implement branch instruction translation.
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_branch.c | 84 ++
target/loongarch/insns.decode | 30
Hi
On Fri, Aug 27, 2021 at 11:44 AM Marc-André Lureau <
marcandre.lur...@redhat.com> wrote:
> Hi
>
> On Thu, Aug 26, 2021 at 10:58 PM Peter Xu wrote:
>
>> Both dump-guest-memory and live migration caches vm state at the
>> beginning.
>> Either of them entering the other one will cause race on th
Hi
On Thu, Aug 26, 2021 at 10:58 PM Peter Xu wrote:
> Both dump-guest-memory and live migration caches vm state at the beginning.
> Either of them entering the other one will cause race on the vm state, and
> even
> more severe on that (please refer to the crash report in the bug link).
>
> Let'
This patch implement floating point load/store instruction translation.
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_fmemory.c | 143
target/loongarc
This patch implement fixed point extra instruction translation.
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 4 ++
target/loongarch/insn_trans/trans_extra.c | 8
This patch implement floationg point move instruction translation.
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Signed-off-by: Song Gao
---
target/loongarch/fpu_helper.c
This patch implement fixed point atomic instruction translation.
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_atomic.c | 132 +
target/loongar
This patch implement fixed point load/store instruction translation.
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao
---
target/loongar
This patch implement floating point conversion instruction translation.
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao
---
target/loongarch/fpu_helper.c| 393 +
This patch implement fixed point shift instruction translation.
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_shift.c | 154
From: Cédric Le Goater
It's generic enough to be used from the XIVE2 router and avoid more
duplication.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
Message-Id: <20210809134547.689560-9-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/xive.c| 8
include/hw/ppc
This patch implement fixed point bit instruction translation.
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Signed-off-by: Song Gao
---
target/loong
This patch add main translation routines and
basic functions for translation.
Signed-off-by: Song Gao
---
target/loongarch/helper.h| 9 +++
target/loongarch/op_helper.c | 22 ++
target/loongarch/translate.c | 171 +++
target/loongarch/translate.
Hi,
This series only adds linux-user emulation support for LoongArch.
So there is no introduction of system in docs/system directory,
We'll add that in a future series.
Changes for v3:
* split trans.inc.c.
* remove csr registers.
* delete patchs 2, 4, 5.
* follow Richard's code review co
This patch give an introduction to the LoongArch target.
Signed-off-by: Song Gao
---
MAINTAINERS | 5 +
target/loongarch/README | 5 +
2 files changed, 10 insertions(+)
create mode 100644 target/loongarch/README
diff --git a/MAINTAINERS b/MAINTAINERS
index dffcb65..396f970
From: Matheus Ferst
Changes the current bswap128 implementation to use __builtin_bswap128
when available, adds a bswap128 implementation for !CONFIG_INT128
builds, and introduces bswap128s based on bswap128.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Matheus
From: Matheus Ferst
As vector registers are stored in host endianness, we shouldn't swap its
64-bit elements in user mode. Add a 16-byte case in
ppc_maybe_bswap_register to handle the reordering of elements in softmmu
and remove avr_need_swap which is now unused.
Reviewed-by: Peter Maydell
Sign
Implementation of linux user emulation for LoongArch.
Signed-off-by: Song Gao
---
include/elf.h | 2 +
linux-user/elfload.c | 58 ++
linux-user/loongarch64/cpu_loop.c | 108 ++
linux-user/loongarch64/signal.c|
From: Cédric Le Goater
But always give the first 1GB to chip 0 as skiboot requires it.
Signed-off-by: Cédric Le Goater
Message-Id: <20210809134547.689560-6-...@kaod.org>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 33 +
1 file changed
This patch implement floating point comparison instruction translation.
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao
---
target/loongarch/fpu_helper.c| 110
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_fcmp.c | 279
This patch implement floating point arithmetic instruction translation.
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: S
From: Cédric Le Goater
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
HAIL but since it does not break the modeling and that we don't plan
to support DD1, modify the LPCR mask of all the POWER10 family.
Setting the HAIL bit is a requirement to support the scv instruction
on P
This patch implement fixed point arithemtic instruction translation.
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MU
From: Matheus Ferst
These helpers shouldn't depend on the host endianness, as they only use
shifts, ands, and int128_* methods.
Fixes: 60caf2216bf0 ("target-ppc: add vextu[bhw][lr]x instructions")
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: David Gibson
Signed-off-by: Matheus Ferst
Messa
This patch add target state header, target definitions
and initialization routines.
Signed-off-by: Song Gao
---
target/loongarch/cpu-param.h | 19 +++
target/loongarch/cpu.c | 285 +++
target/loongarch/cpu.h | 145 ++
targ
From: Cédric Le Goater
The Hypervisor Decrementer exception should not be generated while the
CPU is in power-saving mode (see cpu_ppc_hdecr_excp()). However,
discarding the exception before entering the power-saving mode is
wrong since we would loose a previously generated HDEC.
Fixes: 4b236b62
From: Matheus Ferst
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Matheus Ferst
Message-Id: <20210826141446.2488609-2-matheus.fe...@eldorado.org.br>
Signed-off-by: David Gibson
---
include/qemu/int128.h | 27 ---
From: Cédric Le Goater
There is no need to keep the DD1 chip model as it will never be
publicly available.
Signed-off-by: Cédric Le Goater
Message-Id: <20210809134547.689560-3-...@kaod.org>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c
pc-for-6.2-20210827
for you to fetch changes up to 0ff16b6b78831240c39cfaaeab1f22ae52c84b09:
target/ppc: fix vector registers access in gdbstub for little-endian
(2021-08-27 12:43:13 +1000)
ppc patch queue 2021-08-27
First ppc pu
From: Cédric Le Goater
When the QEMU PowerNV machine was introduced, multi chip support
modeled a two socket system with dual chip modules as found on some P8
Tuleta systems (8286-42A). But this is hardly used and not relevant
for QEMU. Use a simple index instead.
With this change, we can now in
From: Cédric Le Goater
These will be shared with the XIVE2 router.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
Message-Id: <20210809134547.689560-8-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/spapr_xive_kvm.c | 8
hw/intc/xive.c | 6 +++---
include/hw/
From: "Lucas Mateus Castro (alqotel)"
Divided mmu_helper.c in 2 files, functions inside #ifdef CONFIG_SOFTMMU
stayed in mmu_helper.c, other functions moved to mmu_common.c. Updated
meson.build to compile mmu_common.c and only compile mmu_helper.c when
CONFIG_TCG is set.
Moved function declaration
From: Cédric Le Goater
Cc: th...@redhat.com
Fixes: 4e960974d4ee ("xive: Add trace events")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/519
Signed-off-by: Cédric Le Goater
Message-Id: <20210809085227.288523-1-...@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivi
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-Id: <20210809134547.689560-7-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_xscom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index be7018e8ac..faa488e311 100644
--- a/h
From: "Lucas Mateus Castro (alqotel)"
ppc_store_sdr1 was at first in mmu_helper.c and was moved as part
the patches to enable the disable-tcg option, now it's being moved
back to a file that will be compiled with that option
Signed-off-by: Lucas Mateus Castro (alqotel)
Message-Id: <202107231756
This uses g_autofree to simplify logic in spapr_phb_vfio_get_loc_code(),
in the process fixing a leak in one of the paths. I'm told this fixes
Coverity error CID 1460454
Reported-by: Peter Maydell
Fixes: 16b0ea1d852 ("spapr_pci: populate ibm,loc-code")
Reviewed-by: Philippe Mathieu-Daudé
Signed
From: "Lucas Mateus Castro (alqotel)"
moved store_40x_sler from mmu_common.c to helper_regs.c as it is
a function to store a value in a special purpose register, so
moving it to a file focused in special register manipulation
is more appropriate.
Signed-off-by: Lucas Mateus Castro (alqotel)
Mes
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