Re: [PULL 35/44] tcg/arm: Remove fallback definition of __ARM_ARCH

2021-09-13 Thread Philippe Mathieu-Daudé
On 9/14/21 2:14 AM, Richard Henderson wrote: > GCC since 4.8 provides the definition and we now require 7.5. FYI we might go back to 7.4 (this doesn't affect this patch): https://gitlab.com/qemu-project/qemu/-/issues/614 > Reviewed-by: Peter Maydell > Signed-off-by: Richard Henderson > --- >

Re: [PATCH 21/22] qapi: Drop simple unions

2021-09-13 Thread Markus Armbruster
Eric Blake writes: > On Mon, Sep 13, 2021 at 02:39:31PM +0200, Markus Armbruster wrote: >> Simple unions predate flat unions. Having both complicates the QAPI >> schema language and the QAPI generator. We haven't been using simple >> unions in new code for a long time, because they are less

Re: [PATCH 19/22] tests/qapi-schema: Drop simple union __org.qemu_x-Union1

2021-09-13 Thread Markus Armbruster
Eric Blake writes: > On Mon, Sep 13, 2021 at 02:39:29PM +0200, Markus Armbruster wrote: >> Replace simple union __org.qemu_x-Union1 flat union > > missing 'with' Will fix. >> __org.qemu_x-Union2, except drop it from __org.qemu_x-command, because >> there it's only used to pull it into QMP.

Re: [PATCH 12/22] test-qobject-input-visitor: Wean off UserDefListUnion

2021-09-13 Thread Markus Armbruster
Eric Blake writes: > On Mon, Sep 13, 2021 at 02:39:22PM +0200, Markus Armbruster wrote: >> The test_visitor_in_list_union_FOO() use simple union UserDefListUnion >> to cover lists of builtin types. Rewrite as >> test_visitor_in_list_struct(), using struct ArrayStruct and a lot less >> code. >>

Re: [PATCH] gitlab-ci: Make more custom runner jobs manual, and don't allow failure

2021-09-13 Thread Thomas Huth
On 13/09/2021 12.19, Peter Maydell wrote: Currently we define a lot of jobs for our custom runners: for both aarch64 and s390x we have - all-linux-static - all - alldbg - clang (manual) - tci - notcg (manual) This is overkill. The main reason to run on these hosts is to get

Re: [qemu-web RFC PATCH] Add Sponsors page

2021-09-13 Thread Thomas Huth
On 13/09/2021 20.25, Philippe Mathieu-Daudé wrote: Add a page listing QEMU sponsors and displaying their logos. Logo sources: - https://www.rackspace.com/es/newsroom/media-kit - https://developer.arm.com/solutions/infrastructure/works-on-arm - https://gitlab.com/fosshost/assets/logo -

Re: [PATCH 10/22] qapi: Convert simple union TransactionAction to flat one

2021-09-13 Thread Markus Armbruster
Eric Blake writes: > On Mon, Sep 13, 2021 at 02:39:20PM +0200, Markus Armbruster wrote: >> Simple unions predate flat unions. Having both complicates the QAPI >> schema language and the QAPI generator. We haven't been using simple >> unions in new code for a long time, because they are less

Re: [qemu-web PATCH] Gemfile: Add webrick bundle dependency

2021-09-13 Thread Thomas Huth
On 13/09/2021 20.29, Philippe Mathieu-Daudé wrote: Without the webrick bundle, jekyll fails to start: $ bundle exec jekyll serve Ignoring ffi-1.11.1 because its extensions are not built. Try: gem pristine ffi --version 1.11.1 Configuration file: qemu-web/_config.yml

Re: [PATCH 04/22] qapi: Convert simple union InputEvent to flat one

2021-09-13 Thread Markus Armbruster
Eric Blake writes: > On Mon, Sep 13, 2021 at 02:39:14PM +0200, Markus Armbruster wrote: >> Simple unions predate flat unions. Having both complicates the QAPI >> schema language and the QAPI generator. We haven't been using simple >> unions in new code for a long time, because they are less

[PATCH 2/3] hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in q35

2021-09-13 Thread Ani Sinha
Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35") selects an IO address range for acpi based PCI hotplug for q35 arbitrarily. It starts at address 0x0cc4 and ends at 0x0cdb. At the time when the patch was written but the final version of the patch was not yet

[PATCH 3/3] bios-tables-test: Update ACPI DSDT table golden blobs for q35

2021-09-13 Thread Ani Sinha
We have modified the IO address range for ACPI pci hotplug in q35. See change: 36f98d0d4f ("hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in q35") The ACPI DSDT table golden blobs must be regenrated in order to make the unit tests pass. This change updates the golden ACPI

Re: [PATCH 03/22] qapi: Convert simple union KeyValue to flat one

2021-09-13 Thread Markus Armbruster
Eric Blake writes: > On Mon, Sep 13, 2021 at 02:39:13PM +0200, Markus Armbruster wrote: >> Simple unions predate flat unions. Having both complicates the QAPI >> schema language and the QAPI generator. We haven't been using simple >> unions in new code for a long time, because they are less

[PATCH 1/3] bios-tables-test: allow changes in DSDT ACPI tables for q35

2021-09-13 Thread Ani Sinha
We are going to commit a change to fix IO address range allocated for acpi pci hotplug in q35. This affects DSDT tables. This change allows DSDT table modification so that unit tests are not broken. Signed-off-by: Ani Sinha --- tests/qtest/bios-tables-test-allowed-diff.h | 11 +++ 1

hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in q35

2021-09-13 Thread Ani Sinha
Hi Igor/Michael : This patchset fixes the acpi pci hotplug IO address range conflict issue with cpu hotplug. This issue has been reported here: https://gitlab.com/qemu-project/qemu/-/issues/561 We have disucssed this issue at length here:

Re: [PATCH] qapi: define cleanup function for g_autoptr(Error)

2021-09-13 Thread Markus Armbruster
Philippe Mathieu-Daudé writes: > On 9/13/21 3:08 PM, Markus Armbruster wrote: >> Markus Armbruster writes: [...] >> As is, reporting errors doesn't play well with g_autoptr(). Example: >> >> Error *err = NULL; >> >> ... code that may set @err ... >> >> if (error is serious) {

Re: [PATCH RESEND v2 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer

2021-09-13 Thread Alistair Francis
On Sun, Sep 12, 2021 at 11:11 PM wrote: > > From: Frank Chang > > Real PDMA doesn't set Control.error if there are 0 bytes to be > transferred. The DMA transfer is still success. > > The following result is PDMA tested in U-Boot on Unmatched board: > > => mw.l 0x300 0x0

Re: [PATCH] target/riscv: Force to set mstatus_hs.[SD|FS] bits in mark_fs_dirty()

2021-09-13 Thread Frank Chang
On Tue, Sep 14, 2021 at 10:10 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 9/13/21 6:37 PM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. > > Modifying the floating-point state when V=1 causes

Re: [PATCH] target/riscv: Force to set mstatus_hs.[SD|FS] bits in mark_fs_dirty()

2021-09-13 Thread Richard Henderson
On 9/13/21 6:37 PM, frank.ch...@sifive.com wrote: From: Frank Chang When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level

[PATCH v2 2/2] vfio/common: Add trace point when a MMIO RAM section less than PAGE_SIZE

2021-09-13 Thread Kunkun Jiang
The MSI-X structures of some devices and other non-MSI-X structures are in the same BAR. They may share one host page, especially in the case of large page granularity, such as 64K. For example, MSIX-Table size of 82599 NIC is 0x30 and the offset in Bar 3(size 64KB) is 0x0. If host page size is

[PATCH v2 1/2] vfio/pci: Fix vfio-pci sub-page MMIO BAR mmaping in live migration

2021-09-13 Thread Kunkun Jiang
We expand MemoryRegions of vfio-pci sub-page MMIO BARs to vfio_pci_write_config to improve IO performance. The MemoryRegions of destination VM will not be expanded successful in live migration, because their addresses have been updated in vmstate_load_state (vfio_pci_load_config). So iterate BARs

[PATCH v2 0/2] vfio: Some fixes about vfio-pci MMIO RAM mapping

2021-09-13 Thread Kunkun Jiang
This series include patches as below: Patch 1: - vfio/pci: Fix vfio-pci sub-page MMIO BAR mmaping in live migration Patch 2: - Added a trace point to informe users when a MMIO RAM ection less than PAGE_SIZE History: v1 -> v2: - Add iterate sub-page BARs in vfio_pci_load_config and try to

[PATCH] target/riscv: Force to set mstatus_hs.[SD|FS] bits in mark_fs_dirty()

2021-09-13 Thread frank . chang
From: Frank Chang When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vsstatus.FS is Dirty at the time mark_fs_dirty() is

[PATCH] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped

2021-09-13 Thread frank . chang
From: Frank Chang When virtual registers are swapped, mstatus.SD bit should also be backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept across the world switches. Signed-off-by: Frank Chang Reviewed-by: Vincent Chen --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2

Re: [RFC PATCH 0/7] linux-user: Streamline handling of SIGSEGV/SIGBUS

2021-09-13 Thread Richard Henderson
On 9/13/21 3:05 PM, Richard Henderson wrote: All of the really tcg-specific portions are still in user-exec.c, and all of the really host-specific portions are now ditributed across linux-user/host//. Importantly, SEGV_MAPERR and SEGV_ACCERR are now passed through from the host kernel -- or at

[PULL 44/44] tcg/arm: More use of the TCGReg enum

2021-09-13 Thread Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 65 +--- 1 file changed, 35 insertions(+), 30 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index cf0627448b..d25e68b36b

[PULL 43/44] tcg/arm: More use of the ARMInsn enum

2021-09-13 Thread Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c068e707e8..cf0627448b 100644 ---

[PULL 37/44] tcg/arm: Simplify use_armv5t_instructions

2021-09-13 Thread Richard Henderson
According to the Arm ARM DDI 0406C, section A1.3, the valid variants are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb. Therefore simplify the test from preprocessor ifdefs to base architecture revision. Retain the "t" in the name to minimize churn. Reviewed-by: Peter Maydell

[PULL 29/44] target/rx: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-22-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/rx/cpu.h

[PULL 30/44] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-23-f4...@amsat.org> Signed-off-by: Richard Henderson ---

[PULL 23/44] target/nios2: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-16-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/nios2/cpu.c

[PULL 24/44] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-17-f4...@amsat.org> Signed-off-by: Richard Henderson ---

[PULL 25/44] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Acked-by: David Gibson Message-Id: <20210911165434.531552-18-f4...@amsat.org> Signed-off-by: Richard Henderson

[PULL 40/44] tcg/arm: Simplify usage of encode_imm

2021-09-13 Thread Richard Henderson
We have already computed the rotated value of the imm8 portion of the complete imm12 encoding. No sense leaving the combination of rot + rotation to the caller. Create an encode_imm12_nofail helper that performs an assert. This removes the final use of the local "rotl" function, which

[PULL 42/44] tcg/arm: Give enum arm_cond_code_e a typedef and use it

2021-09-13 Thread Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 136 +++ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 529728fbbe..c068e707e8

[PULL 15/44] target/arm: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-8-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/arm/cpu.h

[PULL 38/44] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call

2021-09-13 Thread Richard Henderson
ARMv4T has BX as its only interworking instruction. In order to support testing of different architecture revisions with a qemu binary that may have been built for, say ARMv6T2, fill in the blank required to make calls to helpers in thumb mode. Reviewed-by: Peter Maydell Signed-off-by: Richard

[PULL 34/44] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts

2021-09-13 Thread Richard Henderson
From: Ilya Leoshkevich x86_64 dotnet/runtime uses cmpxchg for code patching. When running it under s390x qemu-linux user, cpu_signal_handler() does not recognize this as a write and does not restore PAGE_WRITE cleared by tb_page_add(), incorrectly forwarding the signal to the guest code.

[PULL 13/44] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé do_interrupt() is sysemu specific. However due to some X86 specific hack, it is also used in user-mode emulation, which is why it couldn't be restricted to CONFIG_SOFTMMU (see the comment around added in commit 78271684719: "cpu: tcg_ops: move to tcg-cpu-ops.h, keep

[PULL 33/44] user: Mark cpu_loop() with noreturn attribute

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé cpu_loop() never exits, so mark it with QEMU_NORETURN. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-By: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210905000429.1097336-1-f4...@amsat.org> Signed-off-by: Richard Henderson

[PULL 16/44] target/cris: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-9-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/cris/cpu.h

[PULL 39/44] tcg/arm: Split out tcg_out_ldstm

2021-09-13 Thread Richard Henderson
Expand these hard-coded instructions symbolically. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index

[PULL 27/44] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-20-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/sh4/cpu.h

[PULL 35/44] tcg/arm: Remove fallback definition of __ARM_ARCH

2021-09-13 Thread Richard Henderson
GCC since 4.8 provides the definition and we now require 7.5. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 19 --- 1 file changed, 19 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d113b7f8db..18bb16c784

[PULL 11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Merge two TARGET_X86_64 consecutive blocks. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-4-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/i386/tcg/seg_helper.c | 4

[PULL 26/44] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-Id: <20210911165434.531552-19-f4...@amsat.org> Signed-off-by: Richard Henderson

[PULL 32/44] user: Remove cpu_get_pic_interrupt() stubs

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé cpu_get_pic_interrupt() is now unreachable from user-mode, delete the unnecessary stubs. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-25-f4...@amsat.org> Signed-off-by: Richard

[PULL 10/44] target/i386: Restrict sysemu-only fpu_helper helpers

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict some sysemu-only fpu_helper helpers (see commit 83a3d9c7402: "i386: separate fpu_helper sysemu-only parts"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id:

[PULL 28/44] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-21-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/sparc/cpu.c

[PULL 05/44] tcg: Remove tcg_global_reg_new defines

2021-09-13 Thread Richard Henderson
From: Bin Meng Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210816143507.11200-1-bmeng...@gmail.com> Signed-off-by: Richard Henderson ---

[PULL 20/44] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-13-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/m68k/cpu.h

[PULL 08/44] tcg/arm: Fix tcg_out_vec_op function signature

2021-09-13 Thread Richard Henderson
From: "Jose R. Ziviani" Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op for arm is missing. It causes a build error on armv6 and armv7: tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *' {aka 'const unsigned int *'} declared as a pointer

[PULL 18/44] target/i386: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-11-f4...@amsat.org> Signed-off-by: Richard Henderson ---

[PULL 22/44] target/mips: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-15-f4...@amsat.org> Signed-off-by: Richard Henderson ---

[PULL 17/44] target/hppa: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-10-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/hppa/cpu.h

[PULL 00/44] tcg patch queue, v2

2021-09-13 Thread Richard Henderson
: Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-09-13 13:33:21 +0100) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210913 for you to fetch changes up to 5b778e9b4e0e0a37a86200e6af322b2a9b69c62e

[PULL 41/44] tcg/arm: Drop inline markers

2021-09-13 Thread Richard Henderson
Let the compiler decide about inlining. Remove tcg_out_nop as unused. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 234 +++ 1 file changed, 114 insertions(+), 120 deletions(-) diff --git

[PULL 07/44] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF

2021-09-13 Thread Richard Henderson
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify the ABI for ppc32. Make a good guess based on other symbols. Reported-by: Brad Smith Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-)

[PULL 12/44] target/xtensa: Restrict do_transaction_failed() to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé The do_transaction_failed() is restricted to system emulation since commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id:

[PULL 36/44] tcg/arm: Standardize on tcg_out__{reg,imm}

2021-09-13 Thread Richard Henderson
Some of the functions specified _reg, some _imm, and some left it blank. Make it clearer to which we are referring. Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when we do not actually require BX semantics. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by:

[PULL 09/44] target/avr: Remove pointless use of CONFIG_USER_ONLY definition

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Commit f1c671f96cb ("target/avr: Introduce basic CPU class object") added to target/avr/cpu.h: #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" #endif Remove the CONFIG_USER_ONLY definition introduced by mistake in commit 78271684719

[PULL 06/44] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN

2021-09-13 Thread Richard Henderson
If __APPLE__, ensure that _CALL_DARWIN is set, then remove our local TCG_TARGET_CALL_DARWIN. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index

[PULL 19/44] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Following the logic of commit 30493a030ff ("i386: split seg_helper into user-only and sysemu parts"), move x86_cpu_exec_interrupt() under sysemu/seg_helper.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-By: Warner Losh

[PULL 21/44] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-14-f4...@amsat.org> Signed-off-by: Richard Henderson ---

[PULL 04/44] accel/tcg: remove redundant TCG_KICK_PERIOD define

2021-09-13 Thread Richard Henderson
From: Luc Michel The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h. Remove it from tcg-accel-ops-rr.c. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210811141229.12470-1-lmic...@kalray.eu> Signed-off-by: Richard

[PULL 03/44] tcg/i386: Split P_VEXW from P_REXW

2021-09-13 Thread Richard Henderson
We need to be able to represent VEX.W on a 32-bit host, where REX.W will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ. Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385 Signed-off-by: Richard Henderson

[PULL 31/44] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded. Restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Signed-off-by:

[PULL 14/44] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-13 Thread Richard Henderson
From: Philippe Mathieu-Daudé Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-7-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/alpha/cpu.h

[PULL 02/44] accel/tcg: Clear PAGE_WRITE before translation

2021-09-13 Thread Richard Henderson
From: Ilya Leoshkevich translate_insn() implementations fetch instruction bytes piecemeal, which can cause qemu-user to generate inconsistent translations if another thread modifies them concurrently [1]. Fix by making pages containing translated instruction non-writable right before loading

[PULL 01/44] accel/tcg: Add DisasContextBase argument to translator_ld*

2021-09-13 Thread Richard Henderson
From: Ilya Leoshkevich Signed-off-by: Ilya Leoshkevich [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson --- include/exec/translator.h | 9 + target/arm/arm_ldst.h | 12 ++-- target/alpha/translate.c | 2

[RFC v2 1/2] virtio-gpu: Add support for VIRTIO_GPU_F_RELEASE_FENCE

2021-09-13 Thread Vivek Kasireddy
To support this feature, we add a new queue named rel_fenceq to enqueue finished set_scanout_blob cmds. Cc: Gerd Hoffmann Signed-off-by: Vivek Kasireddy --- hw/display/virtio-gpu-base.c| 3 ++ hw/display/virtio-gpu-udmabuf.c | 4 +- hw/display/virtio-gpu.c

[RFC v2 2/2] ui: Add a plain Wayland backend for Qemu UI

2021-09-13 Thread Vivek Kasireddy
Cc: Gerd Hoffmann Signed-off-by: Vivek Kasireddy --- configure | 8 +- meson.build | 33 +++ meson_options.txt | 2 + qapi/ui.json | 3 + ui/meson.build| 52 ui/wayland.c | 628 ++ 6 files changed, 725

[RFC v2 0/2] ui: Add a Wayland backend for Qemu UI (v2)

2021-09-13 Thread Vivek Kasireddy
Why does Qemu need a new Wayland UI backend? The main reason why there needs to be a plain and simple Wayland backend for Qemu UI is to eliminate the Blit (aka GPU copy) that happens if using a toolkit like GTK or SDL (because they use EGL). The Blit can be eliminated by sharing the dmabuf fd --

[RFC v6] virtio/vsock: add two more queues for datagram types

2021-09-13 Thread Jiang Wang
Datagram sockets are connectionless and unreliable. The sender does not know the capacity of the receiver and may send more packets than the receiver can handle. Add two more dedicate virtqueues for datagram sockets, so that it will not unfairly steal resources from stream and future

[RFC PATCH 2/7] accel/tcg: Split out adjust_signal_pc

2021-09-13 Thread Richard Henderson
Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 8 +++ accel/tcg/user-exec.c | 50 ++--- 2 files changed, 40 insertions(+), 18

[RFC PATCH 3/7] accel/tcg: Split out handle_sigsegv_accerr_write

2021-09-13 Thread Richard Henderson
This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++ accel/tcg/user-exec.c | 96

[RFC PATCH 6/7] linux-user: Handle SIGSEGV/SIGBUS in host_to_target_siginfo_noswap

2021-09-13 Thread Richard Henderson
Remap the faulting address from the host address space into the guest address space. Signed-off-by: Richard Henderson --- linux-user/signal.c | 9 + 1 file changed, 9 insertions(+) diff --git a/linux-user/signal.c b/linux-user/signal.c index a8faea6f09..73c0f9066b 100644 ---

[RFC PATCH 7/7] linux-user: Reorg cpu_signal_handler

2021-09-13 Thread Richard Henderson
Split out two functions into linux-user/host/arch/host-signal.h. Since linux-user requires a linux host, drop all of the BSD and Solaris ifdefs. These should be recreated under bsd-user/ when the current blanks there are filled. Fold the remnants of handle_cpu_signal into host_signal_handler.

[RFC PATCH 1/7] include/exec: Move cpu_signal_handler declaration

2021-09-13 Thread Richard Henderson
There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 13 + target/alpha/cpu.h | 6 -- target/arm/cpu.h|

[RFC PATCH 0/7] linux-user: Streamline handling of SIGSEGV/SIGBUS

2021-09-13 Thread Richard Henderson
Our current setup is: host_signal_handler cpu_signal_handler handle_cpu_signal cc->tcg_ops->tlb_fill raise_exception cpu_loop queue_signal and in the process lose information from the host siginfo_t, which we (mostly) do not recreate properly. Moreover, the

[RFC PATCH 5/7] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller

2021-09-13 Thread Richard Henderson
Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 15 ++- 1 file changed, 2 insertions(+), 13

[RFC PATCH 4/7] accel/tcg: Move clear_helper_retaddr to cpu loop

2021-09-13 Thread Richard Henderson
Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git

Re: question on vhost, limiting kernel threads and NPROC

2021-09-13 Thread Michael S. Tsirkin
On Mon, Sep 13, 2021 at 12:04:04PM -0500, Mike Christie wrote: > I just realized I forgot to cc the virt list so adding now. > > Christian see the very bottom for a different fork patch. > > On 7/12/21 7:05 AM, Stefan Hajnoczi wrote: > > On Fri, Jul 09, 2021 at 11:25:37AM -0500, Mike Christie

Re: [PATCH v9 07/11] hvf: arm: Implement PSCI handling

2021-09-13 Thread Alexander Graf
On 13.09.21 14:30, Peter Maydell wrote: > On Mon, 13 Sept 2021 at 13:02, Alexander Graf wrote: >> >> On 13.09.21 13:44, Peter Maydell wrote: >>> On Mon, 13 Sept 2021 at 12:07, Alexander Graf wrote: To keep your train of thought though, what would you do if we encounter a conduit that

Re: [PATCH v4 22/33] hostmem-epc: Add the reset interface for EPC backend reset

2021-09-13 Thread Jarkko Sakkinen
On Mon, 2021-09-13 at 20:37 +, Sean Christopherson wrote: > On Mon, Sep 13, 2021, Jarkko Sakkinen wrote: > > On Fri, 2021-09-10 at 17:10 +0200, Paolo Bonzini wrote: > > > On 19/07/21 13:21, Yang Zhong wrote: > > > > +void sgx_memory_backend_reset(HostMemoryBackend *backend, int fd, > > > > +

RE: [qemu-hexagon] Error mapping file: Invalid argument

2021-09-13 Thread Waksmanski, Lukasz
Thanks for pointing me to the toolchain. I'll give it a try to see how it works. However, I'm more interested in being able to use qemu-hexagon as shown in my example below (QuRT). Is it possible? What kind of modifications qemu would require to make it happen? Cheers, Lukasz. -Original

RE: [qemu-hexagon] Error mapping file: Invalid argument

2021-09-13 Thread Brian Cain
> -Original Message- > From: Philippe Mathieu-Daudé On > Behalf Of Philippe Mathieu-Daudé > Sent: Monday, September 13, 2021 3:19 PM > To: Waksmanski, Lukasz ; qemu- > de...@nongnu.org > Cc: Taylor Simpson ; Brian Cain > > Subject: Re: [qemu-hexagon] Error mapping file: Invalid argument

Re: [PATCH v4 22/33] hostmem-epc: Add the reset interface for EPC backend reset

2021-09-13 Thread Sean Christopherson
On Mon, Sep 13, 2021, Jarkko Sakkinen wrote: > On Fri, 2021-09-10 at 17:10 +0200, Paolo Bonzini wrote: > > On 19/07/21 13:21, Yang Zhong wrote: > > > +void sgx_memory_backend_reset(HostMemoryBackend *backend, int fd, > > > + Error **errp) > > > +{ > > > +

Re: [PATCH] target/ppc: Fix 64-bit decrementer

2021-09-13 Thread Peter Maydell
On Mon, 13 Sept 2021 at 19:09, Luis Fernando Fujita Pires wrote: > > > > value = extract64(value, 0, nr_bits); > > > value = ((target_long)value << (64 - nr_bits)) >> (64 - nr_bits); > > > > Oops, sorry. 64 might not be correct here. It would depend on the target > > being > > either 32

Re: [qemu-hexagon] Error mapping file: Invalid argument

2021-09-13 Thread Philippe Mathieu-Daudé
Cc'ing Hexagon team. On 9/13/21 8:38 PM, Waksmanski, Lukasz wrote: > Hello, > >   > > I’m trying to run Hexagon executables in qemu-hexagon. I’m using > official stable version v6.1. Here’s my rather simple program: > > ➜  ~ cat test.c > > #include > > int main() > > {  printf("Hello

Re: [PATCH v4 22/33] hostmem-epc: Add the reset interface for EPC backend reset

2021-09-13 Thread Jarkko Sakkinen
On Fri, 2021-09-10 at 17:10 +0200, Paolo Bonzini wrote: > On 19/07/21 13:21, Yang Zhong wrote: > > +void sgx_memory_backend_reset(HostMemoryBackend *backend, int fd, > > + Error **errp) > > +{ > > +MemoryRegion *mr = >mr; > > + > > +mr->enabled = false; > > + >

[PULL v4 00/23] target-arm queue

2021-09-13 Thread Peter Maydell
100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0

[qemu-hexagon] Error mapping file: Invalid argument

2021-09-13 Thread Waksmanski, Lukasz
Hello, I’m trying to run Hexagon executables in qemu-hexagon. I’m using official stable version v6.1. Here’s my rather simple program: ➜ ~ cat test.c #include int main() { printf("Hello Hexagon!"); return 0; } I’m using Hexagon SDK 4.0.2 toolchain: ➜ ~

Re: [PATCH] target/ppc: Fix 64-bit decrementer

2021-09-13 Thread Cédric Le Goater
On 9/13/21 8:05 PM, Luis Fernando Fujita Pires wrote: >>> value = extract64(value, 0, nr_bits); >>> value = ((target_long)value << (64 - nr_bits)) >> (64 - nr_bits); >> >> Oops, sorry. 64 might not be correct here. It would depend on the target >> being >> either 32 or 64. > > In fact,

Re: [PATCH 2/2] target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l]

2021-09-13 Thread Daniel Henrique Barboza
On 9/9/21 5:34 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst PowerISA v3.0B made tlbie[l] hypervisor privileged when PSR=0 and HR=1. To allow the check at translation time, we'll use the HR bit of LPCR to check the MMU mode instead of the PATE.HR. Signed-off-by: Matheus

Re: [PATCH 1/2] target/ppc: add LPCR[HR] to DisasContext and hflags

2021-09-13 Thread Daniel Henrique Barboza
On 9/9/21 5:34 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Add a Host Radix field (hr) in DisasContext with LPCR[HR] value to allow us to decide between Radix and HPT while validating instructions arguments. Note that PowerISA v3.1 does not require LPCR[HR] and PATE.HR to

Re: [PATCH] hw/i386/acpi-build: adjust q35 IO addr range for acpi pci hotplug

2021-09-13 Thread Michael S. Tsirkin
On Wed, Sep 08, 2021 at 10:43:51AM +0200, Igor Mammedov wrote: > On Wed, 8 Sep 2021 12:51:04 +0530 (IST) > Ani Sinha wrote: > > > On Wed, 8 Sep 2021, Igor Mammedov wrote: > > > > > On Wed, 8 Sep 2021 09:41:39 +0530 > > > Ani Sinha wrote: > > > > > > > Change caf108bc58790

Re: [PATCH] linux-user: Check lock_user result for ip_mreq_source sockopts

2021-09-13 Thread Laurent Vivier
Le 09/08/2021 à 17:54, Peter Maydell a écrit : > In do_setsockopt(), the code path for the options which take a struct > ip_mreq_source (IP_BLOCK_SOURCE, IP_UNBLOCK_SOURCE, > IP_ADD_SOURCE_MEMBERSHIP and IP_DROP_SOURCE_MEMBERSHIP) fails to > check the return value from lock_user(). Handle this in

Re: [PATCH v2] linux-user: Correct host errno for IP[V6]_RECVERR socket options

2021-09-13 Thread Laurent Vivier
Le 11/09/2021 à 19:08, Philippe Mathieu-Daudé a écrit : > Host errno must be converted to target errno in IP_RECVERR > and IPV6_RECVERR socket options. > > Fixes: ee1ac3a1822 ("linux-user: Add sockopts for IPv6") > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/602 > Reported-by: Conrad

Re: [PATCH v2 0/9] linux-user: split internals out of qemu.h

2021-09-13 Thread Laurent Vivier
Le 08/09/2021 à 17:43, Peter Maydell a écrit : > linux-user/qemu.h is an awkward header, for two reasons: > (1) its name suggests it's a rather common generic header, > but it's actually specific to the usermode emulators > (2) it is a mix of: >* lots of things internal to the

[PULL v3 00/23] target-arm queue

2021-09-13 Thread Peter Maydell
://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-2 for you to fetch changes up to eec607843ca81eccab238fce86222be9c78b3675: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:45:02 +0100

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