it replaces error-prone pointer arithmetic for build_header() API,
with 2 calls to start and finish table creation,
which hides offsets magic from API user.
Signed-off-by: Igor Mammedov
Reviewed-by: Eric Auger
---
v4:
* drop not related "vgia_offset = table_data->len" newline change
it replaces error-prone pointer arithmetic for build_header() API,
with 2 calls to start and finish table creation,
which hides offsets magic from API user.
Also since acpi_table_begin() reserves space only for standard header
while previous acpi_data_push() reserved the header + 4 bytes field,
On 9/21/21 11:14 PM, Warner Losh wrote:
Some architecutres publish AT_HWCAP2 as well as AT_HWCAP. Those
architectures will define this in their target_arch_elf.h files. If it
is defined, then publish it.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/target_os_elf.h | 4
1 file
Peter Maydell writes:
> On Mon, 18 Feb 2019 at 14:19, Markus Armbruster wrote:
>>
>> From: Marc-André Lureau
>>
>> A few targets don't emit RTC_CHANGE, we could restrict the event to
>> the tagets that do emit it.
>>
>> Note: There is a lot more of events & commands that we could restrict
>>
it replaces error-prone pointer arithmetic for build_header() API,
with 2 calls to start and finish table creation,
which hides offsets magic from API user.
While at it switch to build_append_int_noprefix() to build
entries to other tables (which also removes some manual offset
calculations).
On 9/21/21 11:14 PM, Warner Losh wrote:
The used field of TaskState is write only. Eliminate it.
Signed-off-by: Warner Losh
---
bsd-user/main.c | 1 -
bsd-user/qemu.h | 1 -
2 files changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
it replaces error-prone pointer arithmetic for build_header() API,
with 2 calls to start and finish table creation,
which hides offsets magic from API user.
Signed-off-by: Igor Mammedov
Reviewed-by: Eric Auger
---
v3:
* s/acpi_init_table|acpi_table_composed/acpi_table_begin|acpi_table_end/
it replaces error-prone pointer arithmetic for build_header() API,
with 2 calls to start and finish table creation,
which hides offests magic from API user.
While at it switch to build_append_int_noprefix() to build
entries to other tables (which also removes some manual offset
calculations).
On 9/21/21 11:14 PM, Warner Losh wrote:
All architectures have a ELF_HWCAP, so remove the fallback ifdef.
Place ELF_HWCAP in the same order as on native FreeBSD.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/target_os_elf.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
On 9/21/21 11:14 PM, Warner Losh wrote:
To avoid a name clash with FreeBSD's sigqueue data structure in
signalvar.h, rename sigqueue to qemu_sigqueue. This sturcture
is currently defined, but unused.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 14 +++---
1 file changed, 7
On 9/21/21 11:14 PM, Warner Losh wrote:
Make get_errno and is_error global so files other than syscall.c can use
them.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h| 4
bsd-user/syscall.c | 10 +-
2 files changed, 9 insertions(+), 5 deletions(-)
Reviewed-by: Richard
On 9/21/21 11:14 PM, Warner Losh wrote:
+/* sysarch() is architecture dependent. */
+abi_long do_freebsd_sysarch(void *cpu_env, abi_long arg1, abi_long arg2)
+{
+
+return do_freebsd_arch_sysarch(cpu_env, arg1, arg2);
+}
Extra newline. Otherwise,
Reviewed-by: Richard Henderson
r~
On 9/21/21 11:14 PM, Warner Losh wrote:
Convert the #ifdef'd i386 code to calling the i386 sysarch code we have
living in i386,x86_64/target_arch_sysarch.h do_freebsd_arch_sysarch
rather than having a separate copy. This is in preparation to remove it
entirely.
Signed-Off-By: Warner Losh
---
On 9/21/21 11:14 PM, Warner Losh wrote:
+void stop_all_tasks(void)
+{
+/*
+ * We trust when using NPTL (pthreads) start_exclusive() handles thread
+ * stopping correctly.
+ */
+start_exclusive();
+}
Eh. It begs the question of why this is present, as opposed to calling
On 9/21/21 9:56 PM, Warner Losh wrote:
MAP_ANON and MAP_ANONYMOUS are identical. Prefer MAP_ANON for BSD since
the file is now a confusing mix of the two.
Signed-off-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
---
bsd-user/mmap.c | 11 +--
1 file changed, 5 insertions(+), 6
On 9/21/21 11:14 PM, Warner Losh wrote:
Signed-off-by: Warner Losh
---
bsd-user/i386/target_arch_cpu.h | 2 --
bsd-user/x86_64/target_arch_cpu.h | 2 --
2 files changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/21/21 11:14 PM, Warner Losh wrote:
Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's
FreeBSD-wide.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/target_os_signal.h | 3 +++
bsd-user/i386/target_arch_signal.h | 2 --
bsd-user/x86_64/target_arch_signal.h | 2 --
+/* fallthrough */
+default:
+tcg_out_mov(s, size == MO_64, l->datalo_reg, TCG_REG_A0);
+break;
Here in tcg_out_qemu_ld_slow_path, "size == MO_64" is "type".
+/* TLB Hit - translate address using addend. */
+if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+
On 9/21/21 11:14 PM, Warner Losh wrote:
Signed-off-by: Warner Losh
---
bsd-user/freebsd/strace.list | 11 ---
1 file changed, 11 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/21/21 11:14 PM, Warner Losh wrote:
From: Stacey Son
To emulate signals and interrupted system calls, we need to have the
same mechanisms we have in the kernel, including these errno values.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/errno_defs.h | 14
On 9/22/21 11:35 AM, Taylor Simpson wrote:
+static inline void probe_store(CPUHexagonState *env, int slot, int mmu_idx)
+{
+if (!(env->slot_cancelled & (1 << slot))) {
+size1u_t width = env->mem_log_stores[slot].width;
+target_ulong va = env->mem_log_stores[slot].va;
+
On 9/21/21 9:56 PM, Warner Losh wrote:
Similar to the equivalent linux-user change 86abac06c14. All error
conditions that target_mprotect checks are also checked by target_mmap.
EACCESS cannot happen because we are just removing PROT_WRITE. ENOMEM
should not happen because we are modifying a
On 9/21/21 9:56 PM, Warner Losh wrote:
mmap should return ENOMEM on len overflow rather than EINVAL. Return
EINVAL when len == 0 and ENOMEM when the rounded to a page length is 0.
Found by make check-tcg.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 9 -
1 file changed, 8
On 9/21/21 9:56 PM, Warner Losh wrote:
+/* Reject the mapping if any page within the range is mapped */
+if (flags & MAP_EXCL) {
+for (addr = start; addr < end; addr++) {
+if (page_get_flags(addr) != 0)
+goto fail;
+}
+
On 9/22/21 11:09 AM, WANG Xuerui wrote:
Following up on previous, I suggest:
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+if (type == TCG_TYPE_I32) {
+val = (int32_t)val;
+}
+
+/* Single-instruction
On 9/21/21 9:56 PM, Warner Losh wrote:
/* no page was there, so we allocate one */
void *p = mmap(host_start, qemu_host_page_size, prot,
- flags | MAP_ANON, -1, 0);
+ flags | ((fd != -1) ? MAP_ANON : 0), -1, 0);
I don't understand
On 9/21/21 9:56 PM, Warner Losh wrote:
All these MAP_ symbols are always defined on supported FreeBSD versions
(12.2 and newer), so remove the #ifdefs since they aren't needed.
Signed-off-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
---
bsd-user/mmap.c | 14 --
1 file
On 9/21/21 9:56 PM, Warner Losh wrote:
From: Mikaël Urankar
Similar to the equivalent linux-user commit e6deac9cf99
When mapping MAP_ANONYMOUS memory fragments, still need notice about to
set it zero, or it will cause issues.
Signed-off-by: Mikaël Urankar
Signed-off-by: Warner Losh
---
On 9/21/21 9:56 PM, Warner Losh wrote:
Keep the shifted expression on one line. It's the same number of lines
and easier to read like this.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/bsd-user/mmap.c
On 9/21/21 9:56 PM, Warner Losh wrote:
From: Mikaël Urankar
Simmilar to the equivalent linux-user: commit fb7e378cf9c, which added
checking to pread's return value.
Signed-off-by: Mikaël Urankar
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 6 --
1 file changed, 4 insertions(+), 2
From: Yang Zhong
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as
There's a typo in Hervé's address.
Fixing it from hpus...@reactos.org to hpous...@reactos.org .
On Fri, 24 Sep 2021 19:55:33 +1000
David Gibson wrote:
> Greg and I are moving towards other areas and no longer have capacity to
> act as regular reviewers for several of the secondary ppc machine
From: Yang Zhong
The QMP and HMP interfaces can be used by monitor or QMP tools to retrieve
the SGX information from VM side when SGX is enabled on Intel platform.
Signed-off-by: Yang Zhong
Message-Id: <20210910102258.46648-2-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-22-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
hw/i386/pc_piix.c | 1 +
1 file changed,
From: Sean Christopherson
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI
From: Sean Christopherson
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-19-yang.zh...@intel.com>
Signed-off-by:
From: Sean Christopherson
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the
On Fri, 24 Sep 2021 19:55:35 +1000
David Gibson wrote:
> The OpenPIC interrupt controller was once the de facto standard on ppc
> machines. In qemu it's now only used on some Macintosh and the
> Freescale e500 machine. It has no listed maintainer, and as far as I
> know, no-one who's really
From: Sean Christopherson
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson
From: Yang Zhong
Libvirt can use query-sgx-capabilities to get the host
sgx capabilities to decide how to allocate SGX EPC size to VM.
Signed-off-by: Yang Zhong
Message-Id: <20210910102258.46648-3-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
hw/i386/sgx-stub.c | 6
From: Sean Christopherson
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
From: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-34-yang.zh...@intel.com>
[Convert to reStructuredText, and adopt the standard === --- ~~~ headings
suggested for example by Linux. - Paolo]
Signed-off-by: Paolo Bonzini
From: Sean Christopherson
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-16-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 5 +
1 file changed, 5 insertions(+)
From: Sean Christopherson
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic
From: Sean Christopherson
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id:
From: Sean Christopherson
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-21-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
hw/i386/pc_q35.c | 1 +
1 file changed, 1
From: Sean Christopherson
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson
From: Sean Christopherson
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic
From: Sean Christopherson
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-12-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
target/i386/kvm/kvm.c | 5
From: Sean Christopherson
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
From: Sean Christopherson
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
From: Sean Christopherson
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
From: Sean Christopherson
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
This version includes a lot of the changes that were pointed out in
the review of the previous versions. I apologize for rushing things
in to make it before the conference break.
Paolo
Changes from v4:
- removed RESET handling, which will use a dedicated kernel API
- cleaned up stubs
From: Yang Zhong
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX since v6.1, or the sgx backend
object cannot bootup.
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-4-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
From: Sean Christopherson
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson
From: Sean Christopherson
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
From: Yang Zhong
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong
Message-Id: <20210719112136.57018-32-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
configs/devices/i386-softmmu/default.mak | 1 +
On 9/24/21 11:55, David Gibson wrote:
qemu/KVM on Power is no longer my primary job responsibility, nor Greg
Kurz'. I still have some time for upstream maintenance, but it's no longer
accurate to say that I'm paid to do so. Therefore, reduce sPAPR (the
"pseries" machine type) from Supported to
On 9/24/21 11:55, David Gibson wrote:
qemu/KVM on Power is no longer my primary job responsibility, nor Greg
Kurz'. I still have some time for upstream maintenance, but it's no longer
accurate to say that I'm paid to do so. Therefore, reduce sPAPR (the
"pseries" machine type) from Supported to
On 9/24/21 11:55, David Gibson wrote:
Greg and I are moving towards other areas and no longer have capacity to
act as regular reviewers for several of the secondary ppc machine types.
So, remove ourselves as reviewers for Macintosh, PReP, sam460ex and
pegasos2 in MAINTAINERS.
Signed-off-by:
On 9/24/21 11:55, David Gibson wrote:
There are a nunber of old embedded ppc machine types which have been little
changed and in "Odd Fixes" state for a long time. With both myself and
Greg Kurz moving toward other areas, we no longer have the capacity to
keep reviewing and maintaining even the
On 9/24/21 11:55, David Gibson wrote:
The OpenPIC interrupt controller was once the de facto standard on ppc
machines. In qemu it's now only used on some Macintosh and the
Freescale e500 machine. It has no listed maintainer, and as far as I
know, no-one who's really familiar with it any more.
On 9/24/21 11:55, David Gibson wrote:
With our interests moving to other areas, Greg and myself no longer have
capacity to be regular reviewers of code for the powernv machine type, let
alone co-maintainers. Additionally, not being IBM employees, we don't have
easy access to the hardware
Hello Titus,
On 9/24/21 10:42, Philippe Mathieu-Daudé wrote:
On 9/24/21 01:48, Titus Rwantare wrote:
Hello all,
I'd like some clarification on how the following code transfers irqs
back and forth:
b/hw/arm/aspeed_soc.c
+ /* iBT */
+ if (!sysbus_realize(SYS_BUS_DEVICE(>ibt), errp)) {
+
On Fri, 24 Sep 2021, David Gibson wrote:
Greg and I are moving towards other areas and no longer have capacity to
act as regular reviewers for several of the secondary ppc machine types.
So, remove ourselves as reviewers for Macintosh, PReP, sam460ex and
pegasos2 in MAINTAINERS.
Signed-off-by:
On Fri, 24 Sep 2021, Philippe Mathieu-Daudé wrote:
On 9/24/21 09:16, Mark Cave-Ayland wrote:
On 23/09/2021 15:16, BALATON Zoltan wrote:
On Thu, 23 Sep 2021, Mark Cave-Ayland wrote:
Convert nubus_device_realize() to use a bitmap to manage available slots
to allow
for future Nubus devices to
Greg Kurz and myself have been co-maintainers for the ppc and ppc64
targets for some time now. However, both our day job responsibilities
and interests are leading us towards other areas, so we have less time
to devote to this any more.
Therefore, here's a bunch of updates to MAINTAINERS,
On 24/09/2021 10:01, Philippe Mathieu-Daudé wrote:
On 9/24/21 09:06, Mark Cave-Ayland wrote:
On 23/09/2021 10:49, Philippe Mathieu-Daudé wrote:
On 9/23/21 11:13, Mark Cave-Ayland wrote:
Each Nubus slot has an IRQ line that can be used to request service from the
CPU. Connect the IRQs to the
All TCG targets implement the TCGCPUOps::has_work() handler.
We can remove the non-NULL handler check in tcg_cpu_has_work().
Add an assertion in tcg_exec_realizefn() for future TCG targets.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c | 4
accel/tcg/tcg-accel-ops.c
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2047742d03c..fb2116dc52e 100644
--- a/target/sh4/cpu.c
+++
The OpenPIC interrupt controller was once the de facto standard on ppc
machines. In qemu it's now only used on some Macintosh and the
Freescale e500 machine. It has no listed maintainer, and as far as I
know, no-one who's really familiar with it any more.
Since I'm moving away from the area, I
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 25a4aa2976d..ac6b40b2716 100644
--- a/target/rx/cpu.c
+++
Am 23.09.2021 um 15:04 hat Paolo Bonzini geschrieben:
> Linux limits the size of iovecs to 1024 (UIO_MAXIOV in the kernel
> sources, IOV_MAX in POSIX). Because of this, on some host adapters
> requests with many iovecs are rejected with -EINVAL by the
> io_submit() or readv()/writev() system
We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is
a const structure, so to avoid creating multiple versions of
the same structure, simply changing the has_work() handler,
introduce yet another indirection with a has_work() handler in
PowerPCCPUClass, and ppc_cpu_has_work() method
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index b95682b7f04..419fa624bd5 100644
---
qemu/KVM on Power is no longer my primary job responsibility, nor Greg
Kurz'. I still have some time for upstream maintenance, but it's no longer
accurate to say that I'm paid to do so. Therefore, reduce sPAPR (the
"pseries" machine type) from Supported to Maintained.
Signed-off-by: David
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
Greg and I are moving towards other areas and no longer have capacity to
act as regular reviewers for several of the secondary ppc machine types.
So, remove ourselves as reviewers for Macintosh, PReP, sam460ex and
pegasos2 in MAINTAINERS.
Signed-off-by: David Gibson
Reviewed-by: Greg Kurz
---
The SPARC target only support TCG acceleration. Remove the CONFIG_TCG
definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 15db277925f..36e6e540483 100644
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 66d22d11895..ad5d26b5c9e 100644
--- a/target/m68k/cpu.c
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7b7b05f1d3a..df8ade9021d 100644
---
With our interests moving to other areas, Greg and myself no longer have
capacity to be regular reviewers of code for the powernv machine type, let
alone co-maintainers. Additionally, not being IBM employees, we don't have
easy access to the hardware information we'd need for good review.
There are a nunber of old embedded ppc machine types which have been little
changed and in "Odd Fixes" state for a long time. With both myself and
Greg Kurz moving toward other areas, we no longer have the capacity to
keep reviewing and maintaining even the rare patches that come in for those
has_work() is sysemu specific, and Hexagon target only provides
a linux-user implementation. Remove the unused hexagon_cpu_has_work().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 27cb04152f9..3c368a1bde7 100644
---
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1e..9938d7c2919 100644
---
Introduce a target-specific has_work() handler for TCG.
Eventually call it from tcg_cpu_has_work(), our
AccelOpsClass::has_work() handler.
Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 4
accel/tcg/tcg-accel-ops.c | 4
2
Now that all TCG targets converted their CPUClass::has_work()
handler to a TCGCPUOps::has_work() one, we can remove has_work
from CPUClass.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 2 --
accel/tcg/tcg-accel-ops.c | 3 ---
2 files
Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work()
- SysemuCPUOps::has_work() implementation - to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu-qom.h | 4 +++-
target/ppc/cpu_init.c | 24 ++--
2 files changed,
All accelerators but TCG implement their AccelOpsClass::has_work()
handler, meaning all the remaining CPUClass::has_work() ones are
only reachable from TCG accelerator; and these has_work() handlers
belong to TCGCPUOps.
We will gradually move each target CPUClass::has_work() to
TCGCPUOps in the
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/cpu.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c1cbd03595e..5cb19a88819 100644
---
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 00e0c55d0e4..3639c03f8ea 100644
---
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 6 --
target/i386/tcg/tcg-cpu.c | 8 +++-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Hi Cris and Marek, could you help me get this series merged?
On 9/23/21 17:14, Laurent Vivier wrote:
Le 18/09/2021 à 11:19, Philippe Mathieu-Daudé a écrit :
Cc'ing qemu-trivial@ (series fully reviewed).
An Acked-by from one of NiosII maintainers would be welcome.
Thanks,
Laurent
On
Implement QTest has_work() handler in AccelOpsClass.
Since no CPU are available under QTest accelerator,
this function is not reachable.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/qtest/qtest.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/qtest/qtest.c
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0d252cb5bdc..8d61bf15f6c 100644
---
ARM v7M cores inherit TYPE_ARM_CPU, so TYPE_ARM_CPU's class_init runs
first and sets up most of the class fields, setting in particular the
has_work handler to the generic arm_cpu_has_work(). Thus M-profile
and A-profile share the same arm_cpu_has_work() function. Some of the
checks the code there
201 - 300 of 384 matches
Mail list logo
