Ping?
Markus Armbruster writes:
> Commit 6287d827d4 "monitor: allow device_del to accept QOM paths"
> extended find_device_state() to accept QOM paths in addition to qdev
> IDs. This added a checked conversion to TYPE_DEVICE at the end, which
> duplicates the check done for the qdev ID case
Markus Armbruster writes:
> Markus Armbruster writes:
>
>> Did this series fall through the cracks for 6.1?
>
> Missed 6.1. What now?
If I understand this correctly, it's a regression in 6.1. Paolo, please
advise on what should be done.
>> Jean-Philippe Brucker writes:
>>
>>> Since commit
Daniel P. Berrangé writes:
> On Fri, Oct 01, 2021 at 07:08:51PM +0200, Paolo Bonzini wrote:
>> On 29/09/21 04:58, Yanan Wang wrote:
>> > @@ -933,8 +935,7 @@ static void machine_set_smp(Object *obj, Visitor *v,
>> > const char *name,
>> > return;
>> > }
>> > -smp_parse(ms,
Hi Alex,
I've tried to use
make check-tcg CORE=test_kc705_be CROSS_CC_GUEST=xtensa-test_kc705_be-elf-gcc
to run TCG tests for a big-endian xtensa core. I thought the following change
would be sufficient to do it:
---8<---
diff --git a/tests/tcg/xtensa/Makefile.softmmu-target
> Not at the moment but it would certainly be a useful addition for the
> unit tests if we could test arbitrary sequences of TCG ops. I'm not sure
> how much test harness would be needed to exercise that though.
On a related note, in addition to testing TCG->Host translation, it
would be nice to
On 9/30/21 10:57 AM, Paolo Bonzini wrote:
The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9:
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request'
into staging (2021-09-29 21:20:49 +0100)
are available in the Git repository at:
> -Original Message-
> From: Brian Cain
...
> > -Original Message-
> > From: Richard Henderson
> ...
> > On 10/1/21 12:59 PM, Brian Cain wrote:
> > > Alex,
> > >
> > > We need to update the docker container used for hexagon for new test
> cases
> > proposed in Taylor's recent
On Tue, 21 Sep 2021 07:02:01 +0800
"Longpeng(Mike)" wrote:
> Commit ecebe53fe993 ("vfio: Avoid disabling and enabling vectors
> repeatedly in VFIO migration") avoid inefficiently disabling and
s/avoid/avoids/
> enabling vectors repeatedly and let the unmasked vectors to be
s/let/lets/ s/to//
On Tue, 21 Sep 2021 07:02:00 +0800
"Longpeng(Mike)" wrote:
> 'defer_kvm_irq_routing' indicates whether we should defer to commit
> the kvm routing.
>
> Signed-off-by: Longpeng(Mike)
> ---
> hw/vfio/pci.c | 43 ++-
> hw/vfio/pci.h | 1 +
> 2 files
On Tue, 21 Sep 2021 07:02:02 +0800
"Longpeng(Mike)" wrote:
> In migration resume phase, all unmasked msix vectors need to be
> setup when load the VF state. However, the setup operation would
s/load/loading/
> take longer if the VM has more VFs and each VF has more unmasked
> vectors.
>
> The
On Tue, 21 Sep 2021 07:01:57 +0800
"Longpeng(Mike)" wrote:
> 'msix_function_masked' is synchronized with the device's config,
> we can use it to replace the complex conditional statementis in
> msix_set/unset_vector_notifiers.
>
> Signed-off-by: Longpeng(Mike)
> ---
> hw/pci/msix.c | 6 ++
> -Original Message-
> From: Richard Henderson
> Sent: Friday, October 1, 2021 12:12 PM
> To: qemu-devel@nongnu.org
> Cc: laur...@vivier.eu; alex.ben...@linaro.org; Taylor Simpson
>
> Subject: [PATCH v3 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill
>
> The fallback code in
On Fri, 1 Oct 2021, 18:59 Brian Cain, wrote:
> > -Original Message-
> > From: Richard Henderson
> ...
> > On 10/1/21 12:59 PM, Brian Cain wrote:
> > > Alex,
> > >
> > > We need to update the docker container used for hexagon for new test
> cases
> > proposed in Taylor's recent patch
Hello,
This is a first attempt to make some progress with the problems found
with OHCI especially when trying to pass through a usb sound card on
mac99. This does not go all the way to allow multiple async packets on
different endpoints yet but as a first step just try to fix the
interaction and
Since isochronous transfers cannot be handled async (the function
returns error in that case) we don't need to remember the packet.
Avoid using the usb_pkt in OHCIState (as that can be a waiting async
packet on another endpoint) and allocate and use a local USBPacket for
the iso transfer instead.
These two do the same and only used once so no need to have two
functions, simplify by merging them.
Signed-off-by: BALATON Zoltan
---
hw/usb/hcd-ohci.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index
This is always done before calling this function so remove duplicated
code and do it within the function at one place.
Signed-off-by: BALATON Zoltan
---
hw/usb/hcd-ohci.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index
This also allows removing two forward declarations
Signed-off-by: BALATON Zoltan
---
hw/usb/hcd-ohci.c | 204 +++---
1 file changed, 100 insertions(+), 104 deletions(-)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 405abbb62d..f8761370e3
On Thu, Sep 30, 2021 at 10:48:09AM +0100, Stefan Hajnoczi wrote:
> On Thu, Sep 30, 2021 at 05:29:06AM +, Raphael Norwitz wrote:
> > On Tue, Sep 28, 2021 at 10:55:00AM +0200, Stefan Hajnoczi wrote:
> > > On Mon, Sep 27, 2021 at 05:17:01PM +, Raphael Norwitz wrote:
> > > > In the
On Fri, Oct 1, 2021 at 10:15 AM Richard Henderson
wrote:
>
> The fallback code in raise_sigsegv is sufficient for xtensa.
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.h | 2 +-
>
On Fri, Oct 01, 2021 at 10:21:36AM +0200, Kevin Wolf wrote:
> Am 30.09.2021 um 23:28 hat John Snow geschrieben:
> > Hiya, I was talking this over with Hanna in review to '[PATCH v3 00/16]
> > python/iotests: Run iotest linters during Python CI' [1] and I have some
> > doubt about what you'd
On Fri, Oct 1, 2021 at 4:21 AM Kevin Wolf wrote:
> Am 30.09.2021 um 23:28 hat John Snow geschrieben:
> > Hiya, I was talking this over with Hanna in review to '[PATCH v3 00/16]
> > python/iotests: Run iotest linters during Python CI' [1] and I have some
> > doubt about what you'd personally like
On Fri, Oct 1, 2021 at 10:11 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Pylint informs us we're not using these arguments. Oops, it's
> > right. Correct the error message and remove the remaining unused
> > parameter.
> >
> > Fix test output now that the error message is improved.
>
Added a check in vhost_vsock_common_send_transport_reset,
and only send messages on event queue when the vsock host
device is started.
Suggested-by: Stefano Garzarella
Signed-off-by: Jiang Wang
---
hw/virtio/vhost-vsock-common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff
On 10/1/2021 1:54 PM, Brad Smith wrote:
On 10/1/2021 5:44 AM, Daniel P. Berrangé wrote:
On Fri, Oct 01, 2021 at 10:37:51AM +0100, Peter Maydell wrote:
On Fri, 1 Oct 2021 at 10:10, Daniel P. Berrangé
wrote:
On Thu, Sep 30, 2021 at 09:10:12AM +0200, Thomas Huth wrote:
On 27/08/2021 14.09,
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
q35 machine.
Since the test instantiates a virtio device and two PCIe expander
bridges, DSDT.viot has more blocks than the base DSDT (long diff not
shown here). The VIOT table generated for the q35 test is:
[000h 4]
Create empty data files and allow updates for the upcoming VIOT tests.
Signed-off-by: Jean-Philippe Brucker
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/DSDT.viot | 0
tests/data/acpi/q35/VIOT.viot | 0
tests/data/acpi/virt/VIOT
Add two test cases for VIOT, one on the q35 machine and the other on
virt. To test complex topologies the q35 test has two PCIe buses that
bypass the IOMMU (and are therefore not described by VIOT), and two
buses that are translated by virtio-iommu.
Signed-off-by: Jean-Philippe Brucker
---
We're about to need this check for a third vIOMMU, virtio-iommu, which
doesn't inherit X86IOMMUState as it doesn't support IRQ remapping and is
a virtio device. Move the check into the pre_plug callback to be shared
by all three vIOMMUs.
Signed-off-by: Jean-Philippe Brucker
---
hw/i386/pc.c
> -Original Message-
> From: Richard Henderson
...
> On 10/1/21 12:59 PM, Brian Cain wrote:
> > Alex,
> >
> > We need to update the docker container used for hexagon for new test cases
> proposed in Taylor's recent patch series under review. Thankfully, CodeLinaro
> has provided a binary
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
table.
Reviewed-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt-acpi-build.c | 7 +++
hw/arm/Kconfig | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c
Allow instantiating a virtio-iommu device by adding an ACPI Virtual I/O
Translation table (VIOT), which describes the relation between the
virtio-iommu and the endpoints it manages.
Add a hotplug handler for virtio-iommu on x86 and set the necessary
reserved region property. On x86, the
To propagate errors to the caller of the pre_plug callback, use the
object_poperty_set*() functions directly instead of the qdev_prop_set*()
helpers.
Suggested-by: Igor Mammedov
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
The previous calculation fell over when I tried to create a 8gb Pi 4
because the values where only 32 bit. However the quirk of the Pi
hardware is the vcram can only appear in the first 1gb of address
space. This also limits where the initial kernel and DTB can be
loaded (notice the DTS for the
Move the masking of the address from cpu_loop into
s390_cpu_record_sigsegv -- this is governed by hw, not linux.
This does mean we have to raise our own exception, rather
than return to the fallback.
Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING.
Use the appropriate si_code for
On 10/1/2021 5:44 AM, Daniel P. Berrangé wrote:
On Fri, Oct 01, 2021 at 10:37:51AM +0100, Peter Maydell wrote:
On Fri, 1 Oct 2021 at 10:10, Daniel P. Berrangé wrote:
On Thu, Sep 30, 2021 at 09:10:12AM +0200, Thomas Huth wrote:
On 27/08/2021 14.09, Thomas Huth wrote:
The dtc submodule is
On 10/1/21 12:59 PM, Brian Cain wrote:
Alex,
We need to update the docker container used for hexagon for new test cases
proposed in Taylor's recent patch series under review. Thankfully, CodeLinaro
has provided a binary of the hexagon cross toolchain so now I think we can
simplify the
Because the linux-user kuser page handling is currently implemented
by detecting magic addresses in the unnamed 0xaa trap, we cannot
simply remove nios2_cpu_tlb_fill and rely on the fallback code.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h| 6 ++
target/nios2/cpu.c| 6
We have replaced tlb_fill with record_sigsegv for user mod.
Move the declaration to restrict it to system emulation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 22 ++
linux-user/signal.c | 3 ---
2
Add a function that generates a Virtual I/O Translation table (VIOT),
describing the topology of paravirtual IOMMUs. The table is created when
instantiating a virtio-iommu device. It contains a virtio-iommu node and
PCI Range nodes for endpoints managed by the IOMMU. By default, a single
node
virtio-iommu is now supported with ACPI VIOT as well as device tree.
Remove the restriction that prevents from instantiating a virtio-iommu
device under ACPI.
Reviewed-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt.c| 10 ++
Not sure why the user-only code wasn't rewritten to use
probe_access_flags at the same time that the sysemu code
was converted. For the purpose of user-only, this is an
exact replacement.
Cc: qemu-s3...@nongnu.org
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 18
Allow instantiating a virtio-iommu device on ACPI systems by adding a
Virtual I/O Translation table (VIOT). Enable x86 support for VIOT.
Changes since v3 [1]:
* Cleaned the IOMMU-uniqueness checks. Added patch 6 to have a
single check on x86.
* Added patch 5 that allows to gracefully propagate
The VIOT blob contains the following:
[000h 4]Signature : "VIOT"[Virtual I/O
Translation Table]
[004h 0004 4] Table Length : 0058
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 66
[00Ah 0010
Because of the complexity of setting ESR, continue to use
arm_deliver_fault. This means we cannot remove the code
within cpu_loop that decodes EXCP_DATA_ABORT and
EXCP_PREFETCH_ABORT.
But using the new hook means that we don't have to do the
page_get_flags check manually, and we'll be able to
The fallback code in raise_sigsegv is sufficient for sparc.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland
Signed-off-by: Richard
We do not support instantiating multiple IOMMUs. Before adding a
virtio-iommu, check that no other IOMMU is present. This will detect
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
Reviewed-by:
The fallback code in raise_sigsegv is sufficient for riscv.
Remove the code from cpu_loop that raised SIGSEGV.
Cc: qemu-ri...@nongnu.org
Signed-off-by: Richard Henderson
---
linux-user/riscv/cpu_loop.c | 7 ---
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 21
This is a new interface to be provided by the os emulator for
raising SIGSEGV on fault. Use the new record_sigsegv target hook.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 15 +++
The fallback code in raise_sigsegv is sufficient for sh4.
Remove the code from cpu_loop that raised SIGSEGV.
Cc: Yoshinori Sato
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 6 +++---
linux-user/sh4/cpu_loop.c | 8
target/sh4/cpu.c | 2 +-
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.
Cc: qemu-...@nongnu.org
Reviewed-by:
The fallback code in raise_sigsegv is sufficient for hppa-linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
This makes all of the code in mem_helper.c sysemu only, so remove the
ifdefs and move the file to hppa_softmmu_ss.
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/mips/host-signal.h | 62 +-
accel/tcg/user-exec.c | 52 +
2 files changed, 62
The fallback code in raise_sigsegv is sufficient for openrisc.
This makes all of the code in mmu.c sysemu only, so remove
the ifdefs and move the file to openrisc_softmmu_ss.
Remove the code from cpu_loop that handled EXCP_DPF.
Cc: Stafford Horne
Signed-off-by: Richard Henderson
---
The fallback code in raise_sigsegv is sufficient for cris-linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
This makes all of the code in helper.c sysemu only, so remove the
ifdefs and move the file to cris_softmmu_ss.
Cc: Edgar E. Iglesias
Reviewed-by: Philippe
The named function no longer exists.
Refer to host_signal_handler instead.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index dab5f1d1cd..07be55b7e1 100644
---
On Fri, Oct 01, 2021 at 07:08:51PM +0200, Paolo Bonzini wrote:
> On 29/09/21 04:58, Yanan Wang wrote:
> > @@ -933,8 +935,7 @@ static void machine_set_smp(Object *obj, Visitor *v,
> > const char *name,
> > return;
> > }
> > -smp_parse(ms, config, errp);
> > -if (*errp) {
>
Use the new os interface for raising the exception,
rather than calling arm_cpu_tlb_fill directly.
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/s390/host-signal.h | 93 -
linux-user/host/s390x/host-signal.h | 2 +-
accel/tcg/user-exec.c | 88
The kernel vectors both of these through unhandled_exception, which
results in force_sig(SIGSEGV). This isn't very useful for userland
when enabling overflow traps or fpu traps, but c'est la vie.
Cc: Stafford Horne
Signed-off-by: Richard Henderson
---
linux-user/openrisc/cpu_loop.c | 13
The fallback code in raise_sigsegv is sufficient for xtensa.
Remove the code from cpu_loop that raised SIGSEGV.
Cc: Max Filippov
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.h | 2 +-
linux-user/xtensa/cpu_loop.c | 9 -
target/xtensa/cpu.c | 2 +-
The fallback code in raise_sigsegv is sufficient for mb linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
Cc: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 8
linux-user/microblaze/cpu_loop.c | 10 --
Do not read 4 bytes before we determine the size of the insn.
Simplify triple switches in favor of checking major opcodes.
Include the missing cases of compact fsd and fsdsp.
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 83 ++---
1 file
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Drop the Solais code as completely unused.
Signed-off-by: Richard Henderson
---
linux-user/host/sparc/host-signal.h | 54 ++-
The fallback code in raise_sigsegv is sufficient for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely.
Remove the code from cpu_loop that raised SIGSEGV.
Signed-off-by: Richard Henderson
---
target/mips/tcg/tcg-internal.h| 7 ++--
linux-user/mips/cpu_loop.c|
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/alpha/host-signal.h | 41 +
accel/tcg/user-exec.c | 31 +-
2 files changed, 42
The fallback code in raise_sigsegv is sufficient for m68k-linux-user.
Remove the code from cpu_loop that handled EXCP_ACCESS.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 10 --
target/m68k/cpu.c | 2 +-
target/m68k/helper.c | 6 +-
3 files
Now that all of the linux-user hosts have been converted
to host-signal.h, drop the compatibility code.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 12
linux-user/signal.c | 14 --
2
Record cr2, error_code, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
Use the maperr parameter to properly set PG_ERROR_P_MASK.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 26
Split host_signal_pc and host_signal_write out of user-exec.c.
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 85 +-
accel/tcg/user-exec.c | 134
2 files changed, 84 insertions(+), 135 deletions(-)
diff
Remove the comment about siglongjmp. We do use sigsetjmp
in the main cpu loop, but we do not save the signal mask
as most exits from the cpu loop do not require them.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 14 ++
1 file changed, 2 insertions(+), 12
The fallback code in raise_sigsegv is sufficient for hexagon.
Remove the code from cpu_loop that raises SIGSEGV.
Cc: Taylor Simpson
Signed-off-by: Richard Henderson
---
linux-user/hexagon/cpu_loop.c | 24 +---
target/hexagon/cpu.c | 23 ---
2
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/arm/host-signal.h | 30 -
accel/tcg/user-exec.c | 45 +--
2
The fallback code in raise_sigsegv is sufficient for alpha-linux-user.
Remove the code from cpu_loop that handled EXCP_MMFAULT.
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 7 ---
linux-user/alpha/cpu_loop.c | 8
target/alpha/cpu.c | 2 +-
Split out a function to adjust the raw signal pc into a
value that could be passed to cpu_restore_state.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Adjust pc in place; return MMUAccessType.
---
include/exec/exec-all.h | 10 ++
accel/tcg/user-exec.c |
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-signal.h | 74 -
accel/tcg/user-exec.c | 94
The existing code for safe-syscall.inc.S will compile
without change for riscv32 and riscv64. We may also
drop the meson.build stanza that merges them for tcg/.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
configure
Currently there are only two places that require we reset this
value before exiting to the main loop, but that will change.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 3 ++-
accel/tcg/user-exec.c | 2 --
2 files changed, 2 insertions(+), 3
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/ppc/host-signal.h | 25 -
linux-user/host/ppc64/host-signal.h | 2 +-
Add stub host-signal.h for all linux-user hosts.
Add new code replacing cpu_signal_handler.
Full migration will happen one host at a time.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
This is the major portion of handle_cpu_signal which is specific
to tcg, handling the page protections for the translations.
Most of the rest will migrate to linux-user/ shortly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Pass guest address to
Changes for v3:
* Rebased on master, as force_sig_fault is now upstream.
* Minimized nios2 changes; there's another patch set that cleans
up nios2, but I don't want to force that as a dependency.
* Renamed raise_sigsegv to cpu_loop_exit_segv (f4bug).
Patches lacking review:
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/i386/host-signal.h | 25 -
linux-user/host/x32/host-signal.h| 2 +-
linux-user/host/x86_64/host-signal.h |
On 29/09/21 04:58, Yanan Wang wrote:
@@ -933,8 +935,7 @@ static void machine_set_smp(Object *obj, Visitor *v, const
char *name,
return;
}
-smp_parse(ms, config, errp);
-if (*errp) {
+if (!smp_parse(ms, config, errp)) {
Alex,
We need to update the docker container used for hexagon for new test cases
proposed in Taylor's recent patch series under review. Thankfully, CodeLinaro
has provided a binary of the hexagon cross toolchain so now I think we can
simplify the hexagon docker file to something like the
On 10/1/21 12:35 PM, Stefan Hajnoczi wrote:
QEMU's TCG threads execute translated code. There are events that
require interrupting these threads. Today a check is performed at the
start of every translated block. Most of the time the check is false and
it's a waste of CPU.
User interrupts can
On Thu, Sep 30, 2021 at 10:24:24AM -0700, Sohil Mehta wrote:
>
> On 9/30/2021 9:30 AM, Stefan Hajnoczi wrote:
> > On Tue, Sep 28, 2021 at 09:31:34PM -0700, Andy Lutomirski wrote:
> > >
> > > I spent some time reviewing the docs (ISE) and contemplating how this all
> > > fits together, and I
On 9/30/21 11:08 AM, Peter Maydell wrote:
Our GICv3 QOM interface includes an array property
redist-region-count which allows board models to specify that the
registributor registers are not in a single contiguous range, but
split into multiple pieces. We implemented this for KVM, but
currently
On 9/30/21 11:08 AM, Peter Maydell wrote:
The 'Last' bit in the GICR_TYPER GICv3 redistributor register is
supposed to be set to 1 if this is the last redistributor in a series
of contiguous redistributor pages. Currently we set Last only for
the redistributor for CPU (num_cpu - 1). This only
On 9/30/21 11:08 AM, Peter Maydell wrote:
The GICv3 devices have an array property redist-region-count.
Currently we check this for errors (bad values) in
gicv3_init_irqs_and_mmio(), just before we use it. Move this error
checking to the arm_gicv3_common_realize() function, where we
> -Original Message-
> From: Richard Henderson
> Sent: Friday, October 1, 2021 10:55 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: f4...@amsat.org; a...@rev.ng; Brian Cain
> Subject: Re: [PATCH v2] Hexagon (target/hexagon) probe the stores in a
> packet at start of commit
>
>
On 10/1/21 11:30 AM, nia wrote:
As discussed in issue 614, we're shipping GCC 7.4.0 as the
system compiler in NetBSD 9, the most recent stable branch,
and are still actively interested in QEMU on this platform.
The differences between GCC 7.5.0 and 7.4.0 are trivial.
Signed-off-by: Nia Alarie
On 9/30/21 5:16 PM, Taylor Simpson wrote:
+} else if (has_store_s0 && has_store_s1) {
+TCGv mem_idx = tcg_const_tl(ctx->mem_idx);
+gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx);
+tcg_temp_free(mem_idx);
+}
So we're assuming that the s1 store happens
On Mon, Sep 20, 2021 at 10:39:36AM +0200, Igor Mammedov wrote:
> > +static void test_acpi_q35_viot(void)
> > +{
> > +test_data data = {
> > +.machine = MACHINE_Q35,
> > +.variant = ".viot",
>
> > +.blkdev = "virtio-blk,bus=pcie.0",
> why is this necessary?
It isn't
Build the entire cross tool chain from source.
For this reason, default to caching.
Signed-off-by: Richard Henderson
---
tests/docker/Makefile.include | 19
.../dockerfiles/debian-nios2-cross.docker | 34 +++
.../build-toolchain.sh| 97
On Mon, Sep 20, 2021 at 10:24:40AM +0200, Igor Mammedov wrote:
> > +if (pcms->virtio_iommu && x86_iommu_get_default()) {
> > +error_report("QEMU does not support multiple vIOMMUs for x86
> > yet.");
> > +exit(EXIT_FAILURE);
> > +}
>
> previous patch does similar check,
Do not cast the signal mask elements; trust __put_user.
Signed-off-by: Richard Henderson
---
linux-user/nios2/signal.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c
index 20b65aa06e..80e3d42fc9 100644
---
Signed-off-by: Richard Henderson
---
tests/tcg/configure.sh | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 1f985ccfc0..62ca1e2cae 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -59,6 +59,7 @@ fi
:
The real kernel will talk about the user PC as EA,
because that's where the hardware will have copied it,
and where it expects to put it to then use ERET.
But qemu does not emulate all of the exception stuff
while emulating user-only. Manipulate PC directly.
This fixes signal entry and return,
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