Never mind, found the answers in kvm_set_user_memory :)
On Fri, Oct 15, 2021 at 9:36 PM Ajay Garg wrote:
>
> Hello everyone.
>
> I have a x86_64 L1 guest, running on a x86_64 host, with a
> host-pci-device attached to the guest.
> The host runs with IOMMU enabled, and passthrough enabled.
>
>
From: Mingwang Li
If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as
On 10/15/21 12:45 AM, frank.ch...@sifive.com wrote:
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank
I've seen a lot of failures on this job recently, and they're all timeouts cloning the git
submodules. Would it be better to mirror these to gitlab?
r~
On 10/15/21 12:29 PM, Alexey Baturo wrote:
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 4
1 file changed, 4 insertions(+)
Reviewed-by: Richard Henderson
r~
On 10/15/21 12:29 PM, Alexey Baturo wrote:
+
+/*
+ * CSRs for PointerMasking extension
+ */
+target_ulong mmte;
+target_ulong mpmmask;
+target_ulong mpmbase;
+target_ulong spmmask;
+target_ulong spmbase;
+target_ulong upmmask;
+target_ulong upmbase;
You
On 10/15/21 12:29 PM, Alexey Baturo wrote:
FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
+/* If PointerMasking should be applied */
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
Merge error.
+if (riscv_has_ext(env, RVJ)) {
+int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
On 10/15/21 12:29 PM, Alexey Baturo wrote:
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
Ping.
On 10/7/21 12:54 PM, Richard Henderson wrote:
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
But targets like Alpha, MIPS, and RISC-V do
On 10/15/21 5:42 AM, Gavin Shan wrote:
The empty NUMA node, where no memory resides, are allowed. For
example, the following command line specifies two empty NUMA nodes.
With this, QEMU fails to boot because of the conflicting device-tree
node names, as the following error message indicates.
On 10/15/21 2:09 PM, Eric Blake wrote:
The following changes since commit 253e399bab7c83b3411f8eac01840283a9304cb3:
Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into staging
(2021-10-15 12:08:54 -0700)
are available in the Git repository at:
On Fri, 15 Oct 2021, BALATON Zoltan wrote:
On Fri, 15 Oct 2021, David Gibson wrote:
On Thu, Oct 14, 2021 at 09:50:19PM +0200, BALATON Zoltan wrote:
This is needed for Linux to access RTC time.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 25 +
1 file
在2021年10月15日十月 上午2:06，BALATON Zoltan写道：
> Other functions in the VT82xx chips need to raise ISA interrupts. Keep
> a reference to them in the device state and add via_isa_set_irq() to
> allow setting their state.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Jiaxun Yang
> ---
--
- Jiaxun
在2021年10月15日十月 上午2:06，BALATON Zoltan写道：
> The vt82c686b_realize and vt8231_realize methods are almost identical,
> factor out the common parts to a via_isa_realize function to avoid
> code duplication.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Jiaxun Yang
> ---
> hw/isa/vt82c686.c |
在2021年10月15日十月 上午9:49，Philippe Mathieu-Daudé写道：
> On 10/11/21 15:58, Jiaxun Yang wrote:
>> ping?
>>
>> 在 2021/10/2 19:45, Jiaxun Yang 写道:
>>> Jiaxun Yang (3):
>>> hw/mips/boston: Massage memory map information
>>> hw/mips/boston: Allow loading elf kernel and dtb
>>> hw/mips/boston:
From: Vladimir Sementsov-Ogievskiy
blk_check_bytes_request is called from blk_co_do_preadv,
blk_co_do_pwritev_part, blk_co_do_pdiscard and blk_co_copy_range
before (maybe) calling throttle_group_co_io_limits_intercept() (which
has int64_t argument) and then calling corresponding bdrv_co_
From: Vladimir Sementsov-Ogievskiy
1. Convert bytes in BlkAioEmAIOCB:
aio->bytes is only passed to already int64_t interfaces, and set in
blk_aio_prwv, which is updated here.
2. For all updated functions the parameter type becomes wider so callers
are safe.
3. In blk_aio_prwv we only
From: Vladimir Sementsov-Ogievskiy
Make bytes argument int64_t to be consistent with modern block-layer.
Callers should be OK with it as type becomes wider.
What is inside functions?
- Conversion from int64_t to size_t. Still, we
can't have a buffer larger than SIZE_MAX, therefore bytes should
From: Vladimir Sementsov-Ogievskiy
Let's drop hand-made coroutine wrappers and use coroutine wrapper
generation like in block/io.c.
Now, blk_foo() functions are written in same way as blk_co_foo() ones,
but wrap blk_do_foo() instead of blk_co_do_foo().
Signed-off-by: Vladimir
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 6 ++
target/riscv/helper.h | 1 +
target/riscv/insn32.decode
From: Vladimir Sementsov-Ogievskiy
We already have this marker for the blk_co_flush function declaration in
block/block-backend.c. Add it in the header too.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211007175243.642516-1-vsement...@virtuozzo.com>
Reviewed-by: Eric Blake
From: Vladimir Sementsov-Ogievskiy
Convert blk_pdiscard, blk_pwrite_compressed, blk_pwrite_zeroes.
These are just wrappers for functions with int64_t argument, so allow
passing int64_t as well. Parameter type becomes wider so all callers
should be OK with it.
Note that requests exceeding
From: Hanna Reitz
With -m32, size_t is generally only a uint32_t. That makes clang
complain that in the assertion
assert(qiov->size <= INT64_MAX);
the range of the type of qiov->size (size_t) is too small for any of its
values to ever exceed INT64_MAX.
Cast qiov->size to uint64_t to
From: Vladimir Sementsov-Ogievskiy
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211006131718.214235-7-vsement...@virtuozzo.com>
Reviewed-by: Eric Blake
Signed-off-by: Eric Blake
---
scripts/block-coroutine-wrapper.py | 12 ++--
block/coroutines.h | 3
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Frank Chang
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x,
From: Vladimir Sementsov-Ogievskiy
This is a preparation to the following commit, to use automatic
coroutine wrapper generation.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211006131718.214235-6-vsement...@virtuozzo.com>
Reviewed-by: Eric Blake
Signed-off-by: Eric Blake
---
From: Vladimir Sementsov-Ogievskiy
We convert blk_do_pwritev_part() and some wrappers:
blk_co_pwritev_part(), blk_co_pwritev(), blk_co_pwrite_zeroes().
All functions are converted so that the parameter type becomes wider, so
all callers should be OK with it.
Look at blk_do_pwritev_part() body:
From: Vladimir Sementsov-Ogievskiy
Function is updated so that parameter type becomes wider, so all
callers should be OK with it.
Look at blk_co_copy_range() itself: bytes is passed only to
blk_check_byte_request() and bdrv_co_copy_range(), which already have
int64_t bytes parameter, so we are
From: Vladimir Sementsov-Ogievskiy
To be consistent with declarations in include/sysemu/block-backend.h.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211006131718.214235-12-vsement...@virtuozzo.com>
Reviewed-by: Eric Blake
Signed-off-by: Eric Blake
---
block/block-backend.c |
From: Vladimir Sementsov-Ogievskiy
For both updated functions, the type of bytes becomes wider, so all callers
should be OK with it.
blk_co_preadv() only passes its arguments to blk_do_preadv().
blk_do_preadv() passes bytes to:
- trace_blk_co_preadv, which is updated too
-
From: Vladimir Sementsov-Ogievskiy
We updated blk_do_pdiscard() and its wrapper blk_co_pdiscard(). Both
functions are updated so that the parameter type becomes wider, so all
callers should be OK with it.
Look at blk_do_pdiscard(): bytes is passed only to
blk_check_byte_request() and
The following changes since commit 253e399bab7c83b3411f8eac01840283a9304cb3:
Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into staging
(2021-10-15 12:08:54 -0700)
are available in the Git repository at:
https://repo.or.cz/qemu/ericb.git tags/pull-nbd-2021-10-15
for you
From: Vladimir Sementsov-Ogievskiy
Rename size and make it int64_t to correspond to modern block layer,
which always uses int64_t for offset and bytes (not in blk layer yet,
which is a task for following commits).
All callers pass int or unsigned int.
So, for bytes in [0, INT_MAX] nothing is
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32.decode
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 82 ++
target/riscv/helper.h | 13 +++
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
+#define REQUIRE_ZFH(ctx) do { \
+if (!ctx->ext_zfh)\
+return false; \
+} while (0)
Missing braces for if.
Otherwise,
Reviewed-by: Richard Henderson
r~
This series fixes memory leaks in Xilinx eFUSE devices for
the Versal and ZynqMP product families.
The leaks result from failing to free memory allocated
by object_get_canonical_path().
Tong Ho (3):
hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
hw/nvram: Fix Memory Leak in Xilinx Versal
Signed-off-by: Tong Ho
---
hw/nvram/xlnx-efuse.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index ee1caab54c..a0fd77b586 100644
--- a/hw/nvram/xlnx-efuse.c
+++ b/hw/nvram/xlnx-efuse.c
@@ -144,10 +144,11 @@ static
Signed-off-by: Tong Ho
---
hw/nvram/xlnx-zynqmp-efuse.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
index 1f87dbf988..228ba0bbfa 100644
--- a/hw/nvram/xlnx-zynqmp-efuse.c
+++
Signed-off-by: Tong Ho
---
hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c
b/hw/nvram/xlnx-versal-efuse-ctrl.c
index d362376703..b35ba65ab5 100644
---
On 10/15/21 7:46 AM, Kevin Wolf wrote:
The following changes since commit 4d1a525dfafe995a98bb486e702da09e31b68b9c:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
staging (2021-10-14 10:49:38 -0700)
are available in the Git repository at:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
> commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
> added the support of Intel PT by making CPUID[14] of PT as fixed feature
> set (from ICX) for any CPU model on any host.
>
> This truly breaks the PT exposing on
On 15/10/2021 09:40, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
This allows the programmer's switch to be triggered via the monitor for
debugging
purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to
hold
the NMI active for 100ms before
On 15/10/2021 08:17, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
whether the hardware is configured for A/UX mode.
Stupid question: why do you use GPIO to pass the auxmode information
On 15/10/2021 07:58, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
whether the hardware is configured for A/UX mode.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/mac_via.c | 18
On 10/15/21 11:30 AM, Warner Losh wrote:
+ /*
+ * Fall back to parsing instructions; will only be needed
+ * for really ancient (pre-3.16) kernels.
+ */
+ insn = *(uint32_t *)host_signal_pc(uc);
+
+ return (insn & 0xbfff) == 0x0c00 /*
On 15/10/2021 07:31, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
In order to allow dynamic routing of IRQs to different IRQ levels on the CPU
depending upon port B bit 6, use GLUE IRQ numbers and map them to the the
corresponding CPU IRQ level accordingly.
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
On 15/10/2021 07:14, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to
configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't
particularly descriptive, the patch leaves this
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7f9dde70b7..fb08c0ffb8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -558,6 +558,9 @@ static void riscv_cpu_realize(DeviceState
From: Anatoly Parshintsev
Signed-off-by: Anatoly Parshintsev
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 20 ++
target/riscv/translate.c | 56 +---
2 files changed, 66 insertions(+), 10
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 96 +
1 file changed, 96 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..1a3767804a 100644
---
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 75e8b8ca83..7f9dde70b7 100644
--- a/target/riscv/cpu.c
v13:
Rebased QEMU and addressed Richard's comment.
v12:
Updated function for adjusting address with pointer masking to allocate and use
temp register.
v11:
Addressed a few style issues Alistair mentioned in the previous review.
If this patch series would be accepted, I think my further
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9e55b2f5b1..3f28dc5f3a 100644
--- a/target/riscv/cpu.h
+++
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 11 ++
target/riscv/csr.c | 285 +
3 files changed, 298 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..75e8b8ca83 100644
---
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
> has access to complete alignment info from the TCGMemOpIdx arg.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
>
On 10/15/21 2:16 AM, Thomas Huth wrote:
Hi!
The following changes since commit bfd9a76f9c143d450ab5545dedfa74364b39fc56:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-121021-2'
into staging (2021-10-12 06:16:25 -0700)
are available in the Git repository at:
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Because of the complexity of setting ESR, re-use the existing
> arm_cpu_do_unaligned_access function. This means we have to
> handle the exception ourselves in cpu_loop, transforming it
> to the
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This requires extra work for each target, but adds the
> common syscall code, and the necessary flag in CPUState.
>
> Signed-off-by: Richard Henderson
> ---
> include/hw/core/cpu.h |
On 10/15/21 4:08 AM, Christian Borntraeger wrote:
Am 13.10.21 um 11:07 schrieb Paolo Bonzini:
From: Markus Armbruster
Commit 6287d827d4 "monitor: allow device_del to accept QOM paths"
extended find_device_state() to accept QOM paths in addition to qdev
IDs. This added a checked conversion
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/user-exec.c | 7 ++-
> 1 file changed, 6 insertions(+), 1
This change exposes ACPI ERST support for x86 guests.
Signed-off-by: Eric DeVolder
---
hw/i386/acpi-build.c | 9 +
hw/i386/acpi-microvm.c | 9 +
include/hw/acpi/erst.h | 5 +
3 files changed, 23 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is not used by, nor required by, user-only.
>
> Signed-off-by: Richard Henderson
> ---
> target/ppc/internal.h| 8 +++-
> target/ppc/excp_helper.c | 8 +++-
> 2 files changed, 6
This change implements the test suite checks for the ERST table.
Signed-off-by: Eric DeVolder
---
tests/qtest/bios-tables-test.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> To be called from tcg generated code on hosts that support
> unaligned accesses natively, in response to an access that
> is supposed to be aligned.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
---
tests/qtest/erst-test.c | 167
tests/qtest/meson.build | 2 +
2 files changed, 169
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 241 +
1 file changed, 241 insertions(+)
diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
index
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
---
hw/acpi/Kconfig | 6 +
hw/acpi/erst.c | 836 +++
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
---
Information on the implementation of the ACPI ERST support.
Signed-off-by: Eric DeVolder
Acked-by: Ani Sinha
---
docs/specs/acpi_erst.rst | 200 +++
1 file changed, 200 insertions(+)
create mode 100644 docs/specs/acpi_erst.rst
diff --git
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 6.
Below is the disassembly of an ERST table, tests/data/acpi/pc/ERST.
This is a PCI device and as such its base address can change; it
is possible for the address fields to differ between this and other
ERST tables.
[000h
This change introduces the public defintions for ACPI ERST.
Signed-off-by: Eric DeVolder
---
include/hw/acpi/erst.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/hw/acpi/erst.h
diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h
new file mode
This change reserves the PCI device_id for the new ACPI ERST
device.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
Acked-by: Ani Sinha
---
include/hw/pci/pci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 7fc9013..45b79b1 100644
This patchset introduces support for the ACPI Error Record
Serialization Table, ERST.
For background and implementation information, please see
docs/specs/acpi_erst.rst, which is patch 2/10.
Suggested-by: Konrad Wilk
Signed-off-by: Eric DeVolder
---
v8: 15oct2021
- Added Kconfig option for
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is a new interface to be provided by the os emulator for
> raising SIGBUS on fault. Use the new record_sigbus target hook.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 14
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Add a new user-only interface for updating cpu state before
> raising a signal. This will take the place of do_unaligned_access
> for user-only and should result in less boilerplate for each guest.
>
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for riscv linux-user.
>
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Reviewed-by: Alistair Francis
> Reviewed-by: Philippe
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Record DAR, DSISR, and exception_index. That last means
> that we must exit to cpu_loop ourselves, instead of letting
> exception_index being overwritten.
>
> This is exactly what the user-mode
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Use the new os interface for raising the exception,
> rather than calling arm_cpu_tlb_fill directly.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for mips linux-user.
>
> This means we can remove tcg/user/tlb_helper.c entirely.
> Remove the code from cpu_loop that raised SIGSEGV.
>
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/riscv/host-signal.h | 85 +-
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Because of the complexity of setting ESR, continue to use
> arm_deliver_fault. This means we cannot remove the code
> within cpu_loop that decodes EXCP_DATA_ABORT and
> EXCP_PREFETCH_ABORT.
>
> But using
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson
> ---
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The named function no longer exists.
> Refer to host_signal_handler instead.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/sve_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/mips/host-signal.h | 62
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
> Drop the Solaris code as completely unused.
>
> Signed-off-by: Richard
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
>
On 10/15/21 7:54 AM, Matheus K. Ferst wrote:
While Appendix B does guarantee that "0" is and always will be an invalid
instruction, I
wonder if the test itself would be clearer (i.e. self-documenting the intent)
using
SIGTRAP and "trap".
r~
It would be better, but cpu_loop is currently
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson
> ---
>
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The existing code for safe-syscall.inc.S will compile
> without change for riscv32 and riscv64. We may also
> drop the meson.build stanza that merges them for tcg/.
>
> Reviewed-by: Philippe Mathieu-Daudé
On Thu, Oct 14, 2021 at 2:00 PM Eugenio Perez Martin
wrote:
>
> On Wed, Oct 13, 2021 at 5:27 AM Jason Wang wrote:
> >
> >
> > 在 2021/10/1 下午3:05, Eugenio Pérez 写道:
> > > Shadow virtqueue notifications forwarding is disabled when vhost_dev
> > > stops, so code flow follows usual cleanup.
> > >
>
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Remove the comment about siglongjmp. We do use sigsetjmp
> in the main cpu loop, but we do not save the signal mask
> as most exits from the cpu loop do not require them.
>
> Signed-off-by: Richard
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is the major portion of handle_cpu_signal which is specific
> to tcg, handling the page protections for the translations.
> Most of the rest will migrate to linux-user/ shortly.
>
> Reviewed-by:
From: Matheus Ferst
PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or
MSR[LE]", but the current code only filters the GPR-provided value if
L=1. This behavior caused some problems in FreeBSD, and a build option
was added to work around the issue [1], but it seems that the
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split out a function to adjust the raw signal pc into a
> value that could be passed to cpu_restore_state.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> v2: Adjust pc
Hi all,
On Thu, 14 Oct 2021 at 09:28, Tom Rini wrote:
>
> On Thu, Oct 14, 2021 at 09:17:52AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, 14 Oct 2021 at 08:56, Tom Rini wrote:
> > >
> > > On Wed, Oct 13, 2021 at 12:06:02PM -0600, Simon Glass wrote:
> > > > Hi François,
> > > >
> > > >
On Fri, Oct 15, 2021 at 06:24:14PM +0200, Lukasz Maniak wrote:
> On Wed, Oct 13, 2021 at 05:10:35AM -0400, Michael S. Tsirkin wrote:
> > On Tue, Oct 12, 2021 at 06:06:46PM +0200, Lukasz Maniak wrote:
> > > On Tue, Oct 12, 2021 at 03:25:12AM -0400, Michael S. Tsirkin wrote:
> > > > On Thu, Oct 07,
On 10/14/21 11:54 PM, frank.ch...@sifive.com wrote:
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 inhttps://github.com/riscv/riscv-isa-manual
Signed-off-by: Chih-Min Chao
---
target/riscv/fpu_helper.c | 8
1 file changed, 4 insertions(+), 4
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