Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On Sun, Oct 17, 2021 at 8:55 AM Frank Chang wrote: > On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 10/16/21 1:52 AM, Frank Chang wrote: >> > On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson < >> richard.hender...@linaro.org >> >

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 10/16/21 1:52 AM, Frank Chang wrote: > > On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson < > richard.hender...@linaro.org > > > wrote: > > > > On 10/14/21 11:54

Re: [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1

On Sun, Oct 17, 2021 at 2:03 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 10/16/21 2:07 AM, frank.ch...@sifive.com wrote: > > Changelog: > > > > v3: > >* Use the renamed softfloat min/max APIs: *_minimum_number() > > and *_maximum_number(). > >* Pick softfloat min/

Re: [PULL 00/24] tcg patch queue

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016 for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a: Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700) Mo

[PATCH] tests/vm: update openbsd to release 7.0

tests/vm: update openbsd to release 7.0 Signed-off-by: Brad Smith --- tests/vm/openbsd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/vm/openbsd b/tests/vm/openbsd index c4c78a80f1..abf510e117 100755 --- a/tests/vm/openbsd +++ b/tests/vm/openbsd @@ -22,8 +22,8 @@ c

Re: [PATCH] tests/vm/openbsd: Move timezone set to after disk setup

Yes, this is the correct order. The timezone question comes after the install sets are extracted. Signed-off-by: Brad Smith On 10/13/2021 12:31 PM, Richard Henderson wrote: Currently the install gets stuck waiting for the timezone when the installer is waiting on the disk. Swap the two. Sig

[PULL 22/24] target/tricore: Drop check for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/tricore/helper.h| 1 - target/tricore/op_helper.c | 7 --- target/tricore/translate.c | 14 +- 3 files changed, 1 insertion(+), 21 deletions(-)

[PULL 21/24] target/sh4: Drop check for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/helper.h| 1 - target/sh4/op_helper.c | 5 - target/sh4/translate.c | 14 +++--- 3 files changed, 3 insertions(+), 17 deletions(-) diff --git a/

[PULL 23/24] target/xtensa: Drop check for singlestep_enabled

GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 25 - 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index dcf6b500ef..09430c1bf9 100644

[PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"

This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. Despite a comment saying why cpu_common_props cannot be placed in a file that is compiled once, it was moved anyway. Revert that. Since then, Property is not defined in hw/core/cpu.h, so it is now easier to declare a function to insta

[PULL 17/24] target/riscv: Remove dead code after exception

We have already set DISAS_NORETURN in generate_exception, which makes the exit_tb unreachable. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_privileged.c.inc | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/riscv/

[PULL 20/24] target/s390x: Drop check for singlestep_enabled

GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a2d6fa5cca..dcc249a197 100644 --- a/targ

[PULL 16/24] target/ppc: Drop exit checks for singlestep_enabled

GDB single-stepping is now handled generically. Reuse gen_debug_exception to handle architectural debug exceptions. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 38 -- 1 file changed, 8 insertions(+), 30 deletions(-) diff --git a/target/ppc/t

[PULL 15/24] target/openrisc: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c

[PULL 19/24] target/rx: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/rx/helper.h| 1 - target/rx/op_helper.c | 8 target/rx/translate.c | 12 ++-- 3 files changed, 2 insertions(+), 19 deletions(-) diff --git a/ta

[PULL 14/24] target/mips: Drop exit checks for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/translate.c | 50 + 1 file changed, 18 insertions(+), 32 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/m

[PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr

GDB single-stepping is now handled generically, which means we don't need to do anything in the wrappers. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 27 +-- .../riscv/insn_trans/trans_privileged.c.inc | 4

[PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt

We were using singlestep_enabled as a proxy for whether translator_use_goto_tb would always return false. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/transl

[PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP

We were using singlestep_enabled as a proxy for whether translator_use_goto_tb would always return false. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/t

[PULL 09/24] target/i386: Drop check for singlestep_enabled

GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson --- target/i386/helper.h | 1 - target/i386/tcg/misc_helper.c | 8 target/i386/tcg/translate.c | 4 +--- 3 files changed, 1 insertion(+), 12 deletions(-) diff --git a/target/i386/helper.h b/targ

[PULL 07/24] target/hppa: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 17 - 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c3698cf

[PULL 13/24] target/mips: Fix single stepping

As per an ancient comment in mips_tr_translate_insn about the expectations of gdb, when restarting the insn in a delay slot we also re-execute the branch. Which means that we are expected to execute two insns in this case. This has been broken since 8b86d6d2580, where we forced max_insns to 1 whi

[PULL 10/24] target/m68k: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Acked-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 44 + 1 file changed, 9 insertions(+), 35 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c

[PULL 06/24] target/arm: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 10 ++ target/arm/translate.c | 36 ++-- 2 files changed, 8 insertions(+), 38 deletions(-) diff --git a/target/arm/translate-a64.c b/targ

[PULL 02/24] target/alpha: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 0eee3a1b

[PULL 03/24] target/avr: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Tested-by: Michael Rolnik Reviewed-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/translate.c | 19 --- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target

[PULL 12/24] target/microblaze: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7e465b629a..437bbed6d6 100644

[PULL 00/24] tcg patch queue

The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tc

[PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec

Currently the change in cpu_tb_exec is masked by the debug exception being raised by the translators. But this allows us to remove that code. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/accel/tcg/cpu-exec.c b/accel/t

[PULL 05/24] target/hexagon: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/translate.c | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4f0

[PULL 04/24] target/cris: Drop checks for singlestep_enabled

GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson --- target/cris/translate.c | 16 1 file changed, 16 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index a84b753349..59325b388a 100644 --- a/target/cris/translate.c ++

Re: [PATCH 7/8] q800: wire up remaining IRQs in classic mode

Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : > Explicitly wire up the remaining IRQs in classic mode to enable the use of > g_assert_not_reached() in the default case to detect any unexpected IRQs. > > Add a comment explaining the IRQ routing differences in A/UX mode based > upon the comments

Re: [PATCH 6/8] q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode

Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : > When the hardware is operating in classic mode the SONIC on-board Ethernet > IRQ is > routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not > affect the framebuffer which although it exists in slot 9, has its own > dedica

Re: [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1

On 10/16/21 2:07 AM, frank.ch...@sifive.com wrote: Changelog: v3: * Use the renamed softfloat min/max APIs: *_minimum_number() and *_maximum_number(). * Pick softfloat min/max APIs based on CPU privilege spec version. So... Given that Zfh 0.1 post-dates F 2.2, does that mean that Zf

Re: [PATCH 5/8] q800: wire up auxmode GPIO to GLUE

Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : > This enables the GLUE logic to change its CPU level IRQ routing depending upon > whether the hardware has been configured for A/UX mode. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/q800.c | 14 ++ > 1 file changed, 14 insert

Re: [PATCH v4 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

On 10/16/21 1:54 AM, frank.ch...@sifive.com wrote: From: Chih-Min Chao For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On 10/16/21 1:52 AM, Frank Chang wrote: On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson > wrote: On 10/14/21 11:54 PM, frank.ch...@sifive.com wrote: > From: Chih-Min Chaomailto:chihmin.c...@sifive.com>> >

[PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand

The position of this read-only field is dependent on the current cpu width. Rather than having to compute that difference in many places, compute it only on read. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c| 37 ++--

[PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB

The count zeros instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/translate.c| 16 target/riscv/insn_trans/trans_rvb.c.inc | 33 - 2

[PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI

Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/translate.c| 31 + target/riscv/insn_trans/trans_rvb.c.inc | 92 ++--- target/ris

[PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64

When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Acked-by: Alistair Francis Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++- 1 file changed, 6 i

[PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM

The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/translate.c| 16 +++ target/riscv/insn_trans/trans_rvm.c.inc | 26 +++

[PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol

In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c

[PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64

Use the same REQUIRE_64BIT check that we use elsewhere, rather than open-coding the use of is_32bit. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen

In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 33 ++--- 1 file changed, 18 insertions(+), 15 deletions(-) diff -

[PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext

The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 15 +++ linux-use

[PATCH v3 07/14] target/riscv: Properly check SEW in amo_op

We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 26 +

[PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: Alista

[PATCH v3 01/14] target/riscv: Move cpu_get_tb_cpu_state out of line

Move the function to cpu_helper.c, as it is large and growing. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h| 47 ++- target/riscv/cpu_helper.c | 46 +

[PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS

Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h| 2 ++ target/riscv/cpu.c| 8 target/riscv

[PATCH v3 02/14] target/riscv: Create RISCVMXL enumeration

Move the MXL_RV* defines to enumerators. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu_bits.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187

[PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length

This is a partial patch set attempting to set things in the right direction for both the UXL and RV128 patch sets. Notable addition for v3 is the treatment of [MS]STATUS.SD. Because this bit changes position depending on XLEN, it's better to split it out. But since it's read-only and computable f

Re: [PATCH 8/8] q800: add NMI handler

Le 15/10/2021 à 22:12, Mark Cave-Ayland a écrit : > On 15/10/2021 09:40, Laurent Vivier wrote: > >> Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : >>> This allows the programmer's switch to be triggered via the monitor for >>> debugging >>> purposes. Since the CPU level 7 interrupt is level-tr

Re: [PATCH 4/8] mac_via: add GPIO for A/UX mode

Le 15/10/2021 à 21:59, Mark Cave-Ayland a écrit : > On 15/10/2021 08:17, Laurent Vivier wrote: > >> Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : >>> Add a new auxmode GPIO that is updated when port B bit 6 is changed >>> indicating >>> whether the hardware is configured for A/UX mode. >> >>

Re: [PATCH 4/8] mac_via: add GPIO for A/UX mode

Le 15/10/2021 à 21:50, Mark Cave-Ayland a écrit : > On 15/10/2021 07:58, Laurent Vivier wrote: > >> Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : >>> Add a new auxmode GPIO that is updated when port B bit 6 is changed >>> indicating >>> whether the hardware is configured for A/UX mode. >>> >>

[PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension

From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h,

[PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 21 + target/riscv/helper.h | 3 ++ target/riscv/insn32.decode|

[PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 6 ++ target/riscv/helper.h | 1 + target/riscv/insn32.decode| 1 + tar

[PATCH v3 3/6] target/riscv: zfh: half-precision convert and move

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 67 + target/riscv/helper.h | 12 + target/riscv/insn32.decode| 19 ++

[PATCH v3 2/6] target/riscv: zfh: half-precision computational

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 86 +++ target/riscv/helper.h | 13 +++ target/riscv/insn32.decode

[PATCH v3 1/6] target/riscv: zfh: half-precision load and store

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 1 + target/riscv/insn32.decode| 4 ++ target/

[PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1

From: Frank Chang Zfh - Half width floating point Zfhmin - Subset of half width floating point Zfh, Zfhmin v0.1 is now in public review period and is required by RVV extension: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ Zfh, Zfhmin can be enabled with -c

[PATCH v4 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

From: Chih-Min Chao For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == Na

[PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax

From: Chih-Min Chao The sNaN propagation behavior has been changed since cd20cee7 in https://github.com/riscv/riscv-isa-manual. Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff -

[PATCH v4 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin

From: Frank Chang In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag are removed and replaced with minimum, minimumNumber, maximum and maximumNumber. minimumNumber/maximumNumber behavior for SNaN is changed to: * If both operands are NaNs, a QNaN is returned. * If either operand is a

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 10/14/21 11:54 PM, frank.ch...@sifive.com wrote: > > From: Chih-Min Chao > > > > The sNaN propagation behavior has been changed since > > cd20cee7 inhttps://github.com/riscv/riscv-isa-manual > > > > Signe

Re: [PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

On Sat, Oct 16, 2021 at 1:00 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 10/14/21 11:54 PM, frank.ch...@sifive.com wrote: > > +/* > > + * In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag > > + * are removed and replaced with minimum, minimumNum

Re: gitlab build-edk2 failures

On 16/10/21 04:04, Richard Henderson wrote: I've seen a lot of failures on this job recently, and they're all timeouts cloning the git submodules.  Would it be better to mirror these to gitlab? They're not timeouts, they're issues with edk2's _own_ submodules. fatal: unable to access 'http