Re: [PATCH] net: vmxnet3: validate configuration values during activate (CVE-2021-20203)

On 30/01/2021 14.16, P J P wrote: From: Prasad J Pandit While activating device in vmxnet3_acticate_device(), it does not validate guest supplied configuration values against predefined minimum - maximum limits. This may lead to integer overflow or OOB access issues. Add checks to avoid it. Fi

Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid

On Mon, 18 Oct 2021 10:17:45 +0800 Bin Meng wrote: > Hi Igor, > > On Fri, Oct 15, 2021 at 8:59 PM Igor Mammedov wrote: > > > > On Fri, 15 Oct 2021 17:25:01 +0800 > > Bin Meng wrote: > > > > > On Fri, Oct 15, 2021 at 4:52 PM limingwang (A) > > > wrote: > > > > > > > > > > > > On Wed, Oct

Re: [PATCH] tests/vm: update openbsd to release 7.0

On 10/18/2021 2:28 AM, Thomas Huth wrote: On 17/10/2021 00.56, Brad Smith wrote: tests/vm: update openbsd to release 7.0 Signed-off-by: Brad Smith ---   tests/vm/openbsd | 4 ++--   1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/vm/openbsd b/tests/vm/openbsd index c4c78a80f

Re: [PATCH] tests/vm: update openbsd to release 7.0

On 17/10/2021 00.56, Brad Smith wrote: tests/vm: update openbsd to release 7.0 Signed-off-by: Brad Smith --- tests/vm/openbsd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/vm/openbsd b/tests/vm/openbsd index c4c78a80f1..abf510e117 100755 --- a/tests/vm/openbsd

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

Hi, > > I can do that but waiting for a decision on how to proceed. Will Gerd > > take my first series this is based on as is then this should be a > > separate series doing the clean up using pci_get_function_0 or should > > these two series be merged? I'd also squash setting user_creatable = >

Re: [PATCH v8 00/78] support vector extension v1.0

On Mon, Oct 18, 2021 at 2:12 PM Alistair Francis wrote: > On Mon, Oct 18, 2021 at 4:09 PM Frank Chang > wrote: > > > > On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis > wrote: > >> > >> On Fri, Oct 15, 2021 at 5:48 PM wrote: > >> > > >> > From: Frank Chang > >> > > >> > This patchset impleme

Re: [PATCH v8 00/78] support vector extension v1.0

On Mon, Oct 18, 2021 at 4:09 PM Frank Chang wrote: > > On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis wrote: >> >> On Fri, Oct 15, 2021 at 5:48 PM wrote: >> > >> > From: Frank Chang >> > >> > This patchset implements the vector extension v1.0 for RISC-V on QEMU. >> > >> > RVV v1.0 spec is now

Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move

On Sat, Oct 16, 2021 at 7:09 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 67 + > targ

Re: [PATCH v8 00/78] support vector extension v1.0

On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis wrote: > On Fri, Oct 15, 2021 at 5:48 PM wrote: > > > > From: Frank Chang > > > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > > > RVV v1.0 spec is now fronzen for public review: > > https://github.com/riscv/riscv-v-

Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand

On 10/17/21 10:38 PM, Alistair Francis wrote: Do we get much of an advantage from this though? To me it seems confusing that the mstatus register doesn't actually contain the latest value (for example when debugging QEMU and adding my own printf's). (1) We have at least 3 places that need to ch

Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

On Fri, Oct 15, 2021 at 5:50 PM wrote: > > From: Frank Chang > > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in > commit: c445593, but other TB_FLAGS bits for rvv and rvh were > not shift as well so these bits may overlap with each other when > rvv is enabled. > > Signed-off-by: Fran

Re: [PATCH v8 00/78] support vector extension v1.0

On Fri, Oct 15, 2021 at 5:48 PM wrote: > > From: Frank Chang > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > RVV v1.0 spec is now fronzen for public review: > https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 > > The port is available here: > https://github.co

Re: [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction

On Fri, Oct 15, 2021 at 6:08 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/insn3

Re: [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions

On Fri, Oct 15, 2021 at 6:06 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 6 +++--- > target/riscv/insn_trans/trans_rvv.c.inc | 5 - > target/risc

Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move

On 10/17/21 4:59 PM, Alistair Francis wrote: +#if defined(TARGET_RISCV64) +/* 16 bits -> 64 bits */ +tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]); +#else +/* 16 bits -> 32 bits */ +tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); +tcg_gen_ext16s_tl(dest, dest); +#endif Can we use is

Re: [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction

On Fri, Oct 15, 2021 at 6:25 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 10 -- > 2 files

Re: [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction

On Fri, Oct 15, 2021 at 6:03 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 2 +- > target/riscv/insn32.decode | 2 +- > target/riscv/insn_

Re: [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction

On Fri, Oct 15, 2021 at 6:22 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 2 +- > target/riscv/insn32.decode | 2 +- > target/riscv/insn_

Re: [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions

On Fri, Oct 15, 2021 at 6:04 PM wrote: > > From: Frank Chang > > Vector AMOs are removed from standard vector extensions. Will be added > later as separate Zvamo extension, but will need a different encoding > from earlier proposal. > > Signed-off-by: Frank Chang Reviewed-by: Alistair Francis

Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand

On Mon, Oct 18, 2021 at 3:31 PM Richard Henderson wrote: > > On 10/17/21 9:52 PM, Alistair Francis wrote: > > On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson > > wrote: > >> > >> The position of this read-only field is dependent on the > >> current cpu width. Rather than having to compute that

Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

On 10/17/21 3:55 PM, Alistair Francis wrote: On Fri, Oct 15, 2021 at 5:50 PM wrote: From: Frank Chang TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in commit: c445593, but other TB_FLAGS bits for rvv and rvh were not shift as well so these bits may overlap with each other when rvv

Re: [RFC PATCH 3/5] target/i386: Enable host pass through of Intel PT

On 10/18/2021 11:46 AM, Xiaoyao Li wrote: On 10/16/2021 4:22 AM, Eduardo Habkost wrote: On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote: commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") added the support of Intel PT by making CPUID[14] of PT as fixed feature se

Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand

On 10/17/21 9:52 PM, Alistair Francis wrote: On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson wrote: The position of this read-only field is dependent on the current cpu width. Rather than having to compute that difference in many places, compute it only on read. Signed-off-by: Richard Hend

Re: [PATCH v2 01/15] meson: *-user: only descend into *-user when configured

On Mon, Oct 18, 2021 at 12:02 AM Warner Losh wrote: > > > > On Sun, Oct 17, 2021 at 10:29 PM Warner Losh wrote: >> >> >> >> On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote: >>> >>> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: >>> > >>> > To increase flexibility, only descend into *-user w

Re: gitlab build-edk2 failures

On Sun, Oct 17, 2021 at 04:58:37PM +0200, Philippe Mathieu-Daudé wrote: > On 10/16/21 09:27, Paolo Bonzini wrote: > > On 16/10/21 04:04, Richard Henderson wrote: > >> I've seen a lot of failures on this job recently, and they're all > >> timeouts cloning the git submodules.  Would it be better to m

Re: [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM

On Sun, Oct 17, 2021 at 3:27 AM Richard Henderson wrote: > > The multiply high-part instructions require a separate > implementation for RV32 when TARGET_LONG_BITS == 64. > > Reviewed-by: LIU Zhiwei > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/ris

Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store

On Mon, Oct 18, 2021 at 12:15 PM Frank Chang wrote: > > On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis wrote: >> >> On Sat, Oct 16, 2021 at 7:08 PM wrote: >> > >> > From: Kito Cheng >> > >> > Signed-off-by: Kito Cheng >> > Signed-off-by: Chih-Min Chao >> > Signed-off-by: Frank Chang >> > R

Re: [PATCH v2 01/15] meson: *-user: only descend into *-user when configured

On Sun, Oct 17, 2021 at 10:29 PM Warner Losh wrote: > > > On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote: > >> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: >> > >> > To increase flexibility, only descend into *-user when that is >> > configured. This allows *-user to selectively include

Re: [PATCH v2 15/15] bsd-user/signal: Create a dummy signal queueing function

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Create dummy signal queueing function so we can start to integrate other > architectures (at the cost of signals remaining broken) to tame the > dependency graph a bit and to bring in signals in a more controlled > fashion. Log unimplemented ev

Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand

On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson wrote: > > The position of this read-only field is dependent on the > current cpu width. Rather than having to compute that > difference in many places, compute it only on read. > > Signed-off-by: Richard Henderson This means that the value repo

[PATCH v1 2/2] target/riscv: Organise the CPU properties

From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..837bea3272 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -

Re: [PATCH v2 01/15] meson: *-user: only descend into *-user when configured

On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote: > On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > > > To increase flexibility, only descend into *-user when that is > > configured. This allows *-user to selectively include directories based > > on the host OS which may not exist on all h

Re: [PATCH v3 7/9] bsd-user/mmap.c: Don't mmap fd == -1 independently from MAP_ANON flag

On Fri, Oct 8, 2021 at 4:29 PM Warner Losh wrote: > > From: Guy Yur > > Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd != -1. > MAP_STACK and MAP_GUARD both require fd == -1 and don't require mapping > the fd either. Add analysis from Guy Yur detailing the different cases > for MAP

Re: [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI

On Sun, Oct 17, 2021 at 3:28 AM Richard Henderson wrote: > > Most shift instructions require a separate implementation > for RV32 when TARGET_LONG_BITS == 64. > > Reviewed-by: LIU Zhiwei > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On Mon, Oct 18, 2021 at 8:18 AM Alistair Francis wrote: > On Sun, Oct 17, 2021 at 4:59 PM Frank Chang > wrote: > > > > On Sun, Oct 17, 2021 at 8:55 AM Frank Chang > wrote: > >> > >> On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson < > richard.hender...@linaro.org> wrote: > >>> > >>> On 10/16/2

Re: [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB

On Sun, Oct 17, 2021 at 3:29 AM Richard Henderson wrote: > > The count zeros instructions require a separate implementation > for RV32 when TARGET_LONG_BITS == 64. > > Reviewed-by: LIU Zhiwei > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/tran

Re: [RFC PATCH 3/5] target/i386: Enable host pass through of Intel PT

On 10/16/2021 4:22 AM, Eduardo Habkost wrote: On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote: commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") added the support of Intel PT by making CPUID[14] of PT as fixed feature set (from ICX) for any CPU model on any host.

[PATCH v1 1/2] target/riscv: Remove some unused macros

From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 8 1 file changed, 8 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..3aa2512d13 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -427

Re: [PATCH v2 01/15] meson: *-user: only descend into *-user when configured

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > To increase flexibility, only descend into *-user when that is > configured. This allows *-user to selectively include directories based > on the host OS which may not exist on all hosts. Adopt Paolo's > suggestion of checking the configuration

Re: [PATCH v3 6/9] bsd-user/mmap.c: Convert to qemu_log logging for mmap debugging

On Fri, Oct 8, 2021 at 4:25 PM Warner Losh wrote: > > Convert DEBUG_MMAP to qemu_log CPU_LOG_PAGE. > > Signed-off-by: Warner Losh > --- > bsd-user/mmap.c | 53 + > 1 file changed, 23 insertions(+), 30 deletions(-) > > diff --git a/bsd-user/mmap.c b

Re: [PATCH v2 13/15] bsd-user/sysarch: Provide a per-arch framework for sysarch syscall

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Add the missing glue to pull in do_freebsd_sysarch to call > do_freebsd_arch_sysarch. Put it in os-sys.c, which will be used for > sysctl and sysarch system calls because they are mostly arch specific. > > Signed-off-by: Stacey Son > Signed-of

Re: [PATCH v2 10/15] bsd-user: Remove used from TaskState

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > The 'used' field in TaskState is write only. Remove it from TaskState. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/main.c | 1 - > bsd-user/qemu.h | 1 - > 2 files c

Re: [PATCH v2 11/15] bsd-user: Add stop_all_tasks

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Similar to the same function in linux-user: this stops all the current tasks. > > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/main.c | 9 + > bsd-user/qemu.h | 1 + > 2 files changed, 10 insertions(+) > >

Re: [PATCH v2 14/15] bsd-user: Rename sigqueue to qemu_sigqueue

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > To avoid a name clash with FreeBSD's sigqueue data structure in > signalvar.h, rename sigqueue to qemu_sigqueue. This sturcture s/sturcture/structure/ > is currently defined, but unused. > > Signed-off-by: Warner Losh > Reviewed-by: Richard

Re: [PATCH v2 09/15] bsd-user/target_os_elf: If ELF_HWCAP2 is defined, publish it

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Some architectures publish AT_HWCAP2 as well as AT_HWCAP. Those > architectures will define ELF_HWCAP2 in their target_arch_elf.h files > for the value for this process. If it is defined, then publish it. > > Signed-off-by: Warner Losh > Revie

Re: [PATCH v2 12/15] bsd-user/sysarch: Move to using do_freebsd_arch_sysarch interface

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > do_freebsd_arch_sysarch() exists in $ARCH/target_arch_sysarch.h for x86. > Call it from do_freebsd_sysarch() and remove the mostly duplicate > version in syscall.c. Future changes will move it to os-sys.c and > support other architectures. > >

Re: [PATCH v2 06/15] bsd-user/errno_defs.h: Add internal error numbers

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > From: Stacey Son > > To emulate signals and interrupted system calls, we need to have the > same mechanisms we have in the kernel, including these errno values. > > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > Reviewed-by: Richar

Re: [PATCH v2 08/15] bsd-user/target_os_elf.h: Remove fallback ELF_HWCAP and reorder

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > All architectures have a ELF_HWCAP, so remove the fallback ifdef. > Place ELF_HWCAP in the same order as on native FreeBSD. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-us

Re: [PATCH v2 07/15] bsd-user: move TARGET_MC_GET_CLEAR_RET to target_os_signal.h

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's > architecture agnostic on FreeBSD. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/freebsd/target_

Re: [PATCH v2 05/15] bsd-user: export get_errno and is_error from syscall.c

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Make get_errno and is_error global so files other than syscall.c can use > them. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/qemu.h| 4 > bsd-user/syscall.

Re: [PATCH v2 04/15] bsd-user: TARGET_RESET define is unused, remove it

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/i386/target_arch_cpu.h | 2 -- > bsd-user/x86_64/target_arch_cpu.h | 2 -- > 2 files changed, 4 deletions(-) > > diff --git

Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction

On Sun, Oct 17, 2021 at 10:01:18PM -0300, Daniel Henrique Barboza wrote: > This new version presents drastic design changes across all areas, most > of them based on the feedback received in v3. > > - TCG reviewers: for people looking to review only TCG related changes, > here's a summmary of wher

Re: [PATCH] target/ppc: Filter mtmsr[d] input before setting MSR

On Fri, Oct 15, 2021 at 03:19:40PM -0300, matheus.fe...@eldorado.org.br wrote: > From: Matheus Ferst > > PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or > MSR[LE]", but the current code only filters the GPR-provided value if > L=1. This behavior caused some problems in Fr

[PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 55 +-- 1 file changed, 11 insertions(+), 44 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 49e566a76f..d73503cea4 100644 --- a/hw/intc/sifi

[PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 82 +-- 1 file changed, 33 insertions(+), 49 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 5444368ad4..49e566a76f 100644 --- a/hw/intc/sifi

[PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 109 +- 1 file changed, 22 insertions(+), 87 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index d73503cea4..3f56223554 100644 --- a/hw/intc/sifi

[PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 45 +++ 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index f0e2799efc..d77a5ced23 100644 --- a/hw/intc/sifi

[PATCH v1 3/9] hw/intc: sifive_plic: Move the properties

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 9ba36dc0b3..f0e2799efc 100644 --- a/hw/intc/sifive_plic.c +++

[PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 877e76877c..5444368ad4 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -355,6

[PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index d77a5ced23..877e76877c 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic

[PATCH v1 2/9] hw/intc: Remove the Ibex PLIC

From: Alistair Francis The Ibex PLIC is now spec complient. Let's remove the Ibex PLIC and instead use the SiFive PLIC. Signed-off-by: Alistair Francis --- hw/intc/ibex_plic.c | 307 hw/intc/meson.build | 1 - 2 files changed, 308 deletions(-) de

[PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build

From: Alistair Francis Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 6 +++--- hw/riscv/opentitan.c | 22 +- 2 files changed, 20 insertions(+), 8 deletions(-) diff -

Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid

Hi Igor, On Fri, Oct 15, 2021 at 8:59 PM Igor Mammedov wrote: > > On Fri, 15 Oct 2021 17:25:01 +0800 > Bin Meng wrote: > > > On Fri, Oct 15, 2021 at 4:52 PM limingwang (A) > > wrote: > > > > > > > > > On Wed, Oct 13, 2021 at 22:41 PM Bin Meng wrote: > > > > > > > > On Tue, Oct 12, 2021 at 9:4

Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store

On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis wrote: > On Sat, Oct 16, 2021 at 7:08 PM wrote: > > > > From: Kito Cheng > > > > Signed-off-by: Kito Cheng > > Signed-off-by: Chih-Min Chao > > Signed-off-by: Frank Chang > > Reviewed-by: Richard Henderson > > --- > > target/riscv/cpu.c

[PATCH] via-ide: Avoid expensive operations in irq handler

Cache the pointer to PCI function 0 (ISA bridge, that this IDE device has to use for IRQs) in the PCIIDEState and pass that as the opaque data for the interrupt handler to eliminate both the need to look up function 0 at every interrupt and also a QOM type cast of the opaque pointer as that's also

[PATCH v4 15/15] target/ppc/excp_helper.c: EBB handling adjustments

The current logic is only considering event-based exceptions triggered by the performance monitor. This is true now, but we might want to add support for external event-based exceptions in the future. Let's make it a bit easier to do so by adding the bit logic that would happen in case we were dea

Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

On Mon, Oct 18, 2021 at 6:30 AM Jose Martins wrote: > > Hello Zhiwei and Alistair, > > I noticed this patch did not make it upstream, contrarily to a couple > other patches I submitted around the same time. Is there something > else needed from my side to push this forward? >From your last respon

[PATCH v4 14/15] target/ppc: PMU Event-Based exception support

From: Gustavo Romero Following up the rfebb implementation, this patch adds the EBB exception support that are triggered by Performance Monitor alerts. This exception occurs when an enabled PMU condition or event happens and both MMCR0_EBE and BESCR_PME are set. The supported PM alerts will cons

[PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction

An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The followin

[PATCH v4 11/15] target/ppc: PMU: handle setting of PMCs while running

The initial PMU support were made under the assumption that the counters would be set before running the PMU and read after either freezing the PMU manually or via a performance monitor alert. Turns out that some EBB powerpc kernel tests set the counters after unfreezing the counters. Setting a PM

[PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running

Up until this moment we were assuming that the counter negative enabled bits, PMC1CE and PMCjCE, would never be changed when the PMU is already started. Turns out that there is no such restriction in the PowerISA v3.1, and software can enable/disable overflow conditions of the counters at any time

[PATCH v4 10/15] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event

PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR

[PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events

The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x8000) a performance monitor alert will occur. This alert can trigger

[PATCH v4 09/15] target/ppc: enable PMU instruction count

The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in

[PATCH v4 05/15] target/ppc: introduce PMU events

This patch starts an IBM Power8+ compatible PMU implementation by adding the representation of PMU events that we are going to sample, PMUEvent. This struct represents a Perf event, determined by the PMUEventType enum, that is being sampled by a specific counter 'sprn'. PMUEvent also contains an ov

[PATCH v4 07/15] target/ppc: PMU basic cycle count for pseries TCG

This patch adds the barebones of the PMU logic by enabling cycle counting. The overall logic goes as follows: - a helper is added to control the PMU state on each MMCR0 write. This allows for the PMU to start/stop as the frozen counter bit (MMCR0_FC) is cleared or set; - MMCR0 reg initial value i

[PATCH v4 06/15] target/ppc: initialize PMUEvents on MMCR1 write

The value of MMCR1 determines the events that are going to be sampled by the programmable counters (PMCs 1-4). PMCs 5 and 6 are always counting instructions and cycles respectively and aren't affected by MMCR1. This patch adds a helper to initialize PMCs 1-4 PMUEvents when writing the MMCR1 regist

[PATCH v4 02/15] target/ppc: add user read/write functions for MMCR0

From: Gustavo Romero Userspace need access to PMU SPRs to be able to operate the PMU. One of such SPRs is MMCR0. MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU register. This class of registers has common read/write rules that are governed by MMCR0 PMCC bits. MMCR0 is also

[PATCH v4 03/15] target/ppc: add user read/write functions for MMCR2

Similar to the previous patch, let's add problem state read/write access to the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered to be read/written by userspace. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 9 +++ target/ppc/cpu_init.c

[PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction

This new version presents drastic design changes across all areas, most of them based on the feedback received in v3. - TCG reviewers: for people looking to review only TCG related changes, here's a summmary of where are the TCG code in the series: * Patches that have a lot of TCG/translation cha

[PATCH v4 04/15] target/ppc: adding user read/write functions for PMCs

Problem state needs to be able to read and write the PMU counters, otherwise it won't be aware of any sampling result that the PMU produces after a Perf run. This patch does that in a similar fashion as already done in the previous patches. PMCs 5 and 6 have a special condition, aside from the con

[PATCH v4 01/15] target/ppc: add MMCR0 PMCC bits to hflags

We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+ emulation and following PowerISA v3.1. This requires several PMU related registers to be exposed to userspace (problem state). PowerISA v3.1 dictates that the PMCC bits of the MMCR0 register controls the level of access of the

Re: [PATCH 1/2] hw/misc/bcm2835_property: Fix framebuffer with recent RPi kernels

On Sun, 2021-10-17 at 17:08 +0200, Philippe Mathieu-Daudé wrote: > Hi Benjamin, > > On 10/17/21 09:48, Benjamin Herrenschmidt wrote: > > The framebuffer driver fails to initialize with recent Raspberry Pi > > kernels, such as the ones shipped in the current RaspiOS images > > (with the out of tree

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On Sun, Oct 17, 2021 at 4:59 PM Frank Chang wrote: > > On Sun, Oct 17, 2021 at 8:55 AM Frank Chang wrote: >> >> On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson >> wrote: >>> >>> On 10/16/21 1:52 AM, Frank Chang wrote: >>> > On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson >>> > >> >

Re: [PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension

On Sat, Oct 16, 2021 at 7:13 PM wrote: > > From: Frank Chang > > Zfhmin extension is a subset of Zfh extension, consisting only of data > transfer and conversion instructions. > > If enabled, only the following instructions from Zfh extension are > included: > * flh, fsh, fmv.x.h, fmv.h.x, fcvt

Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store

On Sat, Oct 16, 2021 at 7:08 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson > --- > target/riscv/cpu.c| 1 + > target/riscv/cpu.h| 1 +

Re: [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify

On Sat, Oct 16, 2021 at 7:11 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 6 ++ > t

Re: [PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare

On Sat, Oct 16, 2021 at 7:12 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 21 +++

Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move

On Sat, Oct 16, 2021 at 7:09 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson > --- > target/riscv/fpu_helper.c | 67 + > target/riscv/helper.h |

Re: [PATCH v3 2/6] target/riscv: zfh: half-precision computational

On Sat, Oct 16, 2021 at 7:08 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 86 ++

Re: [PATCH v3] hw/riscv: virt: Use machine->ram as the system memory

On Sat, Oct 16, 2021 at 1:09 PM MingWang Li wrote: > > From: Mingwang Li > > If default main_mem is used to be registered as the system memory, > other memory cannot be initialized. Therefore, the system memory > should be initialized to the machine->ram, which consists of the > default main_mem

[PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts

From: BALATON Zoltan Other functions in the VT82xx chips need to raise ISA interrupts. Keep a reference to them in the device state and add via_isa_set_irq() to allow setting their state. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <

[PULL 14/17] via-ide: Set user_creatable to false

From: BALATON Zoltan This model only works as a function of the via superio chip not as a standalone PCI device. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211015092159.3e863748...@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/via.c |

Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

On Fri, Oct 15, 2021 at 5:50 PM wrote: > > From: Frank Chang > > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in > commit: c445593, but other TB_FLAGS bits for rvv and rvh were > not shift as well so these bits may overlap with each other when > rvv is enabled. > > Signed-off-by: Fran

[PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r()

Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-5-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) dif

[PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode

While for the DEXTR_S.H opcode: "The shift argument is provided in the instruction." For the DEXTRV_S.H opcode we have: "The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored." While

[PULL 15/17] vt82c686: Move common code to via_isa_realize

From: BALATON Zoltan The vt82c686b_realize and vt8231_realize methods are almost identical, factor out the common parts to a via_isa_realize function to avoid code duplication. Signed-off-by: BALATON Zoltan Reviewed-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Message-Id: <7cb7a16ff4d

[PULL 17/17] via-ide: Avoid using isa_get_irq()

From: BALATON Zoltan Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq() that has a comment saying it should not be used. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: <26cb1848c9fc0360df7a57c2c9ba5e03

[PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf()

Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-6-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 23 ++- 1 file changed, 14 insertions(+),

[PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()

Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions"), the 'v2_t' TCG temporary has never been used. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211014224551.2204949-1-f4...@amsat.org>

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