On 19/10/2021 17:27, Eduardo Habkost wrote:
On Tue, Oct 12, 2021 at 10:24:28AM +0200, Jean-Louis Dupond wrote:
hw_compat modes only take into account their base name.
What do you mean by "base name"?
virtio-net-pci (without the (non-)transitional extension.
But if a device is created with (no
On Wed, Oct 20, 2021 at 4:07 AM Jason Wang wrote:
>
> On Wed, Oct 20, 2021 at 10:02 AM Jason Wang wrote:
> >
> > On Tue, Oct 19, 2021 at 6:29 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Tue, Oct 19, 2021 at 11:25 AM Jason Wang wrote:
> > > >
> > > >
> > > > 在 2021/10/1 下午3:06, Eugenio Pér
On Wed, Oct 20, 2021 at 4:01 AM Jason Wang wrote:
>
> On Tue, Oct 19, 2021 at 4:40 PM Eugenio Perez Martin
> wrote:
> >
> > On Fri, Oct 15, 2021 at 6:42 AM Jason Wang wrote:
> > >
> > >
> > > 在 2021/10/15 上午12:39, Eugenio Perez Martin 写道:
> > > > On Wed, Oct 13, 2021 at 5:47 AM Jason Wang wrote
> -Original Message-
> From: Jason Wang
> Sent: Wednesday, October 20, 2021 11:13 AM
> To: Zhang, Chen
> Cc: Eric Blake ; Markus Armbruster
> ; qemu-dev ; Li Zhijian
> ; Lukas Straub
> Subject: Re: [PATCH V3] net/colo: check vnet_hdr_support flag when using
> virtio-net
>
> On Wed, Oc
Stefan Reiter writes:
> 'protocol' and 'connected' are better suited as enums than as strings,
> make use of that. No functional change intended.
>
> Suggested-by: Markus Armbruster
> Signed-off-by: Stefan Reiter
> ---
> monitor/hmp-cmds.c | 17 +++--
> monitor/qmp-cmds.c | 35
On Mon, Oct 18, 2021 at 7:37 PM LIU Zhiwei wrote:
>
> Hi Alistair,
>
> Sorry for the send error. And I have a question about this patch set.
Hello Zhiwei,
>
> Firstly, I totally support the vector v1.0 upstream.
Great!
>
> The concern is how to deal with the v0.7.1 code on QEMU. There are so
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 2 ++
target/loongarch/insn_trans/trans_core.c | 23 +
target/loongarch/insn_trans/t
Hi Xiaojuan,
On 2021/10/20 09:33, 杨小娟 wrote:
> Hi， Xuerui
> Thank you for your advice， I‘ll modify the README and put the binary in
> the github.
> The remaining patches are send backed， I’ll find the cause and send them
> again.
Okay, understood; thanks for the quick response.
You ma
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
This patch Add loongarch interrupt and exception handle.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 293 +
target/loongarch/cpu.h | 6 +-
2 files changed, 298 inserti
> On Oct 18, 2021, at 6:26 AM, Cédric Le Goater wrote:
>
> Hello,
>
> The Aspeed SoCs have a dual boot function for firmware fail-over
> recovery. The system auto-reboots from the second flash if the main
> flash does not boot successfully within a certain amount of time. This
> function is ca
This patch implements the multiqueue support for vhost-vdpa. This is
done simply by reading the number of queue pairs from the config space
and initialize the datapath and control path net client.
Signed-off-by: Jason Wang
---
hw/virtio/vhost-vdpa.c | 2 +-
net/vhost-vdpa.c | 105 +++
On Wed, Oct 20, 2021 at 9:31 AM Jason Wang wrote:
>
> On Wed, Oct 20, 2021 at 12:56 AM Eduardo Habkost wrote:
> >
> > On Tue, Oct 19, 2021 at 12:13:17PM -0400, Michael S. Tsirkin wrote:
> > > On Tue, Oct 19, 2021 at 11:29:13AM -0400, Eduardo Habkost wrote:
> > > > On Tue, Oct 19, 2021 at 06:59:09
This patch introduces a new field in the vhost_dev structure to record
the last virtqueue index for the virtio device. This will be useful
for the vhost backends with 1:N model to start or stop the device
after all the vhost_dev structures were started or stopped.
Signed-off-by: Jason Wang
---
h
Most of the time, "queues" really means queue pairs. So this patch
switch to use "queue_pairs" to avoid confusion.
Signed-off-by: Jason Wang
---
hw/net/vhost_net.c | 6 +-
hw/net/virtio-net.c| 150 -
include/hw/virtio/virtio-net.h | 4 +
This patch implements the control virtqueue support for vhost. This
requires virtio-net to figure out the datapath queue pairs and control
virtqueue via is_datapath and pass the number of those two types
of virtqueues to vhost_net_start()/vhost_net_stop().
Signed-off-by: Jason Wang
---
hw/net/vh
We assume there's no cvq in the past, this is not true when we need
control virtqueue support for vhost-user backends. So this patch
implements the control virtqueue support for vhost-net. As datapath,
the control virtqueue is also required to be coupled with the
NetClientState. The vhost_net_start
This patch switches to let net_vhost_vdpa_init() to return
NetClientState *. This is used for the callers to allocate multiqueue
NetClientState for multiqueue support.
Signed-off-by: Jason Wang
---
net/vhost-vdpa.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff
This patch introduces a boolean for the device has control queue which
can accepts control command via network queue.
The first user would be the control virtqueue support for vhost.
Signed-off-by: Jason Wang
---
include/net/net.h | 5 +
net/net.c | 24 +---
2 f
Unlike vhost-kernel, vhost-vdpa adapts a single device multiqueue
model. So we need to simply use virtqueue index as the vhost virtqueue
index. This is a must for multiqueue to work for vhost-vdpa.
Signed-off-by: Jason Wang
---
hw/virtio/vhost-vdpa.c | 4 ++--
1 file changed, 2 insertions(+), 2
Vhost-vdpa uses one device multiqueue queue (pairs) model. So we need
to classify the one time request (e.g SET_OWNER) and make sure those
request were only called once per device.
This is used for multiqueue support.
Signed-off-by: Jason Wang
---
hw/virtio/vhost-vdpa.c | 53 +++
This patch switches to open device fd in net_init_vhost_vpda(). This is
used to prepare for the multiqueue support.
Reviewed-by: Stefano Garzarella
Signed-off-by: Jason Wang
---
net/vhost-vdpa.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/net/vho
Hi All:
This patch implements the multiqueue support for vhost-vDPA. The most
important requirement si the control virtqueue support. The virtio-net
and vhost-net core are tweak to support control virtqueue as if what
data queue pairs are done: a dedicated vhost_net device which is
coupled with th
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index afd186abac..7fa3851251 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -45,6 +45,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_TLBPE] = "TLB
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 19 +
target/loongarch/helper.h| 8 +
target/loo
On Tue, Oct 19, 2021 at 11:18:17AM +0200, Thomas Huth wrote:
65;6402;1c> Recent Linux kernels are accessing the PCI device in slot 0 that
> represents the PCI host bridge. This causes ppc4xx_pci_map_irq()
> to return -1 which causes an assert() later:
>
> hw/pci/pci.c:262: pci_bus_change_irq_leve
On Tue, Oct 19, 2021 at 2:55 PM Michael S. Tsirkin wrote:
>
> On Thu, Sep 30, 2021 at 10:33:43AM +0800, Cindy Lu wrote:
> > Add new call back function in vhost-vdpa, this call back function will
> > set the fb number to hardware.
> >
> > Signed-off-by: Cindy Lu
>
> fb being what? you mean fd. sai
The position of this read-only field is dependent on the current xlen.
Rather than having to compute that difference in many places, compute
it only on read.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 3 +--
target/riscv/csr.c| 37 +++
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zh
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 31 +
target/riscv/insn_trans/trans_rvb.c.inc | 92 ++
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 16
target/riscv/insn_trans/trans_rvb.c.inc | 3
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu_bits.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187
This is a partial patch set attempting to set things in the
right direction for both the UXL and RV128 patch sets.
r~
Changes for v6:
* Rebase on riscv-to-apply.next.
Changes for v5:
* Fix cpu_dump, which asserted for -accel qtest.
Instead of filtering CSRs explicitly in cpu_dump,
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.c | 89 +++---
1 file changed
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 16 +++
target/riscv/insn_trans/trans_rvm
Move the function to cpu_helper.c, as it is large and growing.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h| 47 ++-
target/riscv/cpu_helper.c | 46 +
In preparation for RV128, replace a simple predicate
with a more versatile test.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff -
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++-
1 file changed, 6 i
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target
On Wed, Oct 20, 2021 at 10:53 AM Zhang, Chen wrote:
>
>
>
> > -Original Message-
> > From: Jason Wang
> > Sent: Tuesday, October 19, 2021 3:39 PM
> > To: Zhang, Chen ; Eric Blake ;
> > Markus Armbruster
> > Cc: qemu-dev ; Li Zhijian
> > ; Lukas Straub ; Tao Xu
> >
> > Subject: Re: [PATC
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu.c|
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e6..8c579dc297b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -601,6 +601,7 @@ static Property riscv_cpu_p
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8c579dc297b..4c0e6532164 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -602,6 +602,7 @@ static Property riscv_cpu_p
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32.deco
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 6 ++
target/riscv/helper.h | 1 +
target/riscv/insn32.de
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 86 +++
target/riscv/helper.h | 13 +++
target/ri
From: Frank Chang
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h,
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
target/riscv/i
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/insn32.decode| 4 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 65 ++
On Sat, Oct 16, 2021 at 4:54 PM wrote:
> From: Chih-Min Chao
>
> The sNaN propagation behavior has been changed since
> cd20cee7 in https://github.com/riscv/riscv-isa-manual.
>
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> ---
> target/riscv/fpu_helper.c | 16
> -Original Message-
> From: Jason Wang
> Sent: Tuesday, October 19, 2021 3:39 PM
> To: Zhang, Chen ; Eric Blake ;
> Markus Armbruster
> Cc: qemu-dev ; Li Zhijian
> ; Lukas Straub ; Tao Xu
>
> Subject: Re: [PATCH V3] net/colo: check vnet_hdr_support flag when using
> virtio-net
>
>
On Mon, Oct 18, 2021 at 11:44 PM Stefano Garzarella wrote:
>
> On Mon, Oct 11, 2021 at 12:28:22PM +0800, Jason Wang wrote:
> >Unlike vhost-kernel, vhost-vdpa adapts a single device multiqueue
> >model. So we need to simply use virtqueue index as the vhost virtqueue
> >index. This is a must for mul
On Tue, Oct 19, 2021 at 2:56 PM Michael S. Tsirkin wrote:
>
> On Thu, Sep 30, 2021 at 10:33:38AM +0800, Cindy Lu wrote:
> > these patches add the support for configure interrupt
> >
> > These codes are all tested in vp-vdpa (support configure interrupt)
> > vdpa_sim (not support configure interrup
On Tue, Oct 19, 2021 at 2:52 PM Michael S. Tsirkin wrote:
>
> On Thu, Sep 30, 2021 at 10:33:42AM +0800, Cindy Lu wrote:
> > To support the config interrupt, we need to
> > add a new call back function for config interrupt.
> >
> > Signed-off-by: Cindy Lu
>
> Pls make commit log more informative.
Ping...
Is this a right direction to go or should I continue on with this ?
On 2021/10/7 18:43, Yanan Wang wrote:
Hi,
The motivation of this series is to improve the scalability of SMP
related Docs, so that we can easily/clearly extend them without making
confusion when we plan to introduce mo
On Wed, Oct 20, 2021 at 10:02 AM Jason Wang wrote:
>
> On Tue, Oct 19, 2021 at 6:29 PM Eugenio Perez Martin
> wrote:
> >
> > On Tue, Oct 19, 2021 at 11:25 AM Jason Wang wrote:
> > >
> > >
> > > 在 2021/10/1 下午3:06, Eugenio Pérez 写道:
> > > > Use translations added in VhostIOVATree in SVQ.
> > > >
On Tue, Oct 19, 2021 at 6:29 PM Eugenio Perez Martin
wrote:
>
> On Tue, Oct 19, 2021 at 11:25 AM Jason Wang wrote:
> >
> >
> > 在 2021/10/1 下午3:06, Eugenio Pérez 写道:
> > > Use translations added in VhostIOVATree in SVQ.
> > >
> > > Now every element needs to store the previous address also, so Vir
On Tue, Oct 19, 2021 at 4:40 PM Eugenio Perez Martin
wrote:
>
> On Fri, Oct 15, 2021 at 6:42 AM Jason Wang wrote:
> >
> >
> > 在 2021/10/15 上午12:39, Eugenio Perez Martin 写道:
> > > On Wed, Oct 13, 2021 at 5:47 AM Jason Wang wrote:
> > >>
> > >> 在 2021/10/1 下午3:05, Eugenio Pérez 写道:
> > >>> This wi
Hi Igor,
On Tue, Oct 19, 2021 at 3:39 PM Igor Mammedov wrote:
>
> On Mon, 18 Oct 2021 23:38:24 +0800
> Bin Meng wrote:
>
> > Using memory_region_init_ram(), which can't possibly handle vhost-user,
> > and can't work as expected with '-numa node,memdev' options.
> >
> > Use MachineState::ram inst
Ping... for review of the newly added ACPI patches.
On 2021/10/14 21:21, Yanan Wang wrote:
Hi,
This is the latest v8 with update in patch #6 and #8. Now only one
generic reference file for PPTT is added in tests/data/acpi/virt.
Machiel and Igor, please help to have a look, thanks!
And sorry fo
Ping...
On 2021/10/14 21:22, Yanan Wang wrote:
Add a generic empty binary file for the new introduced PPTT table
under tests/data/acpi/virt, and list it as files to be changed in
tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Yanan Wang
---
tests/data/acpi/virt/PPTT
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-of
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-of
Ping...
On 2021/10/14 21:22, Yanan Wang wrote:
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
Disassembled output of the updated new file:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler v
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-of
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-of
As of today, all RISC-V machines (except virt) are still using
memory_region_init_ram()
to initilize the sysytem RAM, which can't possibly handle vhost-user, and can't
work as expected with '-numa node,memdev' options.
Change to use MachineState::ram instead of manually initializing RAM memory
re
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
+target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr)
+{
+int64_t v;
+
+#define CASE_CSR_RDQ(csr)\
+case LOONGARCH_CSR_ ## csr: \
+{\
+v = env->CSR_ ## csr;\
+
On Wed, Oct 20, 2021 at 12:56 AM Eduardo Habkost wrote:
>
> On Tue, Oct 19, 2021 at 12:13:17PM -0400, Michael S. Tsirkin wrote:
> > On Tue, Oct 19, 2021 at 11:29:13AM -0400, Eduardo Habkost wrote:
> > > On Tue, Oct 19, 2021 at 06:59:09AM -0400, Michael S. Tsirkin wrote:
> > > > On Tue, Oct 19, 202
On 10/19/21 3:10 PM, Alistair Francis wrote:
On Wed, Oct 20, 2021 at 2:18 AM Richard Henderson
wrote:
Allocate 8 columns per register name.
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
This probably isn't required though as there is already a si
On Tue, Oct 19, 2021 at 23:53 Michael Roth wrote:
> Quoting Ani Sinha (2021-10-19 09:43:52)
> >
> >
> > On Tue, 19 Oct 2021, Michael Roth wrote:
> >
> > > Hi everyone,
> > >
> > > The following new patches are queued for QEMU stable v6.0.1:
> > >
> > > https://gitlab.com/qemu-project/qemu/-/com
Ani, below. Eric
On 10/19/21 09:58, Ani Sinha wrote:
On Fri, 15 Oct 2021, Eric DeVolder wrote:
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 6.
Below is the disassembly of an ERST table, tests/data/acpi/pc/ERST.
This is a PCI device and as such its base address ca
On Mon, Oct 18, 2021 at 3:34 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 +
> target/riscv/cpu.h | 11 ++
> target/riscv/csr.c | 285 +
> 3 files changed, 298 ins
On Wed, Oct 20, 2021 at 2:52 AM Richard Henderson
wrote:
>
> The position of this read-only field is dependent on the
> current cpu width. Rather than having to compute that
> difference in many places, compute it only on read.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
On Wed, Oct 20, 2021 at 2:50 AM Richard Henderson
wrote:
>
> Use the official debug read interface to the csrs,
> rather than referencing the env slots directly.
> Put the list of csrs to dump into a table.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> t
On Wed, Oct 20, 2021 at 2:18 AM Richard Henderson
wrote:
>
> Allocate 8 columns per register name.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
This probably isn't required though as there is already a similar
patch in my tree:
https://github.co
On 10/19/21 18:12, Christophe Leroy wrote:
Le 19/10/2021 à 16:56, BALATON Zoltan a écrit :
On Tue, 19 Oct 2021, Christophe Leroy wrote:
Le 19/10/2021 à 15:44, Christophe Leroy a écrit :
There is something:
=> bootm 0
Wrong Image Format for bootm command
ERROR: can't get kernel image!
=> md
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
@@ -272,6 +288,7 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
+#ifdef CONFIG_USER_ONLY
static bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
On 10/19/21 18:12, Christophe Leroy wrote:
Le 19/10/2021 à 16:56, BALATON Zoltan a écrit :
On Tue, 19 Oct 2021, Christophe Leroy wrote:
Le 19/10/2021 à 15:44, Christophe Leroy a écrit :
There is something:
=> bootm 0
Wrong Image Format for bootm command
ERROR: can't get kernel image!
=> md
Introduce a QMP command 'query-kvmstats' to query KVM for vm and vcpu
fd-based statistics. The kernel support is provided by commit:
cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data")
The interface supports an optional 'filter' argument to specify a
particular stat to query.
Leverage the QMP support for fd-based KVM stats.
The interface supports an optional 'filter' argument to specify a
particular stat to query. Base and exponent are displayed in human
readable format.
Examples:
(qemu) info kvmstats
vm:
max_mmu_page_hash_collisions (peak): 0
nx_lpage_splits (i
This patchset adds QEMU support for querying fd-based KVM stats. The kernel
support is provided by:
cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data")
Patch 1 adds QMP support; patch 2 adds HMP support.
Mark Kanda (2):
qmp: Support fd-based KVM stats query
hmp: Support f
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
This patch introduce qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 28
2 files changed, 32 insertions(+), 2
On Thu, Sep 16, 2021 at 10:40:43AM +0200, Hanna Reitz wrote:
> Currently, lo_inode.fhandle is always NULL and so always keep an O_PATH
> FD in lo_inode.fd. Therefore, when the respective inode is unlinked,
> its inode ID will remain in use until we drop our lo_inode (and
> lo_inode_put() thus clos
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps loongarch_sysemu_ops = {
+.legacy_vmsd = &vmstate_loongarch_cpu,
+};
+#endif
The documentation for legacy_vmsd is quite clear:
Do not use in new
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
+#ifndef CONFIG_USER_ONLY
+static void set_loongarch_csr(CPULoongArchState *env)
+{
+uint64_t t;
+
+t = FIELD_DP64(0, CSR_PRCFG1, SAVE_NUM, 8);
+t = FIELD_DP64(t, CSR_PRCFG1, TIMER_BITS, 0x2f);
+t = FIELD_DP64(t, CSR_PRCFG1, VSMAX, 0x7);
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
+/*
+ * All Possible CSR registers used by tcg
+ *
+ * default value in target/loongarch/cpu.c
+ *
+ * This macro will be used only in:
+ * > target/loongarch/cpu.h:CPULoongArchState
+ *
+ * during translate:
+ * > helper_csr_rdq()
+ * > helper_csr_w
On Thu, Sep 16, 2021 at 10:40:44AM +0200, Hanna Reitz wrote:
> When the inode_file_handles option is set, try to generate a file handle
> for new inodes instead of opening an O_PATH FD.
>
> Being able to open these again will require CAP_DAC_READ_SEARCH, so
> setting this option will result in us
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
---
target/loongarch/README | 134 +++
target/loongarch/ramdisk | Bin 0 -> 3077952 bytes
target/loongarch/vmlinux | Bin 0 -> 24565536 bytes
3 files changed, 134 insertions(+)
create mode 100644 target/loongar
On 10/19/21 4:19 AM, Michael S. Tsirkin wrote:
The following changes since commit 9c050b661d3a43dfe2fd44106e559b39706d1296:
Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into
staging (2021-10-18 09:16:51 -0700)
are available in the Git repository at:
git://git.kernel.
Quoting Ani Sinha (2021-10-19 09:43:52)
>
>
> On Tue, 19 Oct 2021, Michael Roth wrote:
>
> > Hi everyone,
> >
> > The following new patches are queued for QEMU stable v6.0.1:
> >
> > https://gitlab.com/qemu-project/qemu/-/commits/stable-6.0-staging/
> >
> > Patch freeze is 2021-10-26, and the
On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
+static inline void divrem128(uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh,
+ uint64_t *ql, uint64_t *qh,
+ uint64_t *rl, uint64_t *rh)
I think we should move
On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
Introducing unsigned quad, signed quad, and octo accesses types
to handle load and store by 128-bit processors.
Signed-off-by: Frédéric Pétrot
---
include/exec/memop.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/inclu
Thanks for taking a look. I've sent out a new version of the patch.
Besides the Makefile change, I have also replaced the direct
gdbserver_state manipulation with a call to gdb_set_stop_cpu.
Further responses inline.
On 19/10/2021 19:02, Alex Bennée wrote:
Pavel Labath writes:
Respond wit
Pavel Labath writes:
> On 15/10/2021 17:59, Alex Bennée wrote:
>> Pavel Labath writes:
>>
>>> Ping.
>>>
>>> (This is my first qemu patch, so please let me know if I am doing
>>> something wrong.)
>> Apologies it slipped though the cracks. I shall have a look on
>> Monday.
>>
>
> I don't want
Respond with Txxthread:; instead of a plain Sxx to indicate which
thread received the signal. Otherwise, the debugger will associate it
with the main one. Also automatically select this thread, as that is
what gdb expects.
Signed-off-by: Pavel Labath
---
gdbstub.c
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