Re: Deprecate the ppc405 boards in QEMU? (was: [PATCH v3 4/7] MAINTAINERS: Orphan obscure ppc platforms)

Le 20/10/2021 à 15:16, Christophe Leroy a écrit : Le 20/10/2021 à 14:43, Cédric Le Goater a écrit : On 10/20/21 13:42, BALATON Zoltan wrote: On Wed, 20 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/5/21 14:29, Thomas Huth wrote: On 05/10/2021 14.20, BALATON Zoltan wrote: On Tue, 5 Oct 2

Re: [PATCH v3 0/3] tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges for q35

On Thu, 21 Oct 2021, Michael S. Tsirkin wrote: > On Thu, Oct 21, 2021 at 07:18:43AM +0530, Ani Sinha wrote: > > > > > > On Wed, Oct 20, 2021 at 2:09 PM Michael S. Tsirkin wrote: > > > > On Thu, Oct 07, 2021 at 07:27:47PM +0530, Ani Sinha wrote: > > > changelist: > > > v3: removed "n

Re: [PATCH v7 21/21] scripts: add loongarch64 binfmt config

Hi, Xuerui On 10/18/2021 11:49 PM, WANG Xuerui wrote: > Hi Song, > > On 10/18/21 20:47, Song Gao wrote: >> Signed-off-by: Song Gao >> Signed-off-by: Xiaojuan Yang >> Reviewed-by: Richard Henderson >> --- >>   scripts/qemu-binfmt-conf.sh | 6 +- >>   1 file changed, 5 insertions(+), 1 deleti

Re: [PATCH v3 0/3] tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges for q35

On Thu, Oct 21, 2021 at 07:18:43AM +0530, Ani Sinha wrote: > > > On Wed, Oct 20, 2021 at 2:09 PM Michael S. Tsirkin wrote: > > On Thu, Oct 07, 2021 at 07:27:47PM +0530, Ani Sinha wrote: > > changelist: > > v3: removed "nodefaults" from the command line and rebased the patchset. >

Re: [PATCH v6 4/5] qapi/monitor: only allow 'keep' SetPasswordAction for VNC and deprecate

Stefan Reiter writes: > VNC only supports 'keep' here, enforce this via a seperate > SetPasswordActionVnc enum and mark the option 'deprecated' (as it is > useless with only one value possible). > > Suggested-by: Eric Blake > Signed-off-by: Stefan Reiter With the next patch squashed in: Review

Re: [PATCH v6 5/5] docs: add deprecation note about 'set_password' param 'connected'

Stefan Reiter writes: > Signed-off-by: Stefan Reiter > --- > > Seperate patch since it read a bit unsure in the review, feel free to either > drop or squash this. > > docs/about/deprecated.rst | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/docs/about/deprecated.rst b/docs/about/

Re: [PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions

On Fri, Oct 15, 2021 at 6:18 PM wrote: > > From: Frank Chang > > Add the following instructions: > > * vmv1r.v > * vmv2r.v > * vmv4r.v > * vmv8r.v > > Signed-off-by: Frank Chang Acked-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 4 > target/riscv/ins

Re: [PATCH v6 3/5] qapi/monitor: allow VNC display id in set/expire_password

Stefan Reiter writes: > It is possible to specify more than one VNC server on the command line, > either with an explicit ID or the auto-generated ones à la "default", > "vnc2", "vnc3", ... > > It is not possible to change the password on one of these extra VNC > displays though. Fix this by addi

Re: [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions

On Fri, Oct 15, 2021 at 6:15 PM wrote: > > From: Frank Chang > > NaN-boxed the scalar floating-point register based on RVV 1.0's rules. > > Signed-off-by: Frank Chang Acked-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 4 +-- > target/riscv/insn_trans/tran

Re: [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions

On Fri, Oct 15, 2021 at 6:13 PM wrote: > > From: Frank Chang > > * Remove "vmv.s.x: dothing if rs1 == 0" constraint. > * Add vmv.x.s instruction. > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode

[PULL 24/25] target/ppc: adding user read/write functions for PMCs

From: Daniel Henrique Barboza Problem state needs to be able to read and write the PMU counters, otherwise it won't be aware of any sampling result that the PMU produces after a Perf run. This patch does that in a similar fashion as already done in the previous patches. PMCs 5 and 6 have a speci

[PULL 19/25] tests/acceptance: Add a test for the bamboo ppc board

From: Thomas Huth The kernel and initrd from the "Aboriginal Linux" project can be used to run some tests on the bamboo ppc machine. Signed-off-by: Thomas Huth Message-Id: <20211015090008.1299609-1-th...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-

[PULL 25/25] hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels

From: Thomas Huth Recent Linux kernels are accessing the PCI device in slot 0 that represents the PCI host bridge. This causes ppc4xx_pci_map_irq() to return -1 which causes an assert() later: hw/pci/pci.c:262: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed. Thus we should allocate

[PULL 18/25] ppc/pegasos2: Implement power-off RTAS function with VOF

From: BALATON Zoltan This only helps Linux guests as only that seems to use it. Signed-off-by: BALATON Zoltan Message-Id: <1c1e030f2bbc86e950b3310fb5922facdc21ef86.1634241019.git.bala...@eik.bme.hu> Signed-off-by: David Gibson --- hw/ppc/pegasos2.c | 11 +++ 1 file changed, 11 insert

[PULL 23/25] target/ppc: add user read/write functions for MMCR2

From: Daniel Henrique Barboza Similar to the previous patch, let's add problem state read/write access to the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered to be read/written by userspace. Signed-off-by: Daniel Henrique Barboza Message-Id: <20211018010133.315842-4-danielh

[PULL 16/25] ppc/pegasos2: Access MV64361 registers via their memory region

From: BALATON Zoltan Instead of relying on the mapped address of the MV64361 registers access them via their memory region. This is not a problem at reset time when these registers are mapped at the default address but the guest could change this later and then the RTAS calls accessing PCI config

[PULL 22/25] target/ppc: add user read/write functions for MMCR0

From: Gustavo Romero Userspace need access to PMU SPRs to be able to operate the PMU. One of such SPRs is MMCR0. MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU register. This class of registers has common read/write rules that are governed by MMCR0 PMCC bits. MMCR0 is also

Re: [PATCH v6 2/5] qapi/monitor: refactor set/expire_password with enums

Stefan Reiter writes: > 'protocol' and 'connected' are better suited as enums than as strings, > make use of that. No functional change intended. > > Suggested-by: Markus Armbruster > Signed-off-by: Stefan Reiter Reviewed-by: Markus Armbruster

[PULL 17/25] ppc/pegasos2: Add constants for PCI config addresses

From: BALATON Zoltan Define a constant for PCI config addresses to make it clearer what these numbers are. Signed-off-by: BALATON Zoltan Message-Id: <9bd8e84d02d91693b71082a1fadeb86e6bce3025.1634241019.git.bala...@eik.bme.hu> Signed-off-by: David Gibson --- hw/ppc/pegasos2.c | 6 -- 1 fi

Re: [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended

On Fri, Oct 15, 2021 at 6:28 PM wrote: > > From: Frank Chang > > For some vector instructions (e.g. vmv.s.x), the element is loaded with > sign-extended. > > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/t

[PULL 20/25] target/ppc: Filter mtmsr[d] input before setting MSR

From: Matheus Ferst PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or MSR[LE]", but the current code only filters the GPR-provided value if L=1. This behavior caused some problems in FreeBSD, and a build option was added to work around the issue [1], but it seems that the b

[PULL 15/25] ppc/pegasos2: Implement get-time-of-day RTAS function with VOF

From: BALATON Zoltan This is needed for Linux to access RTC time. Signed-off-by: BALATON Zoltan Message-Id: <6233eb07c680d6c74427e11b9641958f98d53378.1634241019.git.bala...@eik.bme.hu> Signed-off-by: David Gibson --- hw/ppc/pegasos2.c | 25 + 1 file changed, 25 insert

[PULL 21/25] target/ppc: add MMCR0 PMCC bits to hflags

From: Daniel Henrique Barboza We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+ emulation and following PowerISA v3.1. This requires several PMU related registers to be exposed to userspace (problem state). PowerISA v3.1 dictates that the PMCC bits of the MMCR0 register con

[PULL 10/25] target/ppc: Fix XER access in gdbstub

From: Matheus Ferst The value of XER is split in multiple fields of CPUPPCState, like env->xer and env->so. To get/set the whole register from gdb, we should use cpu_read_xer/cpu_write_xer. Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst Mes

[PULL 05/25] hw/ppc/spapr_softmmu: Reduce include list

From: Philippe Mathieu-Daudé Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu") introduced a lot of unnecessary #include directives. Remove them. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211006170801.178023-1-phi...@redhat.com> Signed-off-by: David Gibson --- hw/pp

[PULL 14/25] ppc/pegasos2: Warn when using VOF but no kernel is specified

From: BALATON Zoltan Issue a warning when using VOF (which is the default) but no -kernel option given to let users know that it will likely fail as the guest has nothing to run. It is not a hard error because it may still be useful to start the machine without further options for testing or insp

[PULL 13/25] ppc/pegasos2: Restrict memory to 2 gigabytes

From: BALATON Zoltan The CHRP spec this board confirms to only allows 2 GiB of system memory below 4 GiB as the high 2 GiB is allocated to IO and system resources. To avoid problems with memory overlapping these areas restrict RAM to 2 GiB similar to mac_newworld. Signed-off-by: BALATON Zoltan

[PULL 06/25] spapr/xive: Use xive_esb_rw() to trigger interrupts

From: Cédric Le Goater xive_esb_rw() is the common routine used for memory accesses on ESB page. Use it for triggers also. Signed-off-by: Cédric Le Goater Message-Id: <20211006210546.641102-1-...@kaod.org> Signed-off-by: David Gibson --- hw/intc/spapr_xive_kvm.c | 4 +--- 1 file changed, 1 in

[PULL 08/25] tests/acceptance: Add tests for the ppc405 boards

From: Thomas Huth Using the U-Boot firmware, we can check that at least the serial console of the ppc405 boards is still usable. Signed-off-by: Thomas Huth Message-Id: <20211011125930.750217-1-th...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [dwg: Added

[PULL 09/25] linux-user/ppc: Fix XER access in save/restore_user_regs

From: Matheus Ferst We should use cpu_read_xer/cpu_write_xer to save/restore the complete register since some of its bits are in other fields of CPUPPCState. A test is added to prevent future regressions. Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Mat

[PULL 02/25] target/ppc: Use tcg_constant_i32() in gen_setb()

From: Philippe Mathieu-Daudé Avoid using TCG temporaries for the -1 and 8 constant values. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211003141711.3673181-2-f4...@amsat.org> Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 8 ++-- 1 file c

[PULL 07/25] hw/ppc: Fix iothread locking in the 405 code

From: Thomas Huth When using u-boot as firmware with the taihu board, QEMU aborts with this assertion: ERROR:../accel/tcg/tcg-accel-ops.c:79:tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()) Running QEMU with "-d in_asm" shows that the crash happens when writing to SPR 0

[PULL 11/25] linux-user: Fix XER access in ppc version of elf_core_copy_regs

From: Matheus Ferst env->xer doesn't hold some bits of XER, like OV and CA. To write the complete register in the core dump we should read XER value with cpu_read_xer. Reported-by: Lucas Mateus Castro (alqotel) Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-

[PULL 12/25] target/ppc: Fix XER access in monitor

From: Matheus Ferst We can't read env->xer directly, as it does not contain some bits of XER. Instead, we should have a callback that uses cpu_read_xer to read the complete register. Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst Message-Id

[PULL 03/25] target/ppc: Use tcg_constant_i64() in gen_brh()

From: Philippe Mathieu-Daudé The mask of the Byte-Reverse Halfword opcode is a read-only constant. We can avoid using a TCG temporary by moving the mask to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211003141711.3673181-3-f4...@amsat.org> Reviewed-by: Richard Hender

[PULL 00/25] ppc-for-6.2 queue 20211021

The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-10-20 06:10:51 -0700) are available in the Git repository at: https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.2-20211021 for you t

[PULL 01/25] spapr/xive: Add source status helpers

From: Cédric Le Goater and use them to set and test the ASSERTED bit of LSI sources. Signed-off-by: Cédric Le Goater Message-Id: <20211004212141.432954-1-...@kaod.org> Signed-off-by: David Gibson --- hw/intc/spapr_xive.c | 2 +- hw/intc/spapr_xive_kvm.c | 10 +++--- hw/intc/xive.c

[PULL 04/25] target/ppc: Fix the test raising the decrementer exception

From: Cédric Le Goater Commit 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer") introduced new int64t variables and broke the test triggering the decrementer exception. Revert partially the change to evaluate both clause of the if statement. Reported-by: Coverity CID 1464061 Fixes: 4d9b8ef9b5a

Re: [PATCH 0/4] vl: Prioritize device realizations

On Wed, Oct 20, 2021 at 03:44:08PM +0200, David Hildenbrand wrote: > On 18.08.21 21:42, Peter Xu wrote: > > This is a long pending issue that we haven't fixed. The issue is in QEMU we > > have implicit device ordering requirement when realizing, otherwise some of > > the > > device may not work p

Re: [PATCH v7 02/21] target/loongarch: Add core definition

On 10/21/21 11:21, Song Gao wrote: BTW, Account yangxiaoj...@loongson.cn It seems that she has been blacklisted. Xiaojuan sent 31 e-mails, which were not displayed since the 21st one, people who don't have a CC can't read all the emails,  and xiaojuan reply can't be in qemu-le...@nongnu.org.

Re: [PATCH v15 4/8] [RISCV_PM] Add J extension state description

On Wed, Oct 20, 2021 at 8:24 PM Alexey Baturo wrote: > > Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Alistair > --- > target/riscv/machine.c | 27 +++ > 1 file changed, 27 insertions(+) > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c >

Re: [PATCH v7 02/21] target/loongarch: Add core definition

Hi, all On 10/20/2021 09:56 PM, Richard Henderson wrote: > On 10/20/21 5:00 AM, WANG Xuerui wrote: >> On 2021/10/20 16:54, Song Gao wrote: >> >>> On 10/19/2021 01:38 AM, Philippe Mathieu-Daudé wrote: On 10/18/21 18:06, WANG Xuerui wrote: On 10/18/21 20:47, Song Gao wrote: >> +st

RE: [PATCH V3] net/colo: check vnet_hdr_support flag when using virtio-net

> -Original Message- > From: Jason Wang > Sent: Thursday, October 21, 2021 11:02 AM > To: Zhang, Chen > Cc: Eric Blake ; Markus Armbruster > ; qemu-dev ; Li Zhijian > ; Lukas Straub > Subject: Re: [PATCH V3] net/colo: check vnet_hdr_support flag when using > virtio-net > > On Wed, Oct

Re: [PATCH V3] net/colo: check vnet_hdr_support flag when using virtio-net

On Wed, Oct 20, 2021 at 2:19 PM Zhang, Chen wrote: > > > > > -Original Message- > > From: Jason Wang > > Sent: Wednesday, October 20, 2021 11:13 AM > > To: Zhang, Chen > > Cc: Eric Blake ; Markus Armbruster > > ; qemu-dev ; Li Zhijian > > ; Lukas Straub > > Subject: Re: [PATCH V3] net/c

Re: [RFC PATCH v4 20/20] vdpa: Add custom IOTLB translations to SVQ

On Wed, Oct 20, 2021 at 7:57 PM Eugenio Perez Martin wrote: > > On Wed, Oct 20, 2021 at 11:03 AM Jason Wang wrote: > > > > On Wed, Oct 20, 2021 at 2:52 PM Eugenio Perez Martin > > wrote: > > > > > > On Wed, Oct 20, 2021 at 4:07 AM Jason Wang wrote: > > > > > > > > On Wed, Oct 20, 2021 at 10:02

Re: [RFC PATCH v4 18/20] vhost: Add VhostIOVATree

On Wed, Oct 20, 2021 at 8:07 PM Eugenio Perez Martin wrote: > > On Wed, Oct 20, 2021 at 11:01 AM Jason Wang wrote: > > > > On Wed, Oct 20, 2021 at 3:54 PM Eugenio Perez Martin > > wrote: > > > > > > On Tue, Oct 19, 2021 at 11:23 AM Jason Wang wrote: > > > > > > > > On Tue, Oct 19, 2021 at 4:32

Re: [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2

On 10/20/21 3:27 PM, Luis Fernando Fujita Pires wrote: From: Richard Henderson Reduce some code duplication by folding the NE and EQ cases. Signed-off-by: Richard Henderson --- tcg/optimize.c | 161 + 1 file changed, 83 insertions(+), 78 dele

Re: [PATCH] Fix constant folding logic of setcond2_i32

On 10/21/21 10:13, Liren Wei wrote: For setcond2_i32 DST, A_low, A_high, B_low, B_high, TCG_COND_EQ, DST should be 0 as long as either half of A and B are not equal. Signed-off-by: Liren Wei --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c

[PATCH] Fix constant folding logic of setcond2_i32

For setcond2_i32 DST, A_low, A_high, B_low, B_high, TCG_COND_EQ, DST should be 0 as long as either half of A and B are not equal. Signed-off-by: Liren Wei --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c239c3bd07..45a1

[Bug 1947933] [NEW] xHCI Port Status Change Event at port powered

Public bug reported: Per section 4.19.3 of the xHCI version 1.0 specification, when the Port Power bit transitions from 0 to 1, if there is a connection on that port, a Port Status Change Event should be issued. Currently, when the port is powered, this event is not being issued. I don't know th

Re: [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals

On 10/20/21 9:17 AM, Alex Bennée wrote: +int nb_oargs = def->nb_oargs; for (i = 0; i < nb_oargs; i++) { nit: couldn't you just do for (i = 0; i < deb->nb_oargs; i++) or is that too much for the compiler to wrap it's head around?' That leaves the compiler with non-inv

Re: [PATCH v2 08/48] tcg/optimize: Split out fold_call

On 10/20/21 9:05 AM, Alex Bennée wrote: Richard Henderson writes: Calls are special in that they have a variable number of arguments, and need to be able to clobber globals. Signed-off-by: Richard Henderson --- tcg/optimize.c | 63 -- 1 fil

Re: [PATCH v3 0/3] tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges for q35

On Wed, Oct 20, 2021 at 2:09 PM Michael S. Tsirkin wrote: > On Thu, Oct 07, 2021 at 07:27:47PM +0530, Ani Sinha wrote: > > changelist: > > v3: removed "nodefaults" from the command line and rebased the patchset. > > v2: incorporated some of the feedbacks from Igor. > > v1 : initial RFC patch. > >

Re: [PATCH v2 00/48] tcg: optimize redundant sign extensions

On 10/20/21 9:13 AM, Alex Bennée wrote: Richard Henderson writes: Currently, we have support for optimizing redundant zero extensions, which I think was done with x86 and aarch64 in mind, which zero-extend all 32-bit operations into the 64-bit register. But targets like Alpha, MIPS, and RISC

Re: [PATCH v4 8/8] target/riscv: zfh: add Zfhmin cpu property

On Thu, Oct 21, 2021 at 9:25 AM Alistair Francis wrote: > > On Wed, Oct 20, 2021 at 1:13 PM wrote: > > > > From: Frank Chang > > > > Signed-off-by: Frank Chang > > Reviewed-by: Alistair Francis > > Alistair > > > --- > > target/riscv/cpu.c | 1 + > > 1 file changed, 1 insertion(+) > > > > dif

Re: [PATCH v4 8/8] target/riscv: zfh: add Zfhmin cpu property

On Wed, Oct 20, 2021 at 1:13 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8c579dc297b..4c0e6532164 100

Re: [PATCH v4 6/8] target/riscv: zfh: add Zfh cpu property

On Wed, Oct 20, 2021 at 1:15 PM wrote: > > From: Frank Chang > > Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1d69d1887e6..8c579dc297b 100

Re: [PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax

On Sat, Oct 16, 2021 at 6:55 PM wrote: > > From: Chih-Min Chao > > The sNaN propagation behavior has been changed since > cd20cee7 in https://github.com/riscv/riscv-isa-manual. It would be a good idea to justify why we are using the priv spec for the version check. > > Signed-off-by: Chih-Min C

Re: [PATCH v2 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id

On Wed, Oct 20, 2021 at 11:43 AM Bin Meng wrote: > > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing Machin

Re: [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: +static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ +*val = int128_make128(env->mstatus, env->mstatush); +return RISCV_EXCP_NONE; +} Needs updating from split SD bit. I s

Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id

On Wed, Oct 20, 2021 at 11:42 AM Bin Meng wrote: > > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing Machin

Re: [PATCH v2 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id

On Wed, Oct 20, 2021 at 11:48 AM Bin Meng wrote: > > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing Machin

Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: Support for a 128-bit satp. This is a bit more involved than necessary because we took the opportunity to increase the page size to 16kB, and change the page table geometry, which makes the page walk a bit more parametrizable (variables instead of defin

Re: [PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

On Wed, Oct 20, 2021 at 11:46 AM Bin Meng wrote: > > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing Machin

Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id

On Wed, Oct 20, 2021 at 11:44 AM Bin Meng wrote: > > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing Machin

Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id

On Wed, Oct 20, 2021 at 11:41 AM Bin Meng wrote: > > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing Machin

Re: [PATCH v3 16/21] target/riscv: adding high part of some csrs

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: Adding the high part of a minimal set of csr. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b96ccb37a..

Re: [PATCH] via-ide: Avoid expensive operations in irq handler

On Wed, 20 Oct 2021, Eduardo Habkost wrote: On Mon, Oct 18, 2021 at 12:10:04PM +0200, Philippe Mathieu-Daudé wrote: On 10/18/21 11:51, BALATON Zoltan wrote: On Mon, 18 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/18/21 03:36, BALATON Zoltan wrote: Cache the pointer to PCI function 0 (ISA bri

Re: [PATCH v2 5/5] speed/sdhci: Add trace events

Hi Cedric, On the subject s/speed/aspeed/. Otherwise: Reviewed-by: Francisco Iglesias /BR On [2021 Oct 18] Mon 15:26:09, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater > --- > hw/sd/aspeed_sdhci.c | 5 + > hw/sd/trace-events | 4 > 2 files changed, 9 insertions(+) > >

RE: [PATCH v2 18/48] tcg/optimize: Split out fold_brcond

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 33 +++-- > 1 file changed, 19 insertions(+), 14 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask"

From: Richard Henderson > Prepare for tracking different masks by renaming this one. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 142 + > 1 file changed, 72 insertions(+), 70 deletions(-) R

RE: [PATCH v2 19/48] tcg/optimize: Split out fold_setcond

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 23 ++- > 1 file changed, 14 insertions(+), 9 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi}

From: Richard Henderson > This will allow callers to tail call to these functions and return true > indicating > processing complete. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 9 + > 1 file changed, 5 insertions(+), 4 deletions

RE: [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2

From: Richard Henderson > Reduce some code duplication by folding the NE and EQ cases. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 161 + > 1 file changed, 83 insertions(+), 78 deletions(-) > +case TCG_COND_NE: > +in

RE: [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues

From: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 9 ++--- > 1 file changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2}

From: Richard Henderson > Split out a whole bunch of placeholder functions, which are currently > identical. > That won't last as more code gets moved. > > Use CASE_32_64_VEC for some logical operators that previously missed the > addition of vectors. > > Signed-off-by: Richard Henderson > ---

RE: [PATCH v2 12/48] tcg/optimize: Split out finish_folding

From: Richard Henderson > Copy z_mask into OptContext, for writeback to the first output within the new > function. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 49 + > 1 file changed, 33 insertions(+), 16 deletions(-) Reviewed-b

RE: [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2

From: Richard Henderson > Reduce some code duplication by folding the NE and EQ cases. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 145 - > 1 file changed, 72 insertions(+), 73 deletions(-) > -i = do_constant_fol

RE: [PATCH v2 06/48] tcg/optimize: Split out init_arguments

From: Richard Henderson > There was no real reason for calls to have separate code here. > Unify init for calls vs non-calls using the call path, which handles > TCG_CALL_DUMMY_ARG. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 25 +

RE: [PATCH v2 07/48] tcg/optimize: Split out copy_propagate

From: Richard Henderson > Continue splitting tcg_optimize. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 22 ++ > 1 file changed, 14 insertions(+), 8 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pes

RE: [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals

From: Richard Henderson > Rather than try to keep these up-to-date across folding, re-read nb_oargs at > the > end, after re-reading the opcode. > > A couple of asserts need dropping, but that will take care of itself as we > split the > function further. > > Signed-off-by: Richard Henderson

RE: [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*

From: Richard Henderson > Return -1 instead of 2 for failure. > This us to use comparisons against 0 for all cases. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 145 + > 1 file changed, 74 insertions(+), 71 deletions(-) Reviewed-

RE: [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}

From: Richard Henderson > This puts the separate mb optimization into the same framework as the others. > While fold_qemu_{ld,st} are currently identical, that won't last as more code > gets moved. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 89 +---

RE: [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext

From: Richard Henderson > This will expose the variable to subroutines that will be broken out of > tcg_optimize. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 11 ++- > 1 file changed, 6 insertions(+), 5 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de

RE: [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface

From: Richard Henderson > Adjust the interface to take the OptContext parameter instead of TCGContext or > both. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 67 +- > 1 file changed, 34 insertions(+), 33 deletions(-) Reviewed-by:

RE: [PATCH v2 03/48] tcg/optimize: Remove do_default label

From: Richard Henderson > Break the final cleanup clause out of the main switch statement. When fully > folding an opcode to mov/movi, use "continue" to process the next opcode, else > break to fall into the final cleanup. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 190 +

RE: [PATCH v2 02/48] tcg/optimize: Split out OptContext

From: Richard Henderson > Provide what will become a larger context for splitting the very large > tcg_optimize function. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 77 ++ > 1 file changed, 40 insertions(+), 37 deletions(-) Rev

RE: [PATCH v2 08/48] tcg/optimize: Split out fold_call

From: Richard Henderson > Calls are special in that they have a variable number of arguments, and need > to > be able to clobber globals. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 63 -- > 1 file changed, 41 insertions(+), 22

Re: [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: The csrs are accessed through function pointers: we set-up the table for the 128-bit accesses, make the stub a function that does what it should, and implement basic accesses on read-only csrs. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Por

Re: [PATCH 2/3] optionrom: add a DMA-enabled multiboot ROM

On 10/20/21 16:02, Paolo Bonzini wrote: > From: Marcus Hähnel > > Add a new option rom for the multiboot loader, using DMA transfers to copy > data instead of "rep insb". > > This significantly lowers QEMU's startup latency by a factor of about 40, > for example, going from 30sec to 0.8sec when

Re: [PATCH v2 5/5] speed/sdhci: Add trace events

On 10/18/21 15:26, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater > --- > hw/sd/aspeed_sdhci.c | 5 + > hw/sd/trace-events | 4 > 2 files changed, 9 insertions(+) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 4/5] aspeed/smc: Use a container for the flash mmio address space

On 10/18/21 15:26, Cédric Le Goater wrote: > Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225 > ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use > alias") introduced an alias for the flash mmio region. > > Using a container is cleaner. > > Cc: Philippe Mathie

Re: [PATCH v2 2/5] aspeed: Initialize the watchdog device models before the FMC models

On 10/18/21 15:26, Cédric Le Goater wrote: > Next changes will map the WDT2 registers in the AST2600 FMC memory > region. Make sure the MemoryRegion pointers are correctly initialized > before setting the object links. > > Do the same in the Aspeed AST2400 and AST2500 SoC models for > consistency.

Re: [PATCH v2 1/5] aspeed/wdt: Introduce a container for the MMIO region

On 10/18/21 15:26, Cédric Le Goater wrote: > On the AST2600, the 2nd watchdog timer can be controlled through the > FMC controller to disable the alternate boot function. Next changes > will map the WDT2 registers in the AST2600 FMC memory region. Add a > container on top of the register region for

Re: [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fab

Re: [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: Given the side effects they have, the csr instructions are realized as helpers. We extend this existing infrastructure for 128-bit sized csr. We have a slight issue with returning 128-bit values: we use the globals we added to support div/rem insns to t

Re: [PATCH v3 16/21] target/riscv: adding high part of some csrs

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: +/* Upper 64-bits of 128-bit CSRs */ +uint64_t mtvech; +uint64_t mscratchh; +uint64_t mepch; +uint64_t satph; +uint64_t mstatush; Needs adding to the same machine.c subsection as the gprs. Otherwise, Reviewed-by: Richard Hende

Re: [PATCH v3 15/21] target/riscv: support for 128-bit M extension

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: struct CPURISCVState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ +target_ulong hlpr[2]; /* scratch registers for 128-bit div/rem helpers */ We have something similar for s390x, but we ma

Re: plugins: Missing Store Exclusive Memory Accesses

On Oct 20 18:54, Alex Bennée wrote: > Have you got a test case you are using so I can try and replicate the > failure you are seeing? So far by inspection everything looks OK to me. I took some time today to put together a minimal(ish) reproducer using usermode. The source files used are below, I

Re: [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: +static bool gen_setcond_i128(TCGv rl, TCGv rh, + TCGv al, TCGv ah, + TCGv bl, TCGv bh, + TCGCond cond) +{ +switch (cond) { +case TCG_COND_EQ: +tcg_gen_s

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