Re: [PATCH v2 0/5] aspeed/smc: Improve support for the alternate boot function

And the FMC registers are just an alias to write to these watchdog 2 registers? If this is the same watchdog mapped into the FMC, I would say yes and the logic generate load/stores transactions on the AHB bus. Adding an address space for the WDT registers in the model is the closer we can get w

Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers

Le 20/10/2021 à 16:44, Richard Henderson a écrit : > On 10/19/21 2:47 AM, Frédéric Pétrot wrote: >> The upper 64-bit of the 128-bit registers have now a place inside >> the cpu state structure, and are created as globals for future use. >> >> Signed-off-by: Frédéric Pétrot >> Co-authored-by: Fabie

[PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function

From: Alistair Francis Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 1 - hw/riscv/microchip_pfsoc.c | 14 +- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h i

[PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 20 +--- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2d3a8ec405..8715cfe659 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -748,24 +748,6

[PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function

From: Alistair Francis Add a generic function that can create the PLIC strings. Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 25 + 2 files changed, 27 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/risc

[PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 14 +- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fc5790b8ce..0010b404ee 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@

[PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration

From: Alistair Francis Using a macro for the PLIC configuration doesn't make the code any easier to read. Instead it makes it harder to figure out what is going on, so let's remove it. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- include/hw/riscv/virt.h | 1 - hw/riscv/virt.c

Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store

On Fri, Oct 22, 2021 at 7:28 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 10/21/21 3:31 PM, Alistair Francis wrote: > > On Fri, Oct 22, 2021 at 2:30 AM wrote: > >> > >> From: Kito Cheng > >> > >> Signed-off-by: Kito Cheng > >> Signed-off-by: Chih-Min Chao > >> Signed-off-by

Re: [PATCH 8/8] x86-iommu: Fail early if vIOMMU specified after vfio-pci

On Thu, Oct 21, 2021 at 02:38:54PM +0200, Eric Auger wrote: > Hi Peter, > > On 10/21/21 12:42 PM, Peter Xu wrote: > > Scan the pci bus to make sure there's no vfio-pci device attached before > > vIOMMU > > is realized. > > > > Suggested-by: Igor Mammedov > > Signed-off-by: Peter Xu > > --- > >

Re: [PATCH 7/8] pci: Add pci_for_each_device_all()

Hi, Michael, On Thu, Oct 21, 2021 at 06:54:59AM -0400, Michael S. Tsirkin wrote: > > +typedef struct { > > +pci_bus_dev_fn fn; > > +void *opaque; > > +} pci_bus_dev_args; > > code style violation. CamelCase for structs pls. OK. > > +/* Call 'fn' for each pci device on the system */ > >

Re: [PATCH 01/31] target/loongarch: Upate the README for the softmmu.

在 2021年10月20日 02:56, Richard Henderson 写道: > On 10/19/21 12:34 AM, Xiaojuan Yang wrote: >> --- >> target/loongarch/README | 134 +++ >> target/loongarch/ramdisk | Bin 0 -> 3077952 bytes >> target/loongarch/vmlinux | Bin 0 -> 24565536 bytes >> 3 files c

Re: [PATCH 4/8] pci: Define pci_bus_fn/pci_bus_ret_fn type

On Thu, Oct 21, 2021 at 02:54:44PM +0200, Philippe Mathieu-Daudé wrote: > On 10/21/21 13:44, Philippe Mathieu-Daudé wrote: > > On 10/21/21 12:42, Peter Xu wrote: > >> The pci_bus_fn is similar to pci_bus_dev_fn that only takes a PCIBus* and > >> an > >> opaque. The pci_bus_ret_fn is similar to pc

Re: [PATCH 3/8] pci: Use pci_for_each_device_under_bus*()

On Thu, Oct 21, 2021 at 01:34:07PM +0200, Eric Auger wrote: > Hi Peter, > On 10/21/21 12:42 PM, Peter Xu wrote: > > Replace all the call sites of existing pci_for_each_device*() where the bus > > number is calculated from a PCIBus* already. It should avoid the lookup of > > the > > PCIBus again.

Re: [PATCH 1/8] pci: Define pci_bus_dev_fn type

On Thu, Oct 21, 2021 at 01:15:03PM +0200, Eric Auger wrote: > Hi Peter, > > On 10/21/21 12:42 PM, Peter Xu wrote: > > It's used in quite a few places of pci.c and also in the rest of the code > > base. > > Define such a hook so that it doesn't need to be defined all over the > > places. > > > >

Re: [PATCH 8/8] x86-iommu: Fail early if vIOMMU specified after vfio-pci

Hi, Alex, On Thu, Oct 21, 2021 at 04:30:39PM -0600, Alex Williamson wrote: > On Thu, 21 Oct 2021 18:42:59 +0800 > Peter Xu wrote: > > > Scan the pci bus to make sure there's no vfio-pci device attached before > > vIOMMU > > is realized. > > Sorry, I'm not onboard with this solution at all. >

Re: [PATCH 00/33] PowerISA v3.1 instruction batch

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst This patch series implements 56 new instructions for POWER10, moving 28 "old" instructions to decodetree along the way. The series is divided by facility as follows: - From patch 1 to 4: Floating-Point - From patch 5

Re: [PATCH v7 02/21] target/loongarch: Add core definition

Hi,Bob Thank you for your advice, I'll try. Thanks Xiaojuan, Yang 在 2021年10月22日 08:12, Bob Proulx 写道: > WANG Xuerui wrote: >> Song Gao wrote: >>> Account yangxiaoj...@loongson.cn It seems that she has been >>> blacklisted. Xiaojuan sent 31 e-mails, which were not displayed >>> since the 21st

Re: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs

On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote: diff --git a/target/riscv/csr_andes.c b/target/riscv/csr_andes.c new file mode 100644 index 00..8617f40483 --- /dev/null +++ b/target/riscv/csr_andes.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2021 Andes Technology Corp. + * SPDX-License-

Re: [PATCH v7 02/21] target/loongarch: Add core definition

WANG Xuerui wrote: > Song Gao wrote: > > Account yangxiaoj...@loongson.cn It seems that she has been > > blacklisted. Xiaojuan sent 31 e-mails, which were not displayed > > since the 21st one, people who don't have a CC can't read all the > > emails, and xiaojuan reply can't be in qemu-le...@nongn

Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()

On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote: riscv_csrrw() will be called by CSR handling helpers, which is the most suitable place for checking wheter a custom CSR is being accessed. If we're touching a custom CSR, invoke the registered handlers. Signed-off-by: Ruinland Chuan-Tzu Tsai

Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store

On 10/21/21 3:31 PM, Alistair Francis wrote: On Fri, Oct 22, 2021 at 2:30 AM wrote: From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson It doesn't look like this made it through to the list. I only see v3 on

Re: [PATCH v3 03/22] host-utils: introduce uabs64()

On 10/21/21 3:34 PM, Eduardo Habkost wrote: On Thu, Oct 21, 2021 at 4:04 PM Richard Henderson wrote: On 9/10/21 4:26 AM, Luis Pires wrote: Introduce uabs64(), a function that returns the absolute value of a 64-bit int as an unsigned value. This avoids the undefined behavior for common abs imp

Re: [PATCH v3 22/22] target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: -#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \ -static void gen_##name(DisasContext *ctx) \ -{ \ -TCGv_ptr rt, rs; \ -TCGv_i32 i32;

Re: [PATCH v15 0/8] RISC-V Pointer Masking implementation

On Wed, Oct 20, 2021 at 8:43 PM Alexey Baturo wrote: > > v14: > Addressed Richard's comments from previous series. > > v13: > Rebased QEMU and addressed Richard's comment. > > v12: > Updated function for adjusting address with pointer masking to allocate and > use temp register. > > v11: > Addres

Re: [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support

On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai wrote: > > Hi Alistair, Bin and all : > > Sorry for bumping this stale topic. > As our last discussion, I have removed Kconfigs and meson options. > The custom CSR logic is in-built by default and whether a custom CSR > is presented on the ac

Re: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs

On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai wrote: > > Add CSR bits definitions, CSR table and handler functions for Andes > AX25 and A25 CPUs. Also, enable the logic in a(x)25_cpu_init(). > > Signed-off-by: Ruinland Chuan-Tzu Tsai > --- > target/riscv/andes_cpu_bits.h | 129 +++

Re: [PATCH v3 21/22] target/ppc: Move dct{dp,qpq},dr{sp,dpq},dc{f,t}fix[q],dxex[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: -#define GEN_DFP_T_B_Rc(name) \ -static void gen_##name(DisasContext *ctx)\ -{\ -TCGv_ptr rt, rb; \ -if (unlikely(!ctx->fpu_enabled)) { \

Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()

On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai wrote: > > riscv_csrrw() will be called by CSR handling helpers, which is the > most suitable place for checking wheter a custom CSR is being accessed. > > If we're touching a custom CSR, invoke the registered handlers. > > Signed-off-by: Rui

Re: [PATCH v3 19/22] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: -#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2)\ -static void gen_##name(DisasContext *ctx) \ -{ \ -TCGv_ptr rt, rb; \ -TCGv_i32 u32_1, u32_2;

Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store

On Fri, Oct 22, 2021 at 2:30 AM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson It doesn't look like this made it through to the list. I only see v3 on patchew: https://patchew.org/QEMU/20

Re: [PATCH v3 03/22] host-utils: introduce uabs64()

On Thu, Oct 21, 2021 at 4:04 PM Richard Henderson wrote: > > On 9/10/21 4:26 AM, Luis Pires wrote: > > Introduce uabs64(), a function that returns the absolute value of > > a 64-bit int as an unsigned value. This avoids the undefined behavior > > for common abs implementations, where abs of the mo

Re: [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models

On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai wrote: > > Introduce A25 and AX25 CPU model designed by Andes Technology. > > Signed-off-by: Ruinland Chuan-Tzu Tsai Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 16 > target/riscv/cpu.h | 2 ++ >

Re: [PATCH 8/8] x86-iommu: Fail early if vIOMMU specified after vfio-pci

On Thu, 21 Oct 2021 18:42:59 +0800 Peter Xu wrote: > Scan the pci bus to make sure there's no vfio-pci device attached before > vIOMMU > is realized. Sorry, I'm not onboard with this solution at all. It would be really useful though if this commit log or a code comment described exactly the in

RE: [gdbstub] redirecting qemu console output to a debugger

> -Original Message- > From: Alex Bennée > Sent: Thursday, October 21, 2021 9:52 AM > To: Philippe Mathieu-Daudé > Cc: Sid Manning ; Marc-André Lureau > ; Paolo Bonzini ; > qemu-devel@nongnu.org > Subject: Re: [gdbstub] redirecting qemu console output to a debugger > > WARNING: This emai

Re: [PATCH v3 18/22] target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: -#define GEN_DFP_BF_A_B(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ -TCGv_ptr ra, rb; \ -if (unlikely(!ctx->fpu_enabled)) {

Re: [PATCH v3 20/22] target/ppc: Move dqua[q], drrnd[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: -#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \ -static void gen_##name(DisasContext *ctx)\ -{\ -TCGv_ptr rt, ra, rb; \ -TCGv_i32 i32;\

Re: [PULL 0/1] Block patches

On 10/21/21 10:41 AM, Stefan Hajnoczi wrote: The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-10-20 06:10:51 -0700) are available in the Git repository at: https://gitlab.com/stef

Re: [PATCH v3 17/22] target/ppc: Move d{add,sub,mul,div,iex}[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: -#define GEN_DFP_T_A_B_Rc(name) \ -static void gen_##name(DisasContext *ctx)\ -{\ -TCGv_ptr rd, ra, rb; \ -if (unlikely(!ctx->fpu_enabled)) { \

Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store

On Fri, Oct 22, 2021 at 2:30 AM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h| 1 + > target

Re: [PATCH v3 16/22] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

On 9/10/21 4:26 AM, Luis Pires wrote: +&Z22_bf_fra bf fra dm +@Z22_bf_fra .. bf:3 .. fra:5 dm:6 . . &Z22_bf_fra + +%z22_frap 17:4 !function=times_2 +@Z22_bf_frap.. bf:3 .. 0 dm:6 . . &Z22_bf_fra fra=%z22_frap How confusing. The

Re: [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function

On Thu, Oct 21, 2021 at 5:33 PM Bin Meng wrote: > > On Mon, Oct 18, 2021 at 10:39 AM Alistair Francis > wrote: > > > > From: Alistair Francis > > > > Signed-off-by: Alistair Francis > > --- > > hw/intc/sifive_plic.c | 10 -- > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > R

Re: [PATCH] multiboot: Use DMA instead port-based transfer

On Tuesday, October 19, 2021 6:45:44 PM CEST Paolo Bonzini wrote: > On my system (a relatively recent laptop) I get 15-20 MiB per second, > which is slow but not as slow as what you got. Out of curiosity, can > you test what you get with the following kernel patch? > > diff --git a/arch/x86/kvm

Re: [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines

On Wed, Oct 20, 2021 at 11:41 AM Bin Meng wrote: > > As of today, all RISC-V machines (except virt) are still using > memory_region_init_ram() > to initilize the sysytem RAM, which can't possibly handle vhost-user, and > can't > work as expected with '-numa node,memdev' options. > > Change to us

Re: [PATCH v3 12/22] target/ppc: Implement DCFFIXQQ

On 9/10/21 4:26 AM, Luis Pires wrote: +void helper_DCFFIXQQ(CPUPPCState *env, ppc_fprp_t *t, ppc_avr_t *b) +{ +struct PPC_DFP dfp; Space here after the variable declaration would help. +dfp_prepare_decimal128(&dfp, NULL, NULL, env); +decNumberFromInt128(&dfp.t, (uint64_t)b->VsrD(1

[PATCH v3 46/48] tcg/optimize: Propagate sign info for setcond

The result is either 0 or 1, which means that we have a 2 bit signed result, and thus 62 bits of sign. For clarity, use the smask_from_zmask function. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index d

Re: [PATCH v3 15/22] target/ppc: Implement DCTFIXQQ

On 9/10/21 4:26 AM, Luis Pires wrote: --- a/target/ppc/dfp_helper.c +++ b/target/ppc/dfp_helper.c @@ -51,6 +51,12 @@ static void set_dfp128(ppc_fprp_t *dfp, ppc_vsr_t *src) dfp[1].VsrD(0) = src->VsrD(1); } +static void set_dfp128_to_avr(ppc_avr_t *dst, ppc_vsr_t *src) +{ +dst->Vsr

[PATCH v3 48/48] tcg/optimize: Propagate sign info for shifting

For constant shifts, we can simply shift the s_mask. For variable shifts, we know that sar does not reduce the s_mask, which helps for sequences like ext32s_i64 t, in sar_i64 t, t, v ext32s_i64 out, t allowing the final extend to be eliminated. Signed-off-by: Richard Henderson

[PATCH v3 45/48] tcg/optimize: Propagate sign info for logical operations

Sign repetitions are perforce all identical, whether they are 1 or 0. Bitwise operations preserve the relative quantity of the repetitions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 + 1 file changed, 29 insertions(+

[PATCH v3 41/48] tcg/optimize: Sink commutative operand swapping into fold functions

Most of these are handled by creating a fold_const2_commutative to handle all of the binary operators. The rest were already handled on a case-by-case basis in the switch, and have their own fold function in which to place the call. We now have only one major switch on TCGOpcode. Signed-off-by:

Re: [PATCH v3 08/22] host-utils: add unit tests for divu128/divs128

On 9/10/21 4:26 AM, Luis Pires wrote: Signed-off-by: Luis Pires --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 +++ 2 files changed, 198 insertions(+) create mode 100644 tests/unit/test-div128.c Reviewed-by: Richard Henderson r~

Re: [PATCH v3 07/22] host-utils: add 128-bit quotient support to divu128/divs128

On 9/10/21 4:26 AM, Luis Pires wrote: These will be used to implement new decimal floating point instructions from Power ISA 3.1. A new argument, prem, was added to divu128/divs128 to receive the remainder, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires

[PATCH v3 47/48] tcg/optimize: Propagate sign info for bit counting

The results are generally 6 bit unsigned values, though the count leading and trailing bits may produce any value for a zero input. Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 64d3

[PATCH v3 42/48] tcg/optimize: Add more simplifications for orc

Two simplifications that were missing from before the split to fold functions, and are now easy to provide. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 92b35a8c3f..dc7744d41a 100644 --- a/tcg/opti

[PATCH v3 35/48] tcg/optimize: Split out fold_sub_to_neg

Even though there is only one user, place this more complex conversion into its own helper. Signed-off-by: Richard Henderson --- tcg/optimize.c | 84 -- 1 file changed, 47 insertions(+), 37 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c

[PATCH v3 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops

Rename to fold_addsub2. Use Int128 to implement the wider operation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 65 ++ 1 file changed, 44 insertions(+), 21 deletions(-) diff --git a/tcg/optimize.c b/

[PATCH v3 30/48] tcg/optimize: Split out fold_xx_to_i

Pull the "op r, a, a => movi r, 0" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 41 - 1 file changed, 24 insertions(+), 17 deletions(

[PATCH v3 44/48] tcg/optimize: Optimize sign extensions

Certain targets, like riscv, produce signed 32-bit results. This can lead to lots of redundant extensions as values are manipulated. Begin by tracking only the obvious sign-extensions, and converting them to simple copies when possible. Signed-off-by: Richard Henderson --- tcg/optimize.c | 129

[PATCH v3 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values

This "garbage" setting pre-dates the addition of the type changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64, and INDEX_op_extr{l,h}_i64_i32. So now we have a definitive points at which to adjust z_mask to eliminate such bits from the 32-bit operands. Signed-off-by: Richard Henderson -

[PATCH v3 37/48] tcg/optimize: Split out fold_ix_to_i

Pull the "op r, 0, b => movi r, 0" optimization into a function, and use it in fold_shift. Signed-off-by: Richard Henderson --- tcg/optimize.c | 28 ++-- 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index af26429175..6c1c

[PATCH v3 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies

Rename to fold_multiply2, and handle muls2_i32, mulu2_i64, and muls2_i64. Signed-off-by: Richard Henderson --- tcg/optimize.c | 44 +++- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f0086ee789..efd5f5

[PATCH v3 26/48] tcg/optimize: Split out fold_count_zeros

Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 ++-- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9758d83e3e..c54f839434 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -873,6 +873,20 @@ static bool

[PATCH v3 34/48] tcg/optimize: Split out fold_to_not

Split out the conditional conversion from a more complex logical operation to a simple NOT. Create a couple more helpers to make this easy for the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 154 +++-- 1 file c

[PATCH v3 38/48] tcg/optimize: Split out fold_masks

Move all of the known-zero optimizations into the per-opcode functions. Use fold_masks when there is a possibility of the result being determined, and simply set ctx->z_mask otherwise. Signed-off-by: Richard Henderson --- tcg/optimize.c | 545 ++--- 1

[PATCH v3 29/48] tcg/optimize: Split out fold_mov

This is the final entry in the main switch that was in a different form. After this, we have the option to convert the switch into a function dispatch table. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++- 1 file changed

[PATCH v3 28/48] tcg/optimize: Split out fold_dup, fold_dup2

Signed-off-by: Richard Henderson --- tcg/optimize.c | 53 +- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 77b31680f1..2d626c604a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -915,6 +915

[PATCH v3 24/48] tcg/optimize: Split out fold_extract, fold_sextract

Signed-off-by: Richard Henderson --- tcg/optimize.c | 48 ++-- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 885380bb22..3fffc5b200 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -883,6 +883,1

[PATCH v3 22/48] tcg/optimize: Split out fold_movcond

Signed-off-by: Richard Henderson --- tcg/optimize.c | 56 -- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index eb6f1581ac..ed5a304089 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -917,6 +917

[PATCH v3 36/48] tcg/optimize: Split out fold_xi_to_x

Pull the "op r, a, i => mov r, a" optimization into a function, and use them int the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 60 +- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/tcg/opt

[PATCH v3 31/48] tcg/optimize: Split out fold_xx_to_x

Pull the "op r, a, a => mov r, a" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-)

[PATCH v3 17/48] tcg/optimize: Split out fold_brcond2

Reduce some code duplication by folding the NE and EQ cases. Signed-off-by: Richard Henderson --- tcg/optimize.c | 159 + 1 file changed, 81 insertions(+), 78 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 0eaa0127f3..61a6221ad2 1

[PATCH v3 33/48] tcg/optimize: Add type to OptContext

Compute the type of the operation early. There are at least 4 places that used a def->flags ladder to determine the type of the operation being optimized. There were two places that assumed !TCG_OPF_64BIT means TCG_TYPE_I32, and so could potentially compute incorrect results for vector operations

[PATCH v3 21/48] tcg/optimize: Split out fold_addsub2_i32

Add two additional helpers, fold_add2_i32 and fold_sub2_i32 which will not be simple wrappers forever. Signed-off-by: Richard Henderson --- tcg/optimize.c | 70 +++--- 1 file changed, 44 insertions(+), 26 deletions(-) diff --git a/tcg/optimize.c b/tcg

[PATCH v3 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*

Return -1 instead of 2 for failure. This us to use comparisons against 0 for all cases. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 + 1 file changed, 74 insertions(+), 71 deletions(-) diff --git a/tcg/optimi

[PATCH v3 27/48] tcg/optimize: Split out fold_bswap

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c54f839434..77b31680f1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c

[PATCH v3 20/48] tcg/optimize: Split out fold_mulu2_i32

Signed-off-by: Richard Henderson --- tcg/optimize.c | 37 + 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2086e894c6..142f445cb1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -889,6 +889,24 @@ static

[PATCH v3 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi}

This will allow callers to tail call to these functions and return true indicating processing complete. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/t

[PATCH v3 32/48] tcg/optimize: Split out fold_xi_to_i

Pull the "op r, a, 0 => movi r, 0" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 +++- 1 file changed, 15 insertions(+), 17 deletions(-) diff

[PATCH v3 23/48] tcg/optimize: Split out fold_extract2

Signed-off-by: Richard Henderson --- tcg/optimize.c | 39 ++- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index ed5a304089..885380bb22 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -883,6 +883,25 @@ stat

[PATCH v3 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals

Rather than try to keep these up-to-date across folding, re-read nb_oargs at the end, after re-reading the opcode. A couple of asserts need dropping, but that will take care of itself as we split the function further. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Hende

[PATCH v3 25/48] tcg/optimize: Split out fold_deposit

Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 3fffc5b200..9758d83e3e 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -878,6 +878,18 @@ static bool fold_c

[PATCH v3 16/48] tcg/optimize: Split out fold_setcond2

Reduce some code duplication by folding the NE and EQ cases. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 - 1 file changed, 72 insertions(+), 73 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index

[PATCH v3 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}

This puts the separate mb optimization into the same framework as the others. While fold_qemu_{ld,st} are currently identical, that won't last as more code gets moved. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 89 +

[PATCH v3 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface

Adjust the interface to take the OptContext parameter instead of TCGContext or both. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 67 +- 1 file changed, 34 insertions(+), 33 deletions(-)

[PATCH v3 19/48] tcg/optimize: Split out fold_setcond

Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9059e917cf..2086e894c6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -933,6 +933,17

[PATCH v3 18/48] tcg/optimize: Split out fold_brcond

Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 61a6221ad2..9059e917cf 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -71

[PATCH v3 12/48] tcg/optimize: Split out finish_folding

Copy z_mask into OptContext, for writeback to the first output within the new function. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 49 + 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/tcg/optimiz

[PATCH v3 13/48] tcg/optimize: Use a boolean to avoid a mass of continues

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 368457f4a2..699476e2f1 100644 --- a/tcg/optimize.c +++ b/tcg/optimiz

[PATCH v3 08/48] tcg/optimize: Split out fold_call

Calls are special in that they have a variable number of arguments, and need to be able to clobber globals. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 63 -- 1 file changed, 41 insertion

[PATCH v3 06/48] tcg/optimize: Split out init_arguments

There was no real reason for calls to have separate code here. Unify init for calls vs non-calls using the call path, which handles TCG_CALL_DUMMY_ARG. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 25

[PATCH v3 01/48] tcg/optimize: Rename "mask" to "z_mask"

Prepare for tracking different masks by renaming this one. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 142 + 1 file changed, 72 insertions(+), 70 del

[PATCH v3 15/48] tcg/optimize: Split out fold_const{1,2}

Split out a whole bunch of placeholder functions, which are currently identical. That won't last as more code gets moved. Use CASE_32_64_VEC for some logical operators that previously missed the addition of vectors. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c |

[PATCH v3 07/48] tcg/optimize: Split out copy_propagate

Continue splitting tcg_optimize. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c

[PATCH v3 03/48] tcg/optimize: Remove do_default label

Break the final cleanup clause out of the main switch statement. When fully folding an opcode to mov/movi, use "continue" to process the next opcode, else break to fall into the final cleanup. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c

[PATCH v3 05/48] tcg/optimize: Move prev_mb into OptContext

This will expose the variable to subroutines that will be broken out of tcg_optimize. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimi

[PATCH v3 00/48] tcg: optimize redundant sign extensions

Currently, we have support for optimizing redundant zero extensions, which I think was done with x86 and aarch64 in mind, which zero-extend all 32-bit operations into the 64-bit register. But targets like Alpha, MIPS, and RISC-V do sign-extensions instead. But before that, split the quite massive

[PATCH v3 02/48] tcg/optimize: Split out OptContext

Provide what will become a larger context for splitting the very large tcg_optimize function. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 77 ++ 1 file changed, 40 insertions(+), 37 delet

Re: [PATCH v4 6/6] vfio: defer to commit kvm irq routing when enable msi/msix

On Thu, 14 Oct 2021 08:48:52 +0800 "Longpeng(Mike)" wrote: > In migration resume phase, all unmasked msix vectors need to be > setup when loading the VF state. However, the setup operation would > take longer if the VM has more VFs and each VF has more unmasked > vectors. > > The hot spot is kvm

Re: plugins: Missing Store Exclusive Memory Accesses

On Oct 21 13:28, Alex Bennée wrote: > It's a bit clearer if you use the contrib/execlog plugin: > > ./qemu-aarch64 -plugin contrib/plugins/libexeclog.so -d plugin > ./tests/tcg/aarch64-linux-user/stxp > > 0, 0x400910, 0xf9800011, "prfm pstl1strm, [x0] > 0, 0x400914, 0xc87f4410, "ldxp x16,

Re: [PATCH v3 02/22] host-utils: fix missing zero-extension in divs128

On 9/10/21 4:26 AM, Luis Pires wrote: *plow (lower 64 bits of the dividend) is passed into divs128() as a signed 64-bit integer. When building an __int128_t from it, it must be zero-extended, instead of sign-extended. Suggested-by: Richard Henderson Signed-off-by: Luis Pires --- include/qemu/h

Re: [PATCH v3 06/22] host-utils: move udiv_qrnnd() to host-utils

On 9/10/21 4:26 AM, Luis Pires wrote: Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires --- include/fpu/softfloat-macros.h | 82 -- include/qemu/host-utils.h | 81 ++

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