On 11/11/21 07:18, Yang Zhong wrote:
> On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote:
>> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote:
>>> Add the SGXEPCSection list into SGXInfo to show the multiple
>>> SGX EPC sections detailed info, not the total size like before.
>>>
Hi,
> Given it's a bugfix, and given that I hear through internal channels
> that QE results so far have been encouraging, I am inclined to bite the
> bullet and merge this for -rc1.
Fine with me.
> I don't think this conflicts with Julia's patches as users can still
> disable ACPI hotplug int
On 11/11/21 07:38, Jason Wang wrote:
> We used to access packed descriptor flags via
> address_space_{write|read}_cached(). When we hit the cache, memcpy()
> is used which is not an atomic operation which may lead a wrong value
> is read or wrote.
>
> So this patch switches to use virito_{stw|lduw
On 11/11/21 07:38, Jason Wang wrote:
> We used to access packed descriptor event and off_wrap via
> address_space_{write|read}_cached(). When we hit the cache, memcpy()
> is used which is not atomic which may lead a wrong value to be read or
> wrote.
>
> This patch fixes this by switching to use
>
From: Greg Kurz
The drain_rcu_call() function can be blocked as long as an RCU reader
stays in a read-side critical section. This is typically what happens
when a TCG vCPU is executing a busy loop. It can deadlock the QEMU
monitor as reported in https://gitlab.com/qemu-project/qemu/-/issues/650 .
From: Greg Kurz
A TCG vCPU doing a busy loop systematicaly hangs the QEMU monitor
if the user passes 'device_add' without argument. This is because
drain_cpu_all() which is called from qmp_device_add() cannot return
if readers don't exit read-side critical sections. That is typically
what busy-lo
Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case, so that enclave
memory is included in the output of "info numa" instead of crashing
the monitor.
Fixes: a7c565a941 ("sgx-epc: Add the fill_device_info() callback support",
2021-09-30)
Signed-off-by: Paolo Bonzini
---
hw/core/numa.c | 7 +++
1 fi
On 11/10/21 17:55, Eric Blake wrote:
The QMP interface show:
(QEMU) query-sgx
{"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
[{"node": 0, "size": 67108864}, {"node": 1, "size": 29360128}], "flc": true}}
(QEMU) query-sgx-capabilities
{"return": {"sgx": true, "sgx2": true, "sgx
The following changes since commit 114f3c8cc427333dbae331dfd2ecae64676b087e:
Merge remote-tracking branch 'remotes/philmd/tags/avocado-20211108' into
staging (2021-11-08 18:50:09 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to
From: Yang Zhong
For bare-metal SGX on real hardware, the hardware provides guarantees
SGX state at reboot. For instance, all pages start out uninitialized.
The vepc driver provides a similar guarantee today for freshly-opened
vepc instances, but guests such as Windows expect all pages to be in
The device is created by the machine based on the sgx-epc property.
It should not be created by users.
Reported-by: Thomas Huth
Signed-off-by: Paolo Bonzini
---
hw/i386/sgx-epc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c
index 55e2217eae..e508827e
On 11/10/21 07:42, Janosch Frank wrote:
> On 11/9/21 21:56, Collin Walling wrote:
>> The CPNC portion of the diag 318 data is erroneously reset during an
>> initial CPU reset caused by SIGP. Let's go ahead and relocate the
>> diag318_info field within the CPUS390XState struct such that it is
>> onl
We used to access packed descriptor event and off_wrap via
address_space_{write|read}_cached(). When we hit the cache, memcpy()
is used which is not atomic which may lead a wrong value to be read or
wrote.
This patch fixes this by switching to use
virito_{stw|lduw}_phys_cached() to make sure the a
We used to access packed descriptor flags via
address_space_{write|read}_cached(). When we hit the cache, memcpy()
is used which is not an atomic operation which may lead a wrong value
is read or wrote.
So this patch switches to use virito_{stw|lduw}_phys_cached() to make
sure the aceess is atomic
On Wed, Nov 10, 2021 at 05:07:40PM +0100, Paolo Bonzini wrote:
> On 11/10/21 13:56, Yang Zhong wrote:
> > Paolo, thanks!
> >
> > No other maintainers to review numa patches, so i will send the numa
> > patches again? thanks!
>
> The patch look good, but they were sent too close to the 6.2 re
On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote:
> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote:
> > Add the SGXEPCSection list into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not the total size like before.
> > This patch can enable numa support for '
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 ++---
1 file changed
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8f8f170768..43eaa6c710 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -553,15 +553,14 @@ static RISCVException write
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1a7ee
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b48c7c346c..5f35217f7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index f5aabd5263..41c7c88904 100644
--- a/
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 8 +---
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index
Paolo Bonzini writes:
>> On 11/3/21 09:02, Markus Armbruster wrote:
>>> I wonder whether we really have to step through three states
>>>
>>> x-exit-preconfig cont
>>> preconfig ---> pre run ---> run
>>>
>>> and not two
>>>
>>> cont
>>> pre run ---> run
>
> Device
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c| 3 +--
target/riscv/csr.c | 13 -
target/riscv/machine.c | 1 +
target/riscv/vector_helper.c | 3 ++-
5 files ch
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rva.c.inc | 9 +++--
target/riscv/insn_trans/trans_rvd.c.inc | 19 ++---
target/risc
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 52ce670cbe..b48c7c346c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURI
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vect
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 4
target/riscv/cpu_helper.c | 43 +++
target/riscv/csr.c| 19 +
target/riscv/machine.c| 10 +
5 files changed, 77 insertions(+
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/gdbstub.c | 71 +++---
1 file changed, 52 insertions(+), 19 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 23429179e2..8d0f9139d7 100644
--- a/target/ri
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h| 3 ++-
target/riscv/cpu_helper.c | 25 +++--
target/riscv/t
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..74c0b788fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1445,6 +1445,9 @@ static bool c
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/op_helper.c| 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/ris
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c| 22 +++---
target/riscv/cp
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei
---
target/riscv/translate.c | 32
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/target/riscv/translate.c b/targe
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/translate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translat
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-
target/riscv/op_helper.c
In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
The patch set v3 mainly address Richard comments on v2.
Patch 1,2,3,5,6,16,17 have been reviewed.
v3:
Merge gen_pm_adjust_address into a canonical address functio
On Wed, 10 Nov 2021, Igor Mammedov wrote:
> From: Julia Suvorova
>
> Prepare for changing the _OSC method in q35 DSDT.
>
> Signed-off-by: Julia Suvorova
> Signed-off-by: Igor Mammedov
Acked-by: Ani Sinha
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 16
> 1 file
On Wed, 10 Nov 2021, Igor Mammedov wrote:
> From: Julia Suvorova
>
> The changes are the result of
> 'hw/i386/acpi-build: Deny control on PCIe Native Hot-Plug in _OSC'
> and listed here:
>
> Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
> {
>
On Wed, 10 Nov 2021, Igor Mammedov wrote:
> From: Julia Suvorova
>
> There are two ways to enable ACPI PCI Hot-plug:
>
> * Disable the Hot-plug Capable bit on PCIe slots.
>
> This was the first approach which led to regression [1-2], as
> I/O space for a port is allocated only when it
On 2021/11/10 下午10:40, Richard Henderson wrote:
On 11/10/21 2:44 PM, LIU Zhiwei wrote:
I suspect the extend should come before the pointer mask and not
after, but this is is a weakness in the current RVJ spec that it
does not specify how the extension interacts with UXL. (The reverse
ordering
在 2021/11/8 下午6:53, Stefan Hajnoczi 写道:
On Fri, Nov 05, 2021 at 12:48:17AM +0800, Cindy Lu wrote:
these patches add the support for configure interrupt
These codes are all tested in vp-vdpa (support configure interrupt)
vdpa_sim (not support configure interrupt), virtio tap device
test in vi
On Wed, 10 Nov 2021, Igor Mammedov wrote:
> Mark property as experimental/internal adding 'x-' prefix.
>
> Property was introduced in 6.1 and it should have provided
> ability to turn on native PCIE hotplug on port even when
> ACPI PCI hotplug is in use is user explicitly sets property
> on CLI
This patch make filters and colo-compare module support vnet_hdr by
default. And also support -device non-virtio-net(like e1000.).
Because when enabled the support will make the vnet_hdr_len field
become must-delivery part of filter transfer protocol(even 0 in use
-device e1000). It fully guarantee
> -Original Message-
> From: Jason Wang
> Sent: Thursday, November 11, 2021 10:50 AM
> To: Markus Armbruster
> Cc: Zhang, Chen ; qemu-dev de...@nongnu.org>; Li Zhijian
> Subject: Re: [PATCH] net/filter: Enable the vnet_hdr_support by default
>
> On Wed, Nov 10, 2021 at 4:36 PM Markus
On Wed, Nov 10, 2021 at 4:36 PM Markus Armbruster wrote:
>
> "Zhang, Chen" writes:
>
> >> -Original Message-
> >> From: Markus Armbruster
> >> Sent: Wednesday, November 10, 2021 2:21 PM
> >> To: Zhang, Chen
> >> Cc: Jason Wang ; qemu-dev >> de...@nongnu.org>; Li Zhijian
> >> Subject:
Checkpatch.pl reports errors like below for commit 9e8e393bb7.
Let's fix it with a simpler format.
ERROR: space required after that close brace '}'
+SMPTestData *data = &(SMPTestData){{ }};
Fixes: 9e8e393bb7 ("tests/unit: Add an unit test for smp parsing")
Signed-off-by: Yanan Wang
---
tests
Currently, the name of the tested machine in the expected error
messages is hardcoded as "(null)" which is not good, because the
actual generated name of the machine maybe "(null)" or "(NULL)"
which will cause an unexpected test failure in some CI platforms.
So let's rename the tested machine with
Hi,
There are two fixes for tests/unit/test-smp-parse.c (v2).
The first one makes an unified name for the tested machine, which
will make the test more stable and resolve the CI failures in [1].
The second one fixes a check-patch complain for commit 9e8e393bb7.
[1] https://cirrus-ci.com/task/5823
> -Original Message-
> From: Rao, Lei
> Sent: Thursday, November 11, 2021 10:12 AM
> To: Zhang, Chen ;
> zhang.zhanghaili...@huawei.com; quint...@redhat.com;
> dgilb...@redhat.com
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATCH v2] Fixed a QEMU hang when guest poweroff in COLO
> -Original Message-
> From: Rao, Lei
> Sent: Wednesday, November 10, 2021 4:38 PM
> To: Zhang, Chen ;
> zhang.zhanghaili...@huawei.com; quint...@redhat.com;
> dgilb...@redhat.com
> Cc: qemu-devel@nongnu.org; Rao, Lei
> Subject: [PATCH 2/2] migration/ram.c: Remove the qemu_mutex_lock i
From: "Rao, Lei"
When the PVM guest poweroff, the COLO thread may wait a semaphore
in colo_process_checkpoint().So, we should wake up the COLO thread
before migration shutdown.
Signed-off-by: Lei Rao
---
include/migration/colo.h | 1 +
migration/colo.c | 20
migra
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 349 +
hw/acpi/meson.build | 1 +
hw/loongarc
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/ls3a5000_virt.c | 41
include/hw/loongarch/loongarch.h | 2 ++
3 files changed, 44 insertions(+)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ls3a5000_virt.c | 81
include/hw/loongarch/loongarch.h | 5 ++
2 files changed, 86 insertions(+)
diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c
index 85c8466d75.
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-31.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 8
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 4 +++
hw/loongarch/fw_cfg.c| 33 ++
hw/loongarch/fw_cfg.h| 15
hw/loongarch/ls3a5000_virt.c | 60 +---
hw/loongarch/meson
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 73 +
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 570 +
hw/intc/meson.build| 1 +
hw/loongarch/Kconfig
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ls3a5000_virt.c | 64
include/hw/pci-host/ls7a.h | 4 +++
2 files changed, 68 insertions(+)
diff --git a/hw/loongarch/ls3a5000_virt
This is a model of the PCIe Host Bridge found on a Loongson-5000
processor. It includes a interrupt controller, some interface for
pci and nonpci devices we only emulate part devices for tcg mode.
It support for MSI and MSIX interrupt sources.
For more detailed info about ls7a1000 you can see the
1.From Loongson-3A5000 4 cpus belongs to 1 node.
Now support mostly 4 nodes 16 cpus.
2.Different nodes access different address spaces. All
memory access should be handle correctly even nodes
not assigned memory by numa parameters in the command
line.
Signed-off-by: Xiaojuan Yang
Signed-o
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ipi.c | 144 +++
hw/loongarch/ls3a5000_virt.c | 1 +
hw/loongarch/meson.build | 2 +-
include/hw/loongarch/gipi.h
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 43 +++
gdb-xml/loongarch-fpu64.xml | 57 +++
target/loongarch/cpu.c | 9 +++
target/loongarch/gdbs
Use possible_cpus for storing possible topology info
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/acpi-build.c| 16 ++--
hw/loongarch/ls3a5000_virt.c | 35 ++-
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 283
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/ls3a5000_virt.c | 3 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c| 323 +++
hw/rtc/meson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/disas.c | 86
1 file changed, 86 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 1501462991..65aa0443bd 100644
--- a/target/loongarch/disas.c
+
This patch Add loongarch interrupt and exception handle.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 279 +
1 file changed, 279 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 7db6e21
LoongArch is a new RISC ISA, support 32bit mode
or 64bit mode. Now we only add 64bit support.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3 +
confi
This patch introduces basic TLB interfaces.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-param.h | 3 +
target/loongarch/cpu.c| 36
target/loongarch/cpu.h| 57 ++
target/loongarch/internals.h | 7 +
target/loongarch/machine.c
This patch introduces all possible exceptions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 13 +
target/loongarch/cpu.h | 17 +++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loong
Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
Loongson-3A5000 and ls7a form a legacy model and extended model irq
hierarchy.Tcg mode emulate a simplified extended model which
has no Legacy I/O Interrupt Controller(LIOINTC) and LPC.
e.g:
|+-++-+ +---
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++
target/loongarch/op_helper.c | 4 +++
target/loongarch
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 2 +
target/loongarch/helper.h| 4 +
target/loongarch/insn_trans/trans_core.c.inc | 62 +++
target/loon
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h| 8 +
target/loongarch/insn_trans/trans_core.c.inc | 71 +++
target/loongarch/insns.decode|
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 334 +
target/loongarch/cpu.c | 12 ++
target/loongarch/cpu.h | 127 ++
3 f
This patch introduces qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 28
2 files changed, 32 insertions(+), 2 deletions(-)
This includes:
- CSRRD
- CSRWR
- CSRXCHG
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/csr_helper.c| 322 ++
target/loongarch/helper.h| 11 +
target/loongarch/insn_trans/trans_core.c.inc | 437
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/README | 20
1 file changed, 20 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index 09f809cf80..6f64bde22f 100644
--- a/target/l
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 11 ++
target/loongarch/meson.build | 1 +
target/loongarch/stabletimer.c | 70 ++
3 files changed, 82 insertions(+)
create mode 100644 target/loongarch/stabletimer.c
Sorry only part of the v2 patch succeed. I consulted GNU sysadmin,
He said our mail server was getting temporarily banned by fail2ban. Now the ban
was removed. I resend the v2 series patch. For uefi is preparing to submit to
the community only uefi binary can be provided now. All of the series patc
This patch introduces vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 4 +
target/loongarch/internals.h | 4 +
target/loongarch/machine.c | 154 +++
target/loongarch/meson.build | 6 ++
4 files
Add capability to enable and parse security context as sent by client
and put into fuse_req. Filesystems now can get security context from
request and set it on files during creation.
Signed-off-by: Vivek Goyal
---
tools/virtiofsd/fuse_common.h | 5 ++
tools/virtiofsd/fuse_i.h| 7 +++
Provide an option "-o security_label/no_security_label" to enable/disable
security label functionality. By default these are turned off.
If enabled, server will indicate to client that it is capable of handling
one security label during file creation. Typically this is expected to
be a SELinux lab
Hi,
This is V3 of the patches. I posted V2 here.
https://lore.kernel.org/qemu-devel/20211014153126.575173-1-vgo...@redhat.com/
Kernel patches are not upstream yet. So header files will need to be
updated once kernel patches are merged. I posted V3 of kernel patches
here.
https://lore.kernel.org
These are just header file changes which should show up in qemu if
corresponding kernel changes get merged.
Signed-off-by: Vivek Goyal
---
include/standard-headers/linux/fuse.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/standard-headers/linux/
If guest and host policies can't work with each other, then guest security
context (selinux label) needs to be set into an xattr. Say remap guest
security.selinux xattr to trusted.virtiofs.security.selinux.
That means setting "fscreate" is not going to help as that's ony useful
for security.selinu
Move core file creation bits in a separate function. Soon this is going
to get more complex as file creation need to set security context also.
And there will be multiple modes of file creation in next patch.
Signed-off-by: Vivek Goyal
---
tools/virtiofsd/passthrough_ll.c | 36 ++
This patch adds support to set /proc/thread-self/attr/fscreate before
file creation. It is set to a value as sent by client. This will allow
for atomic creation of security context on files w.r.t file creation.
This is primarily useful when either there is no SELinux enabled on
host or host and gu
On Wed, Nov 10, 2021 at 10:04 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/10/21 5:31 PM, Warner Losh wrote:
> > Move linux-user/safe-syscall.S to common-user/common-safe-syscall.S and
> > replace it with a #include "common-safe-syscall.S" so that bsd-user can
> > also use i
On Wed, Nov 10, 2021 at 10:00 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/10/21 5:31 PM, Warner Losh wrote:
> > Signed-off-by: Warner Losh
> > ---
> > common-user/host/mips/safe-syscall.inc.S | 1 +
> > 1 file changed, 1 insertion(+)
> > create mode 100644 common-user
On Wed, Nov 10, 2021 at 9:59 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/10/21 5:31 PM, Warner Losh wrote:
> > All the *-users generally use the Linux style of negative return codes
> > for errno. FreeBSD returns errno, not -errno. Add ifdefs for FreeBSD to
> > make the adj
On Wed, Nov 10, 2021 at 9:42 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/10/21 5:31 PM, Warner Losh wrote:
> > +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc)
> > +{
> > +#ifdef __arch64__
> > +uc->uc_mcontext.mc_gregs[MC_PC] = pc;
> > +#else
> > +
On Tue, Nov 02, 2021 at 07:25:25AM -0400, Michael S. Tsirkin wrote:
> On Tue, Nov 02, 2021 at 09:51:35AM +0100, Philippe Mathieu-Daudé wrote:
> > On 10/26/21 17:11, Eduardo Habkost wrote:
> > > The i440fx and Q35 machine types are both hardcoded to use the
> > > legacy SMBIOS 2.1 (32-bit) entry poi
On 11/3/21 09:02, Markus Armbruster wrote:
I wonder whether we really have to step through three states
x-exit-preconfig cont
preconfig ---> pre run ---> run
and not two
cont
pre run ---> run
Devices would be hotplugged between x-exit-preconfig and cont, and
From: Julia Suvorova
The changes are the result of
'hw/i386/acpi-build: Deny control on PCIe Native Hot-Plug in _OSC'
and listed here:
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
From: Julia Suvorova
There are two ways to enable ACPI PCI Hot-plug:
* Disable the Hot-plug Capable bit on PCIe slots.
This was the first approach which led to regression [1-2], as
I/O space for a port is allocated only when it is hot-pluggable,
which is determined by HPC bit.
Mark property as experimental/internal adding 'x-' prefix.
Property was introduced in 6.1 and it should have provided
ability to turn on native PCIE hotplug on port even when
ACPI PCI hotplug is in use is user explicitly sets property
on CLI. However that never worked since slot is wired to
ACPI h
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