To ensure you can do everything with QMP, the CLI should wrap around
QMP, like HMP should.
This commit does that in the stupidest way I can think of: each CLI
argument is parsed as QMP command, and fed to the QMP machinery.
Errors are reported, return values thrown away.
This is of course *bad*
The previous commit demonstrated how you can interleave QMP-over-CLI
with startup. We want the same for real QMP.
QMP-over-CLI starts in phase @no-machine, and may advance the phase.
We then advance to phase @machine-ready, and enter the main loop, and
real QMP becomes available.
If we skip
This is a straightforward QMP wrapper around qemu_until_phase().
Useless right now, because by the time you can execute QMP, we're
already in phase @machine-ready, and all you can do with the command
is "advance" to that same phase.
Its error message is RFC-qwality.
Signed-off-by: Markus
qemu-system-FOO starts up like this:
0. Basic, configuration-independent initialization
1. Parse and partially process CLI left to right
2. Startup with the remaining CLI processing mixed in
With -preconfig, some of this is delayed until QMP command
x-exit-preconfig.
3. Run main loop
These patches are meant to back the memo "Redesign of QEMU startup &
initial configuration" I just posted. Read that first, please.
My running example for initial configuration via QMP is cold plug. It
works at the end of the series.
I'm taking a number of shortcuts:
* I hack up
My axing of the CLI also axed the (moderately complicated) code that
posts a request to the board to create a VGA device. Hardcode such a
request, to facilitate manual testing.
Signed-off-by: Markus Armbruster
---
softmmu/vl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/softmmu/vl.c
A later patch will want to use qemu_until_phase() to advance from one
arbitrary phase to another. The previous commit implement advancing
from arbitrary phase to PHASE_MACHINE_READY. This one implements
advancing to a phase given as argument.
Signed-off-by: Markus Armbruster
---
softmmu/vl.c
We bootstrap QMP with the CLI, but the CLI is (temporarily) gone.
Hardcode a QMP monitor on stdio until we get it back.
Signed-off-by: Markus Armbruster
---
softmmu/vl.c | 16
1 file changed, 16 insertions(+)
diff --git a/softmmu/vl.c b/softmmu/vl.c
index
A later patch will want to use qemu_until_phase() to advance from one
arbitrary phase to another. Implement advancing from arbitrary phase
to PHASE_MACHINE_READY.
Indentation is intentionally off to minimize diffs. It's RFC :)
Signed-off-by: Markus Armbruster
---
softmmu/vl.c | 19
I'd like to use device cold plug as an example for how how the user
can now interleave CLI with startup. Doesn't work, because only
commands with 'allow-preconfig': true are available before phase
@machine-ready, and device_add isn't. Instead of changing just
device_add, this hack allows all
The startup code is split between qemu_init() and
qmp_x_exit_preconfig(). Cutting off the CLI leaves the QMP command
useless. Drop it, and inline the startup code back into qemu_init().
I'm going to provide more general replacement shortly.
Signed-off-by: Markus Armbruster
---
qapi/misc.json
This loses a hidden bit of CLI that evaded the axe murderer: picking
the default accelerator based on argv[0].
Signed-off-by: Markus Armbruster
---
include/hw/qdev-core.h | 1 +
hw/core/qdev.c | 5 +
softmmu/vl.c | 16
3 files changed, 18 insertions(+),
= Motivation =
QEMU startup and initial configuration were designed many years ago for
a much, much simpler QEMU. They have since changed beyond recognition
to adapt to new needs. There was no real redesign. Adaption to new
needs has become more and more difficult. A recent example for
On Tue, Nov 16, 2021 at 1:40 PM Daniel P. Berrangé wrote:
>
> On Tue, Nov 16, 2021 at 05:34:50PM +0100, Juan Quintela wrote:
> > Daniel P. Berrangé wrote:
> >
> > >>
> > >> if (params->zerocopy &&
> > >> (params->parameters.multifd_compression !=
> > >> MULTIFD_COMPRESSION_NONE ||
>
On Tue, Nov 16, 2021 at 1:35 PM Daniel P. Berrangé wrote:
>
> On Tue, Nov 16, 2021 at 04:17:47PM +, Daniel P. Berrangé wrote:
> > On Tue, Nov 16, 2021 at 05:08:06PM +0100, Juan Quintela wrote:
> > > Leonardo Bras wrote:
> > > > Implement zerocopy on nocomp_send_write(), by making use of
On Tue, Nov 16, 2021 at 1:08 PM Juan Quintela wrote:
>
> Leonardo Bras wrote:
> > Implement zerocopy on nocomp_send_write(), by making use of QIOChannel
> > zerocopy interface.
> >
> > Change multifd_send_sync_main() so it can distinguish each iteration sync
> > from
> > the setup and the
Hello Leonardo,
On 11/23/21 13:10, lagar...@linux.ibm.com wrote:
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
It seems that POWER10 was renamed to Power10 but not POWER9. And :
https://en.wikipedia.org/wiki/Power9 redirects to POWER9
https://en.wikipedia.org/wiki/POWER10
The following changes since commit 682aa69b1f4dd5f2905a94066fa4c853adc33251:
Update version for v6.2.0-rc3 release (2021-12-01 07:20:06 +0100)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/ide-pull-request
for you to fetch changes up to
From: Philippe Mathieu-Daudé
We are going to re-use this code in the next commit,
so extract it as a new blk_create_empty_drive() function.
Inspired-by: Hanna Reitz
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20211124161536.631563-2-phi...@redhat.com
Signed-off-by: John Snow
---
On Wed, Dec 01, 2021 at 12:17:30PM -0300, Daniel Henrique Barboza wrote:
> The PMU is already counting cycles by calculating time elapsed in
> nanoseconds. Counting instructions is a different matter and requires
> another approach.
>
> This patch adds the capability of counting completed
On Sat, Nov 27, 2021 at 1:08 AM Igor Mammedov wrote:
>
> It's hardly 6.2 material
We introduced the x-hotplug etc property with 6.2. I wanted to make
sure that people understand that the x- prefix indicates that this is
experimental stuff. We had enough mess with this already.
>
> On Fri, 26
Sorry, resending with correct indentation and quoting.
On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
01.12.2021 12:48, Rao, Lei wrote:
-Original Message-
From: Daniel P. Berrangé
Sent: Wednesday, December 1, 2021 5:11 PM
To: Rao, Lei
Cc: Zhang, Chen ;
Hello Markus,
On Fri, Nov 12, 2021 at 9:01 AM Markus Armbruster wrote:
>
> Juan Quintela writes:
>
> > Leonardo Bras wrote:
> >> Add property that allows zerocopy migration of memory pages,
> >> and also includes a helper function migrate_use_zerocopy() to check
> >> if it's enabled.
> >>
> >>
On Thu, Dec 2, 2021 at 4:58 AM David Woodhouse wrote:
>
> From: David Woodhouse
>
> We should probably check if we were meant to be exposing IR, before
> letting the guest turn the IRE bit on.
This looks correct, but it's a change of guest noticeable behaviour.
It's probably fine since we don't
On Thu, Dec 2, 2021 at 4:55 AM David Woodhouse wrote:
>
> From: David Woodhouse
>
> By setting none of the SAGAW bits we can indicate to a guest that DMA
> translation isn't supported. Tested by booting Windows 10, as well as
> Linux guests with the fix at
On Tue, Nov 30, 2021 at 9:46 PM Stefan Hajnoczi wrote:
>
> Packed Virtqueues wrap used_idx instead of letting it run freely like
> Split Virtqueues do. If the used ring wraps more than once there is no
> way to compare vq->signalled_used and vq->used_idx in
> virtio_packed_should_notify() since
-Original Message-
From: Vladimir Sementsov-Ogievskiy
Sent: Wednesday, December 1, 2021 10:27 PM
To: Rao, Lei ; Daniel P. Berrangé
Cc: Zhang, Chen ; ebl...@redhat.com; kw...@redhat.com;
hre...@redhat.com; qemu-bl...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [PATCH] QIO: Add
On Wed, Dec 01, 2021 at 10:12:27AM -0300, Daniel Henrique Barboza wrote:
> On 11/30/21 20:52, David Gibson wrote:
> > On Tue, Nov 30, 2021 at 07:24:04PM -0300, Daniel Henrique Barboza wrote:
[snip]
> > > > > +static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns)
> > > > > +{
> > >
On Wed, Nov 24, 2021 at 9:23 AM Christian Schoenebeck <
qemu_...@crudebyte.com> wrote:
> On Montag, 22. November 2021 01:49:05 CET Will Cohen wrote:
> > From: Keno Fischer
> >
> > Signed-off-by: Keno Fischer
> > Signed-off-by: Michael Roitzsch
> > Signed-off-by: Will Cohen
> > ---
> >
If the 'i8042' property is not set, mouse events handled by
vmmouse_mouse_event() end calling i8042_isa_mouse_fake_event()
with a NULL argument, resulting in ps2_mouse_fake_event() being
called with invalid PS2MouseState pointer. Fix by requiring
the 'i8042' property to be always set:
$
On 12/1/21 3:16 AM, Song Gao wrote:
This patch adds support for disassembling via option '-d in_asm'.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
include/disas/dis-asm.h | 2 +
meson.build | 1 +
target/loongarch/disas.c | 612
On 12/1/21 3:16 AM, Song Gao wrote:
+static bool gen_am(DisasContext *ctx, arg_rrr *a,
+ void (*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
+ MemOp mop)
+{
+TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+TCGv
From: David Woodhouse
We should probably check if we were meant to be exposing IR, before
letting the guest turn the IRE bit on.
Signed-off-by: David Woodhouse
---
hw/i386/intel_iommu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c
From: David Woodhouse
By setting none of the SAGAW bits we can indicate to a guest that DMA
translation isn't supported. Tested by booting Windows 10, as well as
Linux guests with the fix at https://git.kernel.org/torvalds/c/c40c10
Signed-off-by: David Woodhouse
---
hw/i386/intel_iommu.c
Hello Markus,
Thanks for sharing this info!
Best regards,
Leo
On Fri, Nov 12, 2021 at 8:59 AM Markus Armbruster wrote:
>
> Daniel P. Berrangé writes:
>
> > On Fri, Nov 12, 2021 at 12:04:33PM +0100, Juan Quintela wrote:
> >> Leonardo Bras wrote:
>
> [...]
>
> >> > diff --git
Hello Daniel,
On Fri, Nov 12, 2021 at 8:05 AM Daniel P. Berrangé wrote:
>
> On Fri, Nov 12, 2021 at 02:10:39AM -0300, Leonardo Bras wrote:
> > Add property that allows zerocopy migration of memory pages,
> > and also includes a helper function migrate_use_zerocopy() to check
> > if it's enabled.
* Juan Quintela (quint...@redhat.com) wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
(This series has a painful lot of small renamy patches)
> ---
> migration/multifd.h | 3 ++-
> migration/multifd.c | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
* Juan Quintela (quint...@redhat.com) wrote:
> So we can remove the MultiFDPages.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/multifd.h | 4 ++--
> migration/multifd-zlib.c | 2 +-
> migration/multifd-zstd.c | 2 +-
> migration/multifd.c |
Hello Juan,
On Fri, Nov 12, 2021 at 8:04 AM Juan Quintela wrote:
> Leonardo Bras wrote:
> > Add property that allows zerocopy migration of memory pages,
> > and also includes a helper function migrate_use_zerocopy() to check
> > if it's enabled.
> >
> > No code is introduced to actually do the
On Wed, Nov 24, 2021 at 7:06 PM Gerd Hoffmann wrote:
>
> qemu -display egl-headless
Thanks a lot, I tried this, and it's forced me to provide rendernode
option like this:
```
-display egl-headless,rendernode=/dev/dri/renderD128
```
My question is what I need to do to remove the need of
Polite ping. I may have missed if this patch was picked already. Thanks!
--
Regards,
Collin
Stay safe and stay healthy
* Stefan Hajnoczi:
> +#elif defined(__x86_64__)
> +#define QEMU_CO_TLS_ADDR(ret, var) \
> +asm volatile("rdfsbase %0\n\t" \
> + "lea "#var"@tpoff(%0), %0" : "=r"(ret))
> +#endif
RDFSBASE needs quite recent kernels. I
On 12/1/21 17:38, Lucas Mateus Castro (alqotel) wrote:
The instructions mtfsf, mtfsfi and mtfsb1, when called, fail to set the FI
bit (bit 46 in the FPSCR) and can set to 1 the reserved bit 52 of the
FPSCR, as reported in https://gitlab.com/qemu-project/qemu/-/issues/266
(although the bug report
Compiler optimizations can cache TLS values across coroutine yield
points, resulting in stale values from the previous thread when a
coroutine is re-entered by a new thread.
Serge Guelton developed an __attribute__((noinline)) wrapper and tested
it with clang and gcc. I formatted his idea
This patch series solves the coroutines TLS problem. Coroutines re-entered from
another thread sometimes see stale TLS values. This happens because compilers
may cache values across yield points, so a value from the previous thread will
be used when the coroutine is re-entered in another thread.
On 211201 1537, dhbbb wrote:
> Hello Alex，
> Thanks for your kind reply,it really helped me a lot! I am more
> familiar with AFL than libfuzzer，and i noticed that you said "This
> minimal init/exec interface is also supported by other fuzzers, such
> as AFL[++]".But your project seems to be highly
qemu_mutex_iothread_locked() may be used from coroutines. Standard
__thread variables cannot be used by coroutines. Use the coroutine TLS
macros instead.
Signed-off-by: Stefan Hajnoczi
---
softmmu/cpus.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/softmmu/cpus.c
RCU may be used from coroutines. Standard __thread variables cannot be
used by coroutines. Use the coroutine TLS macros instead.
Signed-off-by: Stefan Hajnoczi
---
include/qemu/rcu.h | 7 ---
tests/unit/rcutorture.c| 10 +-
tests/unit/test-rcu-list.c | 4 ++--
QEMU TLS macros must be used to make TLS variables safe with coroutines.
Signed-off-by: Stefan Hajnoczi
---
util/async.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/util/async.c b/util/async.c
index 6f6717a34b..ddd9f24419 100644
--- a/util/async.c
+++
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Signed-off-by: Lucas Mateus Castro (alqotel)
---
tests/tcg/ppc64/Makefile.target | 1 +
tests/tcg/ppc64le/Makefile.target | 1 +
tests/tcg/ppc64le/mtfsf.c | 61
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27 were also added to the mask, as they
The instructions mtfsf, mtfsfi and mtfsb1, when called, fail to set the FI
bit (bit 46 in the FPSCR) and can set to 1 the reserved bit 52 of the
FPSCR, as reported in https://gitlab.com/qemu-project/qemu/-/issues/266
(although the bug report is only for mtfsf, the bug applies to mtfsfi and
mtfsb1
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status and fp_status isn't updated based on FPSCR and
since the value of fp_status is reset earlier in the instruction,
it's always 0.
Because of this
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 6.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-6.2.0-rc3.tar.xz
Hi,
This series attempts to add support for Xilinx Versal's PMC SLCR
(system-level control registers) and OSPI flash memory controller to
Xilinx Versal virt machine.
The series start with adding a model of Versal's PMC SLCR and connecting
the model to the Versal virt machine. The series then
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 320 +
docs/devel/index.rst | 1 +
3 files changed, 322 insertions(+)
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..e52cc94840 100644
--- a/MAINTAINERS
+++
An option on real hardware when embedding a DMA engine into a peripheral
is to make the peripheral control the engine through a custom DMA control
(hardware) interface between the two. Software drivers in this scenario
configure and trigger DMA operations through the controlling peripheral's
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 88
include/hw/arm/xlnx-versal.h | 20 ++
2 files
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Acked-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1445
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1892 +
include/hw/ssi/xlnx-versal-ospi.h | 86 ++
3 files changed, 1979
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 17 +
include/hw/arm/xlnx-versal.h | 6 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 32
include/hw/dma/xlnx_csu_dma.h |
On [2021 Nov 29] Mon 17:44:37, Peter Maydell wrote:
> On Wed, 24 Nov 2021 at 10:16, Francisco Iglesias
> wrote:
> >
> > Add an interface for controlling DMA models that are reused with other
> > models. This allows a controlling model to start transfers through the
> > DMA while reusing the DMA's
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amount of instructions translated
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also
The current logic is only considering event-based exceptions triggered
by the performance monitor. This is true now, but we might want to add
support for external event-based exceptions in the future.
Let's make it a bit easier to do so by adding the bit logic that would
happen in case we were
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow logic later on. Let's
put the
From: Gustavo Romero
Following up the rfebb implementation, this patch adds the EBB exception
support that are triggered by Performance Monitor alerts. This exception
occurs when an enabled PMU condition or event happens and both MMCR0_EBE
and BESCR_PME are set.
The supported PM alerts will
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x8000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x8000) a performance monitor alert will occur. This alert
can
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1)
Hi,
In this new version the most significant change is in patch 6,
where a new hflag allows us to not call the instruction helper
inside translate.c unless we're absolutely certain that there
is an instruction count event being sampled and active in the
PMU. This change turned out to be a big
01.12.2021 12:48, Rao, Lei wrote:
-Original Message-
From: Daniel P. Berrangé
Sent: Wednesday, December 1, 2021 5:11 PM
To: Rao, Lei
Cc: Zhang, Chen ; ebl...@redhat.com;
vsement...@virtuozzo.com; kw...@redhat.com; hre...@redhat.com; qemu-bl...@nongnu.org;
qemu-devel@nongnu.org
On Wed, Dec 1, 2021 at 01:19 Richard Henderson
wrote:
> On 11/30/21 9:47 PM, Eduardo Habkost wrote:
> > * MAINTAINERS: Change my email address (Eduardo Habkost)
> >
> > Eduardo Habkost (1):
> >MAINTAINERS: Change my email address
> >
> > MAINTAINERS | 12 ++--
> > 1 file changed,
On 12/1/21 3:09 PM, Daniel P. Berrangé wrote:
On Wed, Dec 01, 2021 at 02:42:04PM +0100, Li Zhang wrote:
On 12/1/21 1:22 PM, Daniel P. Berrangé wrote:
On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de)
On Wed, Dec 01, 2021 at 02:42:04PM +0100, Li Zhang wrote:
>
> On 12/1/21 1:22 PM, Daniel P. Berrangé wrote:
> > On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
> > > On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
> > > > * Li Zhang (lizh...@suse.de) wrote:
> > > > > On 11/29/21
On 11/30/21 10:41, Michal Prívozník wrote:
> On 11/30/21 09:35, Mark Cave-Ayland wrote:
>> Hi all,
>>
>> Has there been a recent change as to how square brackets are encoded
>> within QOM names? I noticed that the output has changed here in the
>> "info qom-tree" output in qemu-system-m68k for the
On 12/1/21 1:22 PM, Daniel P. Berrangé wrote:
On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
On 11/29/21 12:20 PM, Dr. David Alan Gilbert wrote:
* Daniel P. Berrangé (berra...@redhat.com)
When searching for the latest umn.edu patches I stumbled upon a recently
submitted fix for a bug purportedly introduced by umn.edu:
https://lore.kernel.org/r/yazc4lbx5hrjd...@hovoldconsulting.com
The patch in question is obviously bogus, but a closer look at the
function in question
An initialised kobject must be freed using kobject_put() to avoid
leaking associated resources (e.g. the object name).
Commit fe3c60684377 ("firmware: Fix a reference count leak.") "fixed"
the leak in the first error path of the file registration helper but
left the second one unchanged. This
Make sure to always NUL-terminate file names retrieved from the firmware
to avoid accessing data beyond the entry slab buffer and exposing it
through sysfs in case the firmware data is corrupt.
Fixes: 75f3e8e47f38 ("firmware: introduce sysfs driver for QEMU's fw_cfg
device")
Cc:
Commit fe3c60684377 ("firmware: Fix a reference count leak.") "fixed"
a kobject leak in the file registration helper by properly calling
kobject_put() for the entry in case registration of the object fails
(e.g. due to a name collision).
This would however result in a NULL pointer dereference
Explicitly remove the file entries from sysfs before dropping the final
reference for symmetry reasons and for consistency with the rest of the
driver.
Signed-off-by: Johan Hovold
---
drivers/firmware/qemu_fw_cfg.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 11/30/21 20:52, David Gibson wrote:
On Tue, Nov 30, 2021 at 07:24:04PM -0300, Daniel Henrique Barboza wrote:
On 11/29/21 01:36, David Gibson wrote:
On Thu, Nov 25, 2021 at 12:08:13PM -0300, Daniel Henrique Barboza wrote:
The PMU is already counting cycles by calculating time elapsed
On 11/30/21 18:32, Peter Maydell wrote:
> The calculation of the length of TLB range invalidate operations
> in tlbi_aa64_range_get_length() is incorrect in two ways:
> * the NUM field is 5 bits, but we read only 4 bits
> * we miscalculate the page_shift value, because of an
>off-by-one
On 11/29/21 21:05, Peter Maydell wrote:
> Peter Maydell (4):
> include/hw/i386: Don't include qemu-common.h in .h files
> target/hexagon/cpu.h: don't include qemu-common.h
> target/rx/cpu.h: Don't include qemu-common.h
> hw/arm: Don't include qemu-common.h unnecessarily
Reviewed-by:
On 11/29/21 21:55, Peter Maydell wrote:
> softmmu/rtc.c defines two public functions: qemu_get_timedate() and
> qemu_timedate_diff(). Currently we keep the prototypes for these in
> qemu-common.h, but most files don't need them. Move them to their
> own header, a new include/sysemu/rtc.h.
>
>
On 01/12/2021 04:51, Cédric Le Goater wrote:
The ISO is too big for quick tests. Isn't there a minimum initrd ? can
we build a
builroot-like image for FreeBSD ?
FreeBSD doesn't use initrd. Its bootloader loads kernel modules directly
from disk (unfortunately, it doesn't work on PowerNV).
On Mon, Nov 29, 2021 at 12:05 AM Frédéric Pétrot
wrote:
>
> lwu and ld are functionally close to the other loads, but were after the
> stores in the source file.
> Similarly, xor was away from or and and by two arithmetic functions, while
> the immediate versions were nicely put together.
> This
On Tue, 30 Nov 2021 05:05:09 +0900,
Peter Maydell wrote:
>
> The qemu-common.h header is not supposed to be included from any
> other header files, only from .c files (as documented in a comment at
> the start of it).
>
> Nothing actually relies on target/rx/cpu.h including it, so we can
> just
On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
>
> On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
> > * Li Zhang (lizh...@suse.de) wrote:
> > > On 11/29/21 12:20 PM, Dr. David Alan Gilbert wrote:
> > > > * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > > > > On Fri, Nov 26,
On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
On 11/29/21 12:20 PM, Dr. David Alan Gilbert wrote:
* Daniel P. Berrangé (berra...@redhat.com) wrote:
On Fri, Nov 26, 2021 at 04:31:53PM +0100, Li Zhang wrote:
When doing live migration with multifd
On Tue, Nov 30, 2021 at 11:20:57AM +, Stefan Hajnoczi wrote:
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when
Jonathan Cameron writes:
> On Tue, 30 Nov 2021 09:21:58 -0800
> Ben Widawsky wrote:
>
>> On 21-11-30 13:09:56, Jonathan Cameron wrote:
>> > On Mon, 29 Nov 2021 18:28:43 +
>> > Alex Bennée wrote:
>> >
>> > > Ben Widawsky writes:
>> > >
>> > > > On 21-11-26 12:08:08, Alex Bennée
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