[PATCH 3/4] ui: Revert: "fix incorrect pointer position on highdpi with gtk"

This reverts commit f14aab420c58b57e07189d6d9e6d3fbfab4761a6. This commit was originally tested on gtk/gl which corrected behavior there. Turns out, the OpenGL texture representing the virtual console was being rendered in the incorrect place and not that the cursor was incorrectly being handled.

[PATCH 1/4] ui: Use allocated size instead of window size

In these cases, we only care about the size of the virtual console itself. Previously, these calculations were made using the size of the entire window, which would include the size of the virtual console plus all the ui elements around it. Signed-off-by: Alexander Orzechowski --- ui/gtk.c | 26

[PATCH 4/4] ui: Fix gtk/gl when the scaled virtual console does not fit the window

gtk/gl was incorrectly always rendering as if the 'Zoom to Fit' was always checked even if it wasn't. This is now using logic closer to what is being used for the existing cairo code paths. Signed-off-by: Alexander Orzechowski --- ui/gtk-gl-area.c | 34 +- 1 file

[PATCH 2/4] ui: Remove unnecessary checks

These conditionals should never be false as scale_x and scale_y should scale the fbw and fbh variables such that the ww and wh variables always have a greater magnitude. Signed-off-by: Alexander Orzechowski --- ui/gtk.c | 27 ++- 1 file changed, 6 insertions(+), 21 deleti

[PATCH 0/4] UI fixups

Some UI fixups including one revert. I have some things that I want to have a discussion about. Fullscreen mode will always distort the virtual console. Is this behavior we really want? If we get rid of this, we can combine scale_x and scale_y into a single variable and simplify things a little bi

Re: [PATCH 04/20] tcg/s390x: Implement vector NAND, NOR, EQV

On 12/18/21 20:42, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/s390x/tcg-target.h | 6 +++--- > tcg/s390x/tcg-target.c.inc | 17 + > 2 files changed, 20 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 03/20] tcg/ppc: Implement vector NAND, NOR, EQV

On 12/18/21 20:42, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target.h | 6 +++--- > tcg/ppc/tcg-target.c.inc | 15 +++ > 2 files changed, 18 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t

On 23/10/2021 21:59, Matthias Schiffer wrote: When converting a siginfo_t from waitid(), the interpretation of si_status depends on the value of si_code: For CLD_EXITED, it is an exit code and should be copied verbatim. For other codes, it is a signal number (possibly with additional high bits fr

[PATCH 20/20] tcg/i386: Implement bitsel for avx512

The general ternary logic operation can implement BITSEL. Funnel the 4-operand operation into three variants of the 3-operand instruction, depending on input operand overlap. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 20 ++

[PATCH 15/20] tcg/i386: Remove rotls_vec from tcg_target_op_def

There is no such instruction on x86, so we should not be pretending it has arguments. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 54fb8321a9..99ec31977a 100644 --- a/

[PATCH 11/20] tcg/i386: Implement avx512 immediate rotate

AVX512VL has VPROLD and VPROLQ, layered onto the same opcode as PSHIFTD, but requires EVEX encoding and W. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 15 +-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/i

[PATCH 08/20] tcg/i386: Implement avx512 variable shifts

AVX512VL has VPSRAVQ, and AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 32 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 316e5

[PATCH 16/20] tcg/i386: Expand scalar rotate with avx512 insns

Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V; expand 16-bit scalar rotate with VPSHLDV. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 49 +++ 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc

[PATCH 06/20] tcg/i386: Add tcg_out_evex_opc

The evex encoding is added here, for use in a subsequent patch. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 51 ++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index e

[PATCH 19/20] tcg/i386: Implement more logical operations for avx512

The general ternary logic operation can implement NOT, ORC, NAND, NOR, EQV. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 10 +- tcg/i386/tcg-target.c.inc | 34 ++ 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/tcg/i386/

[PATCH 18/20] tcg/i386: Implement avx512 multiply

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 22eaa53cb1..f982b6e615 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc

[PATCH 17/20] tcg/i386: Implement avx512 min/max/abs

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 447aab7438..22eaa53cb1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-targe

[PATCH 04/20] tcg/s390x: Implement vector NAND, NOR, EQV

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 6 +++--- tcg/s390x/tcg-target.c.inc | 17 + 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index ad29e62b16..fef227b0fe 100644 --- a/tcg/s390x/tcg-t

[PATCH 14/20] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double

While there are no specific 16-bit rotate instructions, there are double-word shifts, which can perform the same operation. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.

[PATCH 13/20] tcg/i386: Support avx512vbmi2 vector shift-double instructions

We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 1 + tcg/i386/tcg-target.opc.h | 3 +++ tcg/i386/tcg-target.c.inc | 38 +++ 3 files changed, 42 insertions(+) diff --git a/t

[PATCH 03/20] tcg/ppc: Implement vector NAND, NOR, EQV

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 6 +++--- tcg/ppc/tcg-target.c.inc | 15 +++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d4fd28c6b0..6a6bc3f480 100644 --- a/tcg/ppc/tcg-target.h +++

[PATCH 12/20] tcg/i386: Implement avx512 variable rotate

AVX512VL has VPROLVQ and VPRORVQ. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 25 - 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 38c09fd66c..841b

[PATCH 10/20] tcg/i386: Implement avx512 immediate sari shift

AVX512 has VPSRAQ with immediate operand, in the same form as with AVX, but requires EVEX encoding and W1. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 29 - 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b

[PATCH 07/20] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv

The condition for UMIN/UMAX availability is about to change; use the canonical version. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 44d291904

[PATCH 02/20] tcg: Add opcodes for vector nand, nor, eqv

We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +++ include/tcg/tcg.h| 3 +++ tcg/aarch64/tcg-target.h | 3 +++ tcg/arm/tcg-target.h | 3 +++ tcg/i386/

[PATCH 00/20] tcg: vector improvements

Add some opcodes for compound logic operations that were so far marked as TODO. Implement those for PPC and S390X. We do not want to implement 512-bit width operations, because those trigger a cluster clock slowdown on the current set of Intel cpus. But there are new operations in avx512 that ap

[PATCH 09/20] tcg/i386: Implement avx512 scalar shift

AVX512VL has VPSRAQ. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 7b9302fcc2..69481c188c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tc

[PATCH 05/20] tcg/i386: Detect AVX512

There are some operation sizes in some subsets of AVX512 that are missing from previous iterations of AVX. Detect them. Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 20 +--- tcg/i386/tcg-target.h | 4 tcg/i386/tcg-target.c.inc | 24 +

[PATCH 01/20] tcg/optimize: Fix folding of vector ops

Bitwise operations are easy to fold, because the operation is identical regardess of element size. But add and sub need extra element size info that is not currently propagated. Fixes: 2f9f08ba43d Signed-off-by: Richard Henderson --- tcg/optimize.c | 49 ++---

Re: [PULL 00/16] qtest and gitlab-CI improvements

Hi, On 12/15/21 08:33, Thomas Huth wrote: > > * Add virtio-net failover test > * Make qtests a little bit more flexible with regards to reduced configs > * Move libssh setup from configure to meson.build > * Run device-crash-test in

Re: [RFC PATCH 0/3] hw/audio/intel-hda: Restrict DMA engine to memories (CVE-2021-3611)

On 12/18/21 17:09, Philippe Mathieu-Daudé wrote: > An attempt to fix the Intel HDA DMA reentrancy problem by > restricting the DMA engine to memories, and reporting invalid > I/O region accesses as overruns. Eh reading again the gitlab issue I realized CVE-2021-3611 has been assigned for this.

[RFC PATCH 3/3] tests/qtest/intel-hda-test: Add reproducer for issue #542

Include the qtest reproducer provided by Alexander Bulekov in https://gitlab.com/qemu-project/qemu/-/issues/542. Without the previous commit, we get: $ make check-qtest-i386 ... Running test tests/qtest/intel-hda-test AddressSanitizer:DEADLYSIGNAL

[RFC PATCH 2/3] hw/audio/intel-hda: Restrict DMA engine to memories (not MMIO devices)

Issue #542 reports a reentrancy problem when the DMA engine accesses the HDA controller I/O registers. Fix by restricting the DMA engine to memories regions (forbidding MMIO devices such the HDA controller). Reported-by: OSS-Fuzz (Issue 28435) Reported-by: Alexander Bulekov Resolves: https://gitl

[RFC PATCH 0/3] hw/audio/intel-hda: Restrict DMA engine to memories (non-MMIO devices)

An attempt to fix the Intel HDA DMA reentrancy problem by restricting the DMA engine to memories, and reporting invalid I/O region accesses as overruns. Based-on: <20211218151053.1545962-1-phi...@redhat.com> "hw: Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 4)" https://lore.kerne

[RFC PATCH 1/3] hw/audio/intel-hda: Do not ignore DMA overrun errors

Per the "High Definition Audio Specification" manual (rev. 1.0a), section "3.3.30 Offset 5Dh: RIRBSTS - RIRB Status": Response Overrun Interrupt Status (RIRBOIS): Hardware sets this bit to a 1 when an overrun occurs in the RIRB. An interrupt may be generated if the Response Overrun Interrup

Re: [PATCH v2] audio: Add sndio backend

Hi Alexandre, sndio is the native API used by OpenBSD, although it has been ported to other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.). Signed-off-by: Brad Smith Signed-off-by: Alexandre Ratchov --- Thank you for the reviews and all the comments. Here's a second diff wi

[PATCH 5/5] dma: Let ld*_pci_dma() propagate MemTxResult

ld*_dma() returns a MemTxResult type. Do not discard it, return it to the caller. Update the few callers. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 17 - hw/audio/intel-hda.c | 2 +- hw/net/eepro100.c| 25 ++--- hw/net/tulip.c

[PATCH 4/5] dma: Let st*_pci_dma() propagate MemTxResult

st*_dma() returns a MemTxResult type. Do not discard it, return it to the caller. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 7a46c1fa226..c90cecc85

[PATCH 2/5] dma: Let st*_pci_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling st*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 11 ++- hw/audio/intel-hda.c | 10 ++ hw/net/eepro100.c| 29 ++-

[PATCH 3/5] dma: Let ld*_pci_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling ld*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 6 +++--- hw/audio/intel-hda.c | 2 +- hw/net/eepro100.c| 19 +-- hw/net/tuli

[PATCH 1/5] hw/scsi/megasas: Use uint32_t for reply queue head/tail values

While the reply queue values fit in 16-bit, they are accessed as 32-bit: 661:s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa); 662:s->reply_queue_head %= MEGASAS_MAX_FRAMES; 663:s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa); 664:s->reply_queue_tail %=

[PATCH 0/5] hw: Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 4)

After updating the dma_buf API (part 2) and the ld/st DMA API (part 3), we now update the ld/st PCI DMA API to: - take a MemTxAttrs argument, - propagate a MemTxResult. Based-on: <20211218145111.1540114-1-phi...@redhat.com> "Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 3)" https:

Re: [PATCH v2] block: drop BLK_PERM_GRAPH_MOD

Ping) 03.09.2021 21:47, Eric Blake wrote: On Thu, Sep 02, 2021 at 12:37:54PM +0300, Vladimir Sementsov-Ogievskiy wrote: First, this permission never protected a node from being changed, as generic child-replacing functions don't check it. Second, it's a strange thing: it presents a permission

[PATCH 3/4] dma: Let st*_dma() propagate MemTxResult

dma_memory_write() returns a MemTxResult type. Do not discard it, return it to the caller. Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/dma.h | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index b

[PATCH 1/4] dma: Let st*_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling st*_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 3 ++- include/hw/ppc/spapr_vio.h | 12 include/sysemu/dma.h | 10 ++

[PATCH 4/4] dma: Let ld*_dma() propagate MemTxResult

dma_memory_read() returns a MemTxResult type. Do not discard it, return it to the caller. Update the few callers. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 6 -- include/hw/ppc/spapr_vio.h | 6 +- include/sysemu/dma.h | 25 -

[PATCH 2/4] dma: Let ld*_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling ld*_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci.h | 3 ++- include/hw/ppc/spapr_vio.h | 3 ++- include/sysemu/dma.h | 11 ++- hw/intc

[PATCH 0/4] hw: Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 3)

After updating the dma_buf API in part 3, we now update the ld/st API to: - take a MemTxAttrs argument, - propagate a MemTxResult. Based-on: <20211216123558.799425-1-phi...@redhat.com> "Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 2)" https://www.mail-archive.com/qemu-devel@nongn

build qemu on Monterey?

Hi : Has anyone tried this? Yes, I know about https://wiki.qemu.org/Hosts/Mac but I am getting $ ./configure --target-list=x86_64-softmmu Using './build' as the directory for build output Disabling PIE due to missing toolchain support ERROR: glib-2.56 gthread-2.0 is required to compile QEMU whe

[PATCH v2 5/5] hw/input/pckbd: Open-code i8042_setup_a20_line() wrapper

Since the named GPIO lines are a "public" interface to the device, we can directly call qdev_connect_gpio_out_named(), making it consistent with how the other A20 input source (port92) is wired. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- include/hw/input/i8042.h | 1 -

[PATCH v2 2/5] hw/qdev: Correct qdev_init_gpio_out_named() documentation

qdev_init_gpio_out_named() is described as qdev_init_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Reported-by: Yanan Wang Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/incl

[PATCH v2 4/5] hw/qdev: Rename qdev_connect_gpio_out*() 'input_pin' parameter

@pin is an input where we connect a device output. Rename it @input_pin to simplify the documentation. Reviewed-by: Yanan Wang Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 6 +++--- hw/core/gpio.c | 13 +++-- 2 files changed, 10 insertions(+), 9 deletions(

[PATCH v2 1/5] hw/qdev: Cosmetic around documentation

Add empty lines to have a clearer distinction between different functions declarations. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 20d3066595e..59a822ffceb

[PATCH v2 0/5] hw/qdev: Clarify qdev_connect_gpio_out() documentation

Trivial patches clarifying qdev_connect_gpio_out() use, basically that the qemu_irq argument is an input. Since v1: - Addressed Yanan Wang and Peter Maydell comments: - Correct qdev_init_gpio_out_named() doc - Drop i8042_setup_a20_line() wrapper Philippe Mathieu-Daudé (5): hw/qdev: Cosmetic aro

[PATCH v2 3/5] hw/qdev: Correct qdev_connect_gpio_out_named() documentation

qdev_connect_gpio_out_named() is described as qdev_connect_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hw/qdev-co

Re: [RFC PATCH v2 14/14] job.c: enable job lock/unlock and remove Aiocontext locks

04.11.2021 17:53, Emanuele Giuseppe Esposito wrote: --- a/block/replication.c +++ b/block/replication.c @@ -728,9 +728,11 @@ static void replication_stop(ReplicationState *rs, bool failover, Error **errp) * disk, secondary disk in backup_job_completed(). */ if (s-

Re: [RFC PATCH v2 13/14] jobs: add job lock in find_* functions

18.12.2021 15:11, Vladimir Sementsov-Ogievskiy wrote: 04.11.2021 17:53, Emanuele Giuseppe Esposito wrote: Both blockdev.c and job-qmp.c have TOC/TOU conditions, because they first search for the job and then perform an action on it. Therefore, we need to do the search + action under the same job

Re: [RFC PATCH v2 13/14] jobs: add job lock in find_* functions

04.11.2021 17:53, Emanuele Giuseppe Esposito wrote: Both blockdev.c and job-qmp.c have TOC/TOU conditions, because they first search for the job and then perform an action on it. Therefore, we need to do the search + action under the same job mutex critical section. Note: at this stage, job_{loc

Re: [RFC PATCH v2 11/14] block_job_query: remove atomic read

04.11.2021 17:53, Emanuele Giuseppe Esposito wrote: Not sure what the atomic here was supposed to do, since job.busy is protected by the job lock. In block_job_query() it is protected only since previous commit. So, before previous commit, atomic read make sense. Hmm. but job_lock() is still

Re: [RFC PATCH v2 10/14] jobs: protect jobs with job_lock/unlock

04.11.2021 17:53, Emanuele Giuseppe Esposito wrote: Introduce the job locking mechanism through the whole job API, following the comments and requirements of job-monitor (assume lock is held) and job-driver (lock is not held). job_{lock/unlock} is independent from_job_{lock/unlock}. Note: at th

Re: [RFC PATCH v2 05/14] block/mirror.c: use of job helpers in drivers to avoid TOC/TOU

04.11.2021 17:53, Emanuele Giuseppe Esposito wrote: Once job lock is used and aiocontext is removed, mirror has to perform job operations under the same critical section, using the helpers prepared in previous commit. Note: at this stage, job_{lock/unlock} and job lock guard macros are *nop*. S

[PATCH] hw: m68k: Add virt compat machine type for 7.0

Signed-off-by: Laurent Vivier --- Based-On: <20211217143948.289995-1-coh...@redhat.com> hw/m68k/virt.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index 0efa4a45c7f4..78e926a55457 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@

Re: [RFC PATCH v3 3/3] softmmu/physmem: Introduce MemTxAttrs::memory field and MEMTX_BUS_ERROR

On 12/18/21 03:07, Richard Henderson wrote: > On 12/17/21 3:18 PM, Philippe Mathieu-Daudé wrote:   #define MEMTX_OK 0   #define MEMTX_ERROR (1U << 0) /* device returned an error */   #define MEMTX_DECODE_ERROR  (1U << 1) /* nothing at that address */ +#

[PATCH v2] hw/scsi/megasas: Simplify using the ldst API

This code is easier to review using the load/store API. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v2: Fixed offset in megasas_setup_inquiry (rth) --- hw/scsi/megasas.c | 17 +++-- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/hw/scsi/m

Re: [PATCH] hw/scsi/megasas: Simplify using the ldst API

On 12/18/21 01:36, Richard Henderson wrote: > On 12/17/21 3:15 PM, Philippe Mathieu-Daudé wrote: >> -    cdb[3] = (len >> 8) & 0xff; >> -    cdb[4] = (len & 0xff); >> +    stw_be_p(&cdb[2], len); > > Wrong offset.  Otherwise, >_< > Reviewed-by: Richard Henderson Thank you.

Re: [PATCH 04/10] configure: do not set bsd_user/linux_user early

On 12/17/21 21:49, Richard Henderson wrote: On 12/16/21 12:51 AM, Paolo Bonzini wrote: @@ -541,7 +541,6 @@ gnu/kfreebsd)   ;;   freebsd)     bsd="yes" -  bsd_user="yes"     make="${MAKE-gmake}"     # needed for kinfo_getvmmap(3) in libutil.h   ;; @@ -586,7 +585,6 @@ haiku)   ;;   linux)     linu

Re: [RFC PATCH v3 23/27] hw/loongarch: Add LoongArch ls7a rtc device support

On 04/12/2021 12:07, Xiaojuan Yang wrote: This patch add ls7a rtc device support. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 1 + hw/loongarch/loongson3.c | 3 + hw/rtc/Kconfig | 3 + hw/rtc/ls7a_rtc.c | 323

Re: [RFC PATCH] docs/devel: more documentation on the use of suffixes

On 12/17/21 18:19, Alex Bennée wrote: Using _qemu is a little confusing. Let's use _compat for these sorts of things. We should also mention _impl which is another common suffix in the code base. Signed-off-by: Alex Bennée --- docs/devel/style.rst | 7 +++ include/glib-compat.h | 6 +++-

Re: [RFC PATCH v3 22/27] hw/loongarch: Add some devices support for 3A5000.

On 04/12/2021 12:07, Xiaojuan Yang wrote: 1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the pci host. Non pci device use irq 0-16, pci device use 16-64. 3.Add some unimplented device to emulate guest unused memory space. Signed-off-by: Xiaojuan Yang Signed-off-by: Son

[PATCH] qemu-options: warn for short form booleans in all parsing functions

qemu_opts_parse and qemu_opts_do_parse were not warning for short form booleans. qemu_opts_parse is used internally and short form boolean options are never passed to it. qemu_opts_do_parse is mostly used by the block layer, and also for character device creation with options other than -chardev.

Re: [RFC PATCH v3 21/27] hw/loongarch: Add irq hierarchy for the system

On 04/12/2021 12:07, Xiaojuan Yang wrote: This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c | 84 ++ include/hw/pci-host/ls7a.h | 13 ++ 2 files changed, 97 inser

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

Don't know if this is the reason of our problems but I think there is something to investigate around timer interrupts: / # cat /proc/interrupts CPU0    16: 68   UIC   1 Level serial LOC:  0   Local timer interrupts for timer event device LOC:  0   Lo