在 2022/1/2 上午3:48, Richard Henderson 写道:
ol is the operation length; xl is the register length.
In this case, the operation length doesn't matter -- we're interested
in distinguishing RV32 and RV64, because that's where the change in
semantics comes from.
So both read and write fpr
在 2022/1/2 上午3:46, Richard Henderson 写道:
On 12/31/21 9:55 PM, Weiwei Li wrote:
This shouldn't be necessary because it should never have been set.
Yes, I think so. However, I have a question about MSTATUS_MIE and
MSTATUS_MPRV, will they be set before cpu reset?
Yes, via warm reset.
Thanks.
Thanks for your comments.
I'll fix the three flags.
在 2022/1/1 下午9:15, Anup Patel 写道:
On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li wrote:
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
On 12/31/21 10:05 PM, Weiwei Li wrote:
在 2022/1/1 上午4:06, Richard Henderson 写道:
On 12/30/21 7:23 PM, Weiwei Li wrote:
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
Oh, you should be using get_xl here and elsewhere in this patch, not get_ol.
Sorry. I don't know the difference
On 12/31/21 9:55 PM, Weiwei Li wrote:
This shouldn't be necessary because it should never have been set.
Yes, I think so. However, I have a question about MSTATUS_MIE and MSTATUS_MPRV, will they
be set before cpu reset?
Yes, via warm reset.
I would think it would be more correct to have a
On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li wrote:
>
> It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is
> sequentially consistent and doesn't model PMAs currently
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Tested-by: Heiko Stuebner
> ---
>
On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/cpu.c| 1 +
> target/riscv/cpu.h| 1 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 20
> 4 files
On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++
>
On Wed, Dec 29, 2021 at 01:57:49PM -0300, Fabiano Rosas wrote:
> None of the interrupt setup code touches 'vector', so we can move it
> earlier in the function. This will allow us to later move the System
> Call Vectored setup that is on the top level into the
> POWERPC_EXCP_SYSCALL_VECTORED code
On Wed, Dec 29, 2021 at 01:57:48PM -0300, Fabiano Rosas wrote:
> The next patch will start accessing the excp_vectors array earlier in
> the function, so add a bounds check as first thing here.
>
> This converts the empty return on POWERPC_EXCP_NONE to an error. This
> exception number never
10 matches
Mail list logo
