On 12/30/21 23:12, Daniel Henrique Barboza wrote:
On 12/23/21 18:19, Richard Henderson wrote:
On 12/23/21 12:36 PM, Daniel Henrique Barboza wrote:
This reorg is breaking PMU-EBB tests, unfortunately. These tests are run from
the kernel
tree [1] and I test them inside a pSeries TCG guest. You
CCing, qemu-stable@
On Mon, 27 Dec 2021 14:31:17 -0500
Igor Mammedov wrote:
> if QEMU is started with used provided SLIC table blob,
>
> -acpitable sig=SLIC,oem_id='CRASH
> ',oem_table_id="ME",oem_rev=2210,asl_compiler_id="",asl_compiler_rev=,data=/dev/null
> it will assert with:
On 12/23/21 21:18, Daniel Henrique Barboza wrote:
Hi,
In this version the tedious repetition was taken away from the
code by using a helper that increments the PMCs based on specified
conditions.
As far as Avocado test goes, the performance is the same as the previous
version. All PMU-EBB kerne
The 405 timers were broken when booke support was added. Assumption
was made that the register numbers were the same but it's not :
SPR_BOOKE_TSR (0x150)
SPR_BOOKE_TCR (0x154)
SPR_40x_TSR (0x3D8)
SPR_40x_TCR (0x3DA)
Cc: Christophe Leroy
Fixes:
Use a QEMU log primitive for errors and trace events for debug.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20211222064025.1541490-3-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/mpc8544_guts.c | 9 ++---
hw/ppc/ppc4xx_
This is a small cleanup to ease reading. It includes the removal of a
check done on the returned value of g_malloc0(), which can not fail.
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-6-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/p
There is no need to deactivate MMU logging at compile time. Remove all
use of defines. Only keep DUMP_PAGE_TABLES for another series since
page tables could be dumped from the monitor.
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-4-...@kaod.org>
Signed-off-by: Cédric Le Goa
Timers are already initialized in ppc4xx_init(). No need to do it a
second time with a wrong set.
Fixes: d715ea961254 ("PPC: 405: Fix ppc405ep initialization")
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-7-...@kaod.org>
Signed-off-by: Cédric
Rework slightly ppc_cpu_dump_state() to replace the various 'if'
statements with a 'switch'.
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-9-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 27 +--
The compiler should know better how to inline code if necessary.
Suggested-by: Richard Henderson
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
inde
Hello,
The series starts with a couple of cleanups helping debug. It then
adds back support for 405 timers which was broken 10 years ago.
Thanks,
C.
Changes in v2:
- removed inlining from powerpc_excp() routines
- fixed a compile breakage with CONFIG_USER_ONLY
- removed all DEBUG defines f
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-8-...@kaod.org>
Signed-off-by: Cédric Le Goater
It facilitates reading the logs when mask CPU_LOG_INT is activated. We
should do the same for error codes.
Cc: Fabiano Rosas
Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20211222064025.1541490-2-...@kaod.org>
On Wed, Dec 29, 2021 at 7:03 PM Philippe Mathieu-Daudé
wrote:
> On 12/23/21 05:11, Richard Henderson wrote:
> > Hi John,
> >
> > This test has been failing for quite a while. While it is allowed to
> > fail, can we either fix this or disable it, to allow the ci to go proper
> > green?
>
> This jo
Am Sonntag, 19. Dezember 2021, 00:32:09 CET schrieb Matthias Schiffer:
> On 23/10/2021 21:59, Matthias Schiffer wrote:
> > When converting a siginfo_t from waitid(), the interpretation of si_status
> > depends on the value of si_code: For CLD_EXITED, it is an exit code and
> > should be copied verb
On 2/1/22 22:58, Patrick Venture wrote:
Add the four lm75s behind the mux on bus 13.
Tested by booting the firmware:
lm75 42-0048: hwmon0: sensor 'lm75'
lm75 43-0049: supply vs not found, using dummy regulator
lm75 43-0049: hwmon1: sensor 'lm75'
lm75 44-0048: supply vs not found, using dummy reg
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 257bf638fd..4cd58972c5 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -330,8
On 2/1/22 22:58, Patrick Venture wrote:
From: Chris Rauer
Signed-off-by: Chris Rauer
Reviewed-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 8
1 file changed, 8 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
---
hw/arm/npcm7xx_boards.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 37de9fef43..257bf638fd 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b
This series of patches adds various devices that are defined in the device-tree
for this board.
Chris Rauer (1):
hw/arm: Add kudo i2c eeproms.
Patrick Venture (2):
hw/arm: add i2c muxes to kudo-bmc
hw/arm: kudo add lm75s on bus 13
Shengtan Mao (1):
hw/arm: attach MMC to kudo-bmc
hw/ar
Add the four lm75s behind the mux on bus 13.
Tested by booting the firmware:
lm75 42-0048: hwmon0: sensor 'lm75'
lm75 43-0049: supply vs not found, using dummy regulator
lm75 43-0049: hwmon1: sensor 'lm75'
lm75 44-0048: supply vs not found, using dummy regulator
lm75 44-0048: hwmon2: sensor 'lm75'
From: Chris Rauer
Signed-off-by: Chris Rauer
Reviewed-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 0866d2f4f0..37de9fef43 100644
--- a/hw/arm/npcm7xx_boar
On 12/28/21 13:57, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit
> is not set to 1 correclty when the assigned SD image size is larger
> than 2GB (SDHC). This will cause the SD card to be indentified as SDSC
> incorrectly
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest. Defaults to enabled.
Also updated the cocoa display documentation to ref
This resolves an issue where using command-tab to switch between QEMU
and other windows on the host can leave the mouse pointer visible.
By releasing the mouse when the user switches away, the user must left
click on the QEMU window when switching back in order to hide the
pointer and return contr
Supersedes earlier submissions and splits the patch into two separate
patches covering
- addition of left-command-key option to disable forwarding this key
to the guest
- fix for persistent mouse cursor when switching from and back to the
QEMU window
Having made the switch to an M1 Ma
1) Make the QEMU monitor `info registers' command more informative
2) Implement the QEMU monitor `print $register'
3) Introduce a new command `info gmem' to the QEMU monitor, which displays
a RISC-V hypervisor's guest's 2nd level paging tables similarly to the
existing `info mem' command.
4)
GDB target descriptions support typed registers;
such that `info register X' displays not only the hex value of
register `X', but also the individual bitfields the register
comprises (if any), using textual labels if possible.
This patch includes type information for GDB for
a large subset of the
This is analog to the existing 'info mem' command and is implemented
using the same machinery.
Signed-off-by: Konrad Schwarz
---
hmp-commands-info.hx | 16 +
include/monitor/hmp-target.h | 2 +
target/riscv/monitor.c | 135 +--
3 files changed
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz
---
target/riscv/monitor.c | 69
The RISC-V Debug Support specification suggests debuggers provide
"virtual debug registers" to show state not directly visible in the ISA,
and defines one such register, `priv', which encodes the processor's
current operating mode in the two least significant bits.
GDB represents virtual debug reg
Display more CSRs in the 'info registers' command
and group them according to function.
The number of CSRs in RISC-V is so large to make it impractical
for all CSRs to be displayed by 'info registers'.
The code uses conditional compilation directives around register
groups; advanced users can enab
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