FreeBSD is dropping support for mips starting with FreeBSD 14. mips
support has been removed from the bsd-user fork because updating it for
new signal requirements will take too much time. Remove it here since it
is a distraction.
Signed-off-by: Warner Losh
Acked-by: Richard Henderson
---
bsd-u
No functional change; just moving the saved reserved regs to the end.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/x86_64/target_arch_signal.h | 4
1 file changed, 4 deletions(-)
diff --git a/bsd-user/x86_64/target_arch_signal.h
b
Fill in target_mcontext match the FreeBSD mcontext_t structure. Also
define the size correctly.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/x86_64/target_arch_signal.h | 54
1 file changed, 54 insertions(+)
diff --git a/bsd-user/x86_64/ta
During normal processing, the constant pool is accessible via
TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 65 +--
2 files changed, 49 inse
We can use the routines just added for user-only to emit
unaligned accesses in softmmu mode too.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 91 ++-
1 file changed, 51 insertions(+), 40 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc
Hi Peter,
On 1/8/22 12:40 AM, Peter Maydell wrote:
On Fri, 3 Dec 2021 at 23:34, Gavin Shan wrote:
This supports virtio-mem-pci device on "virt" platform, by simply
following the implementation on x86.
* This implements the hotplug handlers to support virtio-mem-pci
device hot-add,
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 -
tcg/arm/tcg-target.c.inc | 83 +++-
2 files changed, 81 insertions(+), 4 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 1dd4cd5377..27c27a1f14 100644
--- a/tcg/a
Fill in target_mcontext_t to match the FreeBSD mcontex_t. Also tag the
current size of mcontext and ucontext to enable size checking for i386.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/i386/target_arch_signal.h | 46 ++
1 file changed, 46
Emit all constants that can be loaded in exactly one insn.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 76fb1dada0..8741fd
Reserve a register for the guest_base using aarch64 for reference.
By doing so, we do not have to recompute it for every memory load.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
dif
This is now always true, since we require armv6.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 3 +--
tcg/arm/tcg-target.c.inc | 35 ++-
2 files changed, 7 insertions(+), 31 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
Create a place-holder signal.c file for each of the architectures that
are currently built. In the future, some code that's currently inlined
in target_arch_signal.h will live here.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/i386/signal.c | 1 +
bsd-user/x86_64/sig
We will shortly allow the use of unaligned memory accesses,
and these require proper alignment. Use get_alignment_bits
to verify and remove USING_SOFTMMU.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
From: Frédéric Pétrot
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
Message-id: 20220106210108.138226-13-
Based-on: <20220104021543.396571-1-richard.hender...@linaro.org>
("[PATCH v4 0/7] Unaligned access for user only")
Changes from v3:
* Rebase on master, which has some patches applied.
* Drop support for armv4 and armv5.
* Drop code to emit ldm/stm for aligned trapping insns.
Previously, I a
From: Frédéric Pétrot
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by:
These sequences are inexpensive to test. Maxing out at three insns
results in the same space as a load plus the constant pool entry.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 44 +++
1 file changed, 44 insertions(+)
diff --git a/tcg/mi
This is now always true, since we require armv6.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 1 -
tcg/arm/tcg-target.c.inc | 192 ++-
2 files changed, 27 insertions(+), 166 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-tar
From: Frédéric Pétrot
Get function to retrieve the 64 top bits of a register, stored in the gprh
field of the cpu state. Set function that writes the 128-bit value at once.
The access to the gprh field can not be protected at compile time to make
sure it is accessed only in the 128-bit version of
This vastly reduces the size of code generated for 64-bit addresses.
The code for exit_tb, for instance, where we load a (tagged) pointer
to the current TB, goes from
0x400aa9725c: li v0,64
0x400aa97260: dsll v0,v0,0x10
0x400aa97264: ori v0,v0,0xaa9
0x400aa97268: dsll v0,v0,
These addresses are often loaded by the qemu_ld/st slow path,
for loading the retaddr value.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 13 +
1 file changed, 13 insertions(+)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index e967f62869..a
From: Alistair Francis
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the f
No functional change; just moving the saved reserved regs to the end.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.h | 2 +-
tcg/mips/tcg-target.c.inc | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcg/mips/tcg-target
From: Frédéric Pétrot
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu
Repeated calls to a single helper are common -- especially
the ones for softmmu memory access. Prefer the constant pool
to longer sequences to increase sharing.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
From: Alistair Francis
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id: 20211220064916.1
From: Frédéric Pétrot
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Althou
This is kinda sorta the opposite of the other tcg hosts, where
we get (normal) alignment checks for free with host SIGBUS and
need to add code to support unaligned accesses.
Fortunately, the ISA contains pairs of instructions that are
used to implement unaligned memory accesses. Use them.
Signed
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id: 20211220064916.107241-2-alistair.fran...@opensource.wdc.com
---
target/riscv/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/translate.c b/tar
Based-on: <20220104021543.396571-1-richard.hender...@linaro.org>
("[PATCH v4 0/7] Unaligned access for user only")
Changes from v3:
* Rebase on master, which has some patches applied.
r~
Richard Henderson (12):
tcg/mips: Support unaligned access for user-only
tcg/mips: Support unaligned
From: Philipp Tomsich
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
them to be enabled by default, the comment about experimental
extensions was kept in place above them. This moves it down a few
lines to only cover experimental extensions.
References: 0643c12e4b ("target/
>From armv6, the architecture supports unaligned accesses.
All we need to do is perform the correct alignment check
in tcg_out_tlb_read.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 39 ++-
1 file changed, 18 insertions(+), 21 deletions(-)
Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for wired interrupts called APLIC (Advanced
> Platform Level Interrupt Controller). The APLIC is capabable of
> forwarding wired interupts to RISC-V
From: Frédéric Pétrot
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use re
Support for unaligned accesses is difficult for pre-v6 hosts.
While debian still builds for armv4, we cannot use a compile
time test, so test the architecture at runtime and error out.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 5 +
1 file changed, 5 insertions(+)
diff
From: Frédéric Pétrot
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
flo
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20220105022247.21131-2-frank.ch...@sifive.com>
Signed-off-by: Alistair F
From: Frédéric Pétrot
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
Message-id: 20220106210108.138226-7-frederic.p
From: Frédéric Pétrot
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-
From: Alistair Francis
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Message-Id: <20220105213937.1113508-6-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1
From: Frédéric Pétrot
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20220106210108.138226-16-frederic.pet...@univ-grenoble-alpes.fr
Signed-off-by: Alista
From: Frédéric Pétrot
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20220106210108.138226-3-frederic.pet...@univ-grenoble-alpes.fr
Signed-off-by
From: Frédéric Pétrot
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallba
From: Frédéric Pétrot
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
Messa
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-Id: <20220105213937.1113508-4-alistair.fran...@opensource.wdc.com>
---
hw/intc/sifive_plic.c | 55 +--
1 file changed, 11 insertions(+), 44 deletions(-)
diff --git a/hw
From: Bin Meng
Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
The v1.0 release includes the following commits:
ec5274b platform: implement K210 system reset
5487cf0 include: sbi: Simplify HSM state define names
8df1f9a lib: sbi: Use SBI_HSM_STATE_xyz defines instead of SBI_STA
From: Jim Shu
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu
Reviewed-by:
From: Frédéric Pétrot
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed
From: Frédéric Pétrot
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Me
From: Alistair Francis
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis
Reviewed-by: Anup Patel
Reviewed-by: Philippe Mathieu-Daudé
From: Frédéric Pétrot
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Rich
From: Frédéric Pétrot
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Message-Id: <20220105213937.1113508-2-alistair.fran...@opensource.wdc.com>
---
hw/intc/sifive_plic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/intc
From: Alistair Francis
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
From: Frédéric Pétrot
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
From: Alistair Francis
When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.
Currently a user can see this:
$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display
none -drive if=pflash
QEMU 6.1.
From: Nikita Shubin
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured and pmp is present, othwerwise access
should succeed.
Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is
configured)
Signed-off-by: Nikita Shubin
Re
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-Id: <20220105213937.1113508-3-alistair.fran...@opensource.wdc.com>
---
hw/intc/sifive_plic.c | 76 +++
1 file changed, 27 insertions(+), 49 deletions(-)
diff --git a/hw
From: Jim Shu
Real PDMA supports high 32-bit read/write memory access of 64-bit
register.
The following result is PDMA tested in U-Boot on Unmatched board:
1. Real PDMA allows high 32-bit read/write to 64-bit register.
=> mw.l 0x300 0x0 <= Disclaim channel 0
=> mw.l 0x3
From: Alistair Francis
The following changes since commit d70075373af51b6aa1d637962c962120e201fc98:
Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging (2022-01-07 17:24:24 -0800)
are available in the Git repository at:
g...@github.com:alistair23/qemu.g
From: Alistair Francis
We can remove the original sifive_plic_irqs_pending() function and
instead just use the sifive_plic_claim() function (renamed to
sifive_plic_claimed()) to determine if any interrupts are pending.
This requires move the side effects outside of sifive_plic_claimed(),
but as
On 1/7/22 5:03 PM, Michael S. Tsirkin wrote:
Changes from v2:
- fix fallout from attempts to fix up virtio mem prealloc patches
Changes from v1:
- mingw build fixes
- added TPM patches which got acks meanwhile
Big changes that were tagged originally but did not make the cut:
- SRIOV/nvme (not s
From: Hao Wu
SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
interface that reports AMD SoC's Ttcl (normalized temperature),
and resembles a typical 8-pin remote temperature sensor's I2C interface
to BMC.
This patch implements a basic AMD SB-TSI sensor that is
compatible with the
在 2022/1/8 上午4:54, Richard Henderson 写道:
On 1/7/22 3:27 AM, Weiwei Li wrote:
+#define REQUIRE_EVEN(ctx, reg) do { \
+ if (ctx->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \
+ (reg & 0x1)) { \
+ return false; \
+ } \
+} while (0)
Parenthesis around reg.
+ REQUIRE_EVEN(ctx
From: Stefan Berger
The updated TPM related tables have the following additions:
Device (TPM)
{
Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware
ID
+ Name (_STR, "TPM 2.0 Device") // _STR: Description String
+ Name (_UID, One) // _UID: Unique ID
From: Stefan Berger
Add missing TPM device identification objects _STR and _UID. They will
appear as files 'description' and 'uid' under Linux sysfs.
Following inspection of sysfs entries for hardware TPMs we chose
uid '1'.
Cc: Shannon Zhao
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Ani Si
From: Thomas Huth
The virtio-balloon-stats documentation might be useful for people that
are implementing software that talks to QEMU via QMP, so this should
reside in the docs/interop/ directory. While we're at it, also convert
the file to restructured text and mention it in the MAINTAINERS file
From: Daniil Tatianin
vhost_dev_init calls vhost_dev_cleanup on error, which closes vhostfd,
don't double close it.
Signed-off-by: Daniil Tatianin
Message-Id: <20211129132358.1110372-2-d-tatia...@yandex-team.ru>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/scsi/vh
From: Igor Mammedov
if QEMU is started with used provided SLIC table blob,
-acpitable sig=SLIC,oem_id='CRASH
',oem_table_id="ME",oem_rev=2210,asl_compiler_id="",asl_compiler_rev=,data=/dev/null
it will assert with:
hw/acpi/aml-build.c:61:build_append_padded_str: assertion faile
From: Thomas Huth
When running "qemu-system-x86_64 -M pc,help" I noticed that some
properties were still missing their description. Add them now so
that users get at least a slightly better idea what they are all
about.
Signed-off-by: Thomas Huth
Message-Id: <20211206134255.94784-1-th...@redhat
From: David Hildenbrand
Let's synchronize the new feature flag, available in Linux since
v5.16-rc1.
Reviewed-by: Michal Privoznik
Signed-off-by: David Hildenbrand
Message-Id: <20211217134039.29670-2-da...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
incl
在 2022/1/8 上午4:48, Richard Henderson 写道:
On 1/7/22 3:27 AM, Weiwei Li wrote:
@@ -342,6 +342,11 @@ static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (ctx->ext_zfinx) {
+ return;
+ }
+
if (ctx->msta
From: Stefan Berger
Replace existing TPM related tables, that are about to change, with
empty files.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Ani Sinha
Signed-off-by: Stefan Berger
Acked-by: Ani Sinha
Message-id: 20211223022310.575496-2-stef...@linux.ibm.com
Message-Id: <20220104175806.
From: David Hildenbrand
Let's minimize the number of global variables to prepare for
os_mem_prealloc() getting called concurrently and make the code a bit
easier to read.
The only consumer that really needs a global variable is the sigbus
handler, which will require protection via a mutex in the
From: Ani Sinha
All work related to VIOT tables are being done by Jean. Adding him as the
maintainer for acpi VIOT table code in qemu.
Signed-off-by: Ani Sinha
Message-Id: <20211213045924.344214-1-...@anisinha.ca>
Acked-by: Jean-Philippe Brucker
Reviewed-by: Michael S. Tsirkin
Signed-off-by:
From: Daniil Tatianin
vhost_dev_init calls vhost_dev_cleanup in case of an error during
initialization, which zeroes out the entire vsc->dev as well as the
vsc->dev.vqs pointer. This prevents us from properly freeing it in free_vqs.
Keep a local copy of the pointer so we can free it later.
Signe
From: Daniil Tatianin
In case of an error during initialization in vhost_dev_init, vhostfd is
closed in vhost_dev_cleanup. Remove close from err_virtio as it's both
redundant and causes a double close on vhostfd.
Signed-off-by: Daniil Tatianin
Message-Id: <20211129125204.1108088-1-d-tatia...@ya
From: Stefan Hajnoczi
Packed Virtqueues wrap used_idx instead of letting it run freely like
Split Virtqueues do. If the used ring wraps more than once there is no
way to compare vq->signalled_used and vq->used_idx in
virtio_packed_should_notify() since they are modulo vq->vring.num.
This causes
From: Ani Sinha
Get rid of the static variable that keeps track of whether hotplug has been
disabled on the root pci bus. Simply use qbus_is_hotpluggable() api to
perform the same check. This eliminates additional if conditional and
simplifies the function.
Signed-off-by: Ani Sinha
Message-Id:
From: David Hildenbrand
Let's limit the number of threads to something sane, especially that
- We don't have more threads than the number of pages we have
- We don't have threads that initialize small (< 64 MiB) memory
Reviewed-by: Pankaj Gupta
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by:
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20211227193120.1084176-5-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
tests/data/acpi/q35/FACP.slic | Bin 244 -> 244
From: David Hildenbrand
Let's prepare touch_all_pages() for returning differing errors. Return
an error from the thread and report the last processed error.
Translate SIGBUS to -EFAULT, as a SIGBUS can mean all different kind of
things (memory error, read error, out of memory). When allocating m
From: Jason Wang
When scalable mode is enabled, the passthrough more is not determined
by the context entry but PASID entry, so switch to use the logic of
vtd_dev_pt_enabled() to determine the passthrough mode in
vtd_do_iommu_translate().
Signed-off-by: Jason Wang
Message-Id: <20220105041945.13
From: Igor Mammedov
When user uses '-acpitable' to add SLIC table, some ACPI
tables (FADT) will change its 'Oem ID'/'Oem Table ID' fields to
match that of SLIC. Test makes sure thati QEMU handles
those fields correctly when SLIC table is added with
'-acpitable' option.
Signed-off-by: Igor Mammed
From: David Hildenbrand
Let's sense support and use it for preallocation. MADV_POPULATE_WRITE
does not require a SIGBUS handler, doesn't actually touch page content,
and avoids context switches; it is, therefore, faster and easier to handle
than our current approach.
While MADV_POPULATE_WRITE is
From: Andy Pei
Turn on pre-defined feature VIRTIO_BLK_F_SIZE_MAX for virtio blk device to
avoid guest DMA request sizes which are too large for hardware spec.
Signed-off-by: Andy Pei
Message-Id: <1641202092-149677-1-git-send-email-andy@intel.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-
From: David Hildenbrand
With VIRTIO_MEM_F_UNPLUGGED_INACCESSIBLE, we signal the VM that reading
unplugged memory is not supported. We have to fail feature negotiation
in case the guest does not support VIRTIO_MEM_F_UNPLUGGED_INACCESSIBLE.
First, VIRTIO_MEM_F_UNPLUGGED_INACCESSIBLE is required to
From: Eduardo Habkost
The i440fx and Q35 machine types are both hardcoded to use the
legacy SMBIOS 2.1 (32-bit) entry point. This is a sensible
conservative choice because SeaBIOS only supports SMBIOS 2.1
EDK2, however, can also support SMBIOS 3.0 (64-bit) entry points,
and QEMU already uses thi
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20211227193120.1084176-3-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
tests/data/acpi/q35/FACP.slic | Bin 0 -> 244 by
From: Eduardo Habkost
This prepares for exposing the SMBIOS entry point type as a
machine property on x86.
Based on a patch from Daniel P. Berrangé.
Signed-off-by: Daniel P. Berrangé
Signed-off-by: Eduardo Habkost
Message-Id: <20211026151100.1691925-3-ehabk...@redhat.com>
Reviewed-by: Michael
From: Eduardo Habkost
Rename the enums to match the naming style used by QAPI, and to
use "32" and "64" instead of "20" and "31". This will allow us
to more easily move the enum to the QAPI schema later.
About the naming choice: "SMBIOS 2.1 entry point"/"SMBIOS 3.0
entry point" and "32-bit entr
From: David Hildenbrand
Temporarily modifying the SIGBUS handler is really nasty, as we might be
unlucky and receive an MCE SIGBUS while having our handler registered.
Unfortunately, there is no way around messing with SIGBUS when
MADV_POPULATE_WRITE is not applicable or not around.
Let's forwar
From: David Hildenbrand
Set the new default to "auto", keeping it set to "off" for compat
machines. This property is only available for x86 targets.
Reviewed-by: Michal Privoznik
Reviewed-by: Pankaj Gupta
Signed-off-by: David Hildenbrand
Message-Id: <20211217134039.29670-4-da...@redhat.com>
R
From: Frederic Barrat
Skip triggering an LSI when the AER root error status is updated if no
LSI is defined for the device. We can have a root bridge with no LSI,
MSI and MSI-X defined, for example on POWER systems.
Signed-off-by: Frederic Barrat
Message-Id: <2026170133.724751-4-fbar...@lin
From: David Hildenbrand
Let's simplify the case when we only want a single thread and don't have
to mess with signal handlers.
Reviewed-by: Pankaj Gupta
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Michal Privoznik
Signed-off-by: David Hildenbrand
Message-Id: <20211217134611.31172-6-da...@re
From: Frederic Barrat
Move the pci_intx() definition to the PCI header file, so that it can
be called from other PCI files. It is used by the next patch.
Signed-off-by: Frederic Barrat
Message-Id: <2026170133.724751-3-fbar...@linux.ibm.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Mi
From: David Hildenbrand
For scarce memory resources, such as hugetlb, we want to be able to
prealloc such memory resources in order to not crash later on access. On
simple user errors we could otherwise easily run out of memory resources
an crash the VM -- pretty much undesired.
For ordinary mem
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