On Tue, 18 Jan 2022 09:15:42 -0800
Patrick Venture wrote:
> On Tue, Jan 11, 2022 at 5:13 AM Igor Mammedov wrote:
>
> > On Thu, 6 Jan 2022 14:33:16 -0800
> > Patrick Venture wrote:
> >
[...]
> > > diff --git a/qemu-options.hx b/qemu-options.hx
> > > index ec90505d84..3c51b6cf8f 100644
> > >
On Tue, Jan 18, 2022 at 7:18 PM Anup Patel wrote:
>
> Now that all RISC-V machines can use OpenSBI BIN images, we remove
> OpenSBI ELF images and also exclude these images from BIOS build.
>
> Signed-off-by: Anup Patel
> ---
> pc-bios/meson.build| 2 --
> pc-bios/op
On Tue, Jan 18, 2022 at 7:18 PM Anup Patel wrote:
>
> Currently, we have to use OpenSBI firmware ELF as bios for the spike
> machine because the HTIF console requires ELF for parsing "fromhost"
> and "tohost" symbols.
>
> The latest OpenSBI can now optionally pick-up HTIF register address
> from H
On Tue, Jan 18, 2022 at 7:18 PM Anup Patel wrote:
>
> Now that RISC-V Spike machine can use BIN BIOS images, we remove
> the macros used for ELF BIOS image names.
>
> Signed-off-by: Anup Patel
> ---
> hw/riscv/spike.c| 4 ++--
> include/hw/riscv/boot.h | 2 --
> 2 files changed, 2 insert
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 90f78eca65..c6b2407a06 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -584,7 +584,7
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file
Signed-off-by: LIU Zhiwei
Acked-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe58ccaeae..55635d68d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,7 +
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 ++-
target/ri
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/ri
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/vector_helper.c | 7 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6c740b92c1..
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9be2820d2b..c00a82022e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 9 +++--
target/riscv
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c| 3 +--
target/riscv/csr.c | 13 -
target/riscv/machine.c
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 4
target/riscv/cpu_helper.c | 43 +++
target/riscv/csr.c| 19 +
target/risc
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b11d92b51b..90f78eca65 100644
--- a/target/riscv/csr
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 32
1 file changed, 8 insertions(+),
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
.../riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc | 5 ++--
target/riscv/ins
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 12
target/riscv/op_helper.c| 3 ++-
2 files changed, 10 insertions(+), 5 deleti
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 8 ++---
target/riscv/gdbstub.c | 71 +++---
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target/risc
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
target/riscv/translate.c| 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.
Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration loa
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 19 +++
target/riscv/pmp.c | 12
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a9e7ac903b.
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-
In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
The patch set v7 has been tested by running rv64 Linux with
rv32 rootfs in compat mode. You can almost follow the test [1]
given by GuoRen, except using the branch
Hello Daniel,
On Thu, Jan 13, 2022 at 7:53 AM Daniel P. Berrangé wrote:
>
> On Thu, Jan 06, 2022 at 07:13:38PM -0300, Leonardo Bras wrote:
> > Add flags to io_writev and introduce io_flush as optional callback to
> > QIOChannelClass, allowing the implementation of zero copy writes by
> > subclass
On 1/17/22 03:45, Peter Maydell wrote:
On Fri, 7 Jan 2022 at 07:29, Alexey Kardashevskiy wrote:
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral chan
On Wed, Jan 19, 2022 at 1:36 PM LIU Zhiwei wrote:
>
>
> On 2022/1/19 上午11:24, Alistair Francis wrote:
> > On Thu, Jan 13, 2022 at 9:50 PM LIU Zhiwei wrote:
> >> Signed-off-by: LIU Zhiwei
> > I'm not clear on why this is better?
>
> Current xlen has been used in helper functions and many other pl
On 2022/1/19 上午11:24, Alistair Francis wrote:
On Thu, Jan 13, 2022 at 9:50 PM LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
I'm not clear on why this is better?
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so tha
On Thu, Jan 13, 2022 at 10:23 PM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d944ee9caf..1037c
On Thu, Jan 13, 2022 at 10:20 PM LIU Zhiwei wrote:
>
> When sew <= 32bits, not need to extend scalar reg.
> When sew > 32bits, if xlen is less that sew, we should sign extend
> the scalar register, except explicitly specified by the spec.
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Franc
On Thu, Jan 13, 2022 at 9:50 PM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
I'm not clear on why this is better?
Alistair
> ---
> target/riscv/cpu.c| 1 +
> target/riscv/cpu.h| 31 +++
> target/riscv/cpu_helper.c | 34 ++
On Thu, Jan 13, 2022 at 9:45 PM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
> target/riscv/translate.c| 4 +---
> 2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --g
On Thu, Jan 13, 2022 at 9:41 PM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 19 +++
> target/riscv/pmp.c | 12
> 2 files changed, 23 insertions(+), 8 deletio
On Wed, Jan 5, 2022 at 1:09 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This adds initial support for the native debug via the Trigger Module,
> as defined in the RISC-V Debug Specification [1].
Doesn't this mean we are just supporting the Sdtrig extension?
>
> Only "Address / Data Match" trigger
On 2022/1/18 下午7:29, Weiwei Li wrote:
在 2022/1/18 下午7:15, Guo Ren 写道:
On Tue, Jan 18, 2022 at 4:51 PM Anup Patel
wrote:
On Tue, Jan 18, 2022 at 2:16 PM Guo Ren wrote:
On Tue, Jan 18, 2022 at 11:32 AM Anup Patel
wrote:
On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li
wrote:
From: Guo Ren
Hi
On Wed, Jan 5, 2022 at 1:15 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This adds debug CSR read/write support to the RISC-V CSR RW table.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v3:
> - add riscv_trigger_init(), moved from patch #1 to this patch
>
> target/riscv/debug.h | 2 ++
> targe
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify detailed version history information and also change
some related comments, which make SGX related comments clearer.
Signed-off-by: Yang Zhong
---
qapi/machine.json | 4 ++--
qapi/misc-target.json | 14 +-
2
On Tue, Jan 18, 2022 at 05:45:09PM -0300, Leonardo Bras Soares Passos wrote:
> Hello Peter,
>
> On Thu, Jan 13, 2022 at 3:28 AM Peter Xu wrote:
> >
> > On Thu, Jan 06, 2022 at 07:13:38PM -0300, Leonardo Bras wrote:
> > > diff --git a/io/channel.c b/io/channel.c
> > > index e8b019dc36..904855e16e
On Wed, Jan 19, 2022 at 11:19 AM Alistair Francis wrote:
>
> On Wed, Jan 19, 2022 at 9:22 AM Philipp Tomsich
> wrote:
> >
> > Alistair,
> >
> > Some of us (the merit almost exclusively goes to Kito) have been
> > working towards a similar policy for GCC/binutils and LLVM.
> > This currently lives
On Wed, Jan 19, 2022 at 9:22 AM Philipp Tomsich
wrote:
>
> Alistair,
>
> Some of us (the merit almost exclusively goes to Kito) have been
> working towards a similar policy for GCC/binutils and LLVM.
> This currently lives in:
>https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/
On Tue, Jan 18, 2022 at 06:05:48PM +0100, Thomas Huth wrote:
> The fdt version test in meson.build uses a function from libfdt v1.4.7,
> but we require version 1.5.1 nowadays. Thus use a function that has
> been introduced in that version instead.
>
> Resolves: https://gitlab.com/qemu-project/qemu
On Tue, Jan 18, 2022 at 5:01 AM Daniel P. Berrangé wrote:
>
> With the current 'qmp-shell' tool developers must first spawn QEMU with
> a suitable -qmp arg and then spawn qmp-shell in a separate terminal
> pointing to the right socket.
>
> With 'qmp-shell-wrap' developers can ignore QMP sockets en
On Tue, 18 Jan 2022 19:41:56 +
Peter Maydell wrote:
Hi Peter, Alex,
thanks for the heads up!
> On Tue, 18 Jan 2022 at 17:42, Alex Bennée wrote:
> >
> >
> > Peter Maydell writes:
> >
> > > I've been working on the ITS to add support for the GICv4 functionality.
> > > In the course of tha
Alistair,
Some of us (the merit almost exclusively goes to Kito) have been
working towards a similar policy for GCC/binutils and LLVM.
This currently lives in:
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17
A few comments & a question below.
Thanks,
Philipp.
On Tue, 18
On Fri, Jan 14, 2022 at 6:22 AM Philipp Tomsich
wrote:
>
> This adds the decoder and translation for the XVentanaCondOps custom
> extension (vendor-defined by Ventana Micro Systems), which is
> documented at
> https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/vent
On Wed, Jan 19, 2022 at 3:42 AM Thomas Huth wrote:
>
> The fdt version test in meson.build uses a function from libfdt v1.4.7,
> but we require version 1.5.1 nowadays. Thus use a function that has
> been introduced in that version instead.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issue
On Tue, Jan 18, 2022 at 9:18 PM Anup Patel wrote:
>
> Now that RISC-V Spike machine can use BIN BIOS images, we remove
> the macros used for ELF BIOS image names.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/spike.c| 4 ++--
> include/hw/riscv
On Tue, Jan 18, 2022 at 9:22 PM Anup Patel wrote:
>
> Now that all RISC-V machines can use OpenSBI BIN images, we remove
> OpenSBI ELF images and also exclude these images from BIOS build.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
In future it's best to not send a large binar
;
> are available in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-ppc-20220118
>
> for you to fetch changes up to ba49190107ee9803fb2f336b15283b457384b178:
>
> ppc/pnv: Remove PHB4 version property (2022-01-18 12:56:31 +0100)
>
> ---
On Tue, Jan 18, 2022 at 9:24 PM Anup Patel wrote:
>
> Currently, we have to use OpenSBI firmware ELF as bios for the spike
> machine because the HTIF console requires ELF for parsing "fromhost"
> and "tohost" symbols.
>
> The latest OpenSBI can now optionally pick-up HTIF register address
> from H
On Thu, Jan 13, 2022 at 4:04 PM Kyle Evans wrote:
> On Thu, Jan 13, 2022 at 2:53 PM Peter Maydell
> wrote:
> >
> > On Thu, 13 Jan 2022 at 20:29, Peter Maydell
> wrote:
> > >
> > > On Sun, 9 Jan 2022 at 16:44, Warner Losh wrote:
> > > >
> > > > Force delivering a signal and generating a core fi
On Tue, Jan 18, 2022 at 11:50 AM wrote:
>
> From: Frank Chang
>
> In RVV v1.0 spec, several Zve* vector extensions for embedded processors
> are defined in Chapter 18.2:
> https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
>
> This patchset i
Hi Francisco!
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> An option on real hardware when embedding a DMA engine into a peripheral
> is to make the peripheral control the engine through a custom DMA control
> (hardware) interface between the two. Software drivers in this scenario
> confi
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> Add a model of Versal's PMC SLCR (system-level control registers).
>
> Signed-off-by: Francisco Iglesias
> Signed-off-by: Edgar E. Iglesias
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/misc/meson.build
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> Add in the missing includes in the header for being able to build the DMA
> model when reusing it.
>
> Signed-off-by: Francisco Iglesias
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/hw/dma/xlnx_csu_dma.h | 5 +
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
>
> Signed-off-by: Francisco Iglesias
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c| 2 +-
> hw/arm/xlnx-versal.c |
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> Connect Versal's PMC SLCR (system-level control registers) model.
>
> Signed-off-by: Francisco Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 71
> +++-
> include/hw/arm/xln
Hi Francisco,
Impressive beast :-) Nicely done. Maybe I would have split it in a
couple of commits to ease review. Also, you can use
[diff]
orderFile = scripts/git.orderfile
as a local config in your QEMU git so that files are placed in a
sensible order (.h files will come first), which eas
Hello Peter,
On Thu, Jan 13, 2022 at 3:28 AM Peter Xu wrote:
>
> On Thu, Jan 06, 2022 at 07:13:38PM -0300, Leonardo Bras wrote:
> > diff --git a/io/channel.c b/io/channel.c
> > index e8b019dc36..904855e16e 100644
> > --- a/io/channel.c
> > +++ b/io/channel.c
> > @@ -67,12 +67,13 @@ ssize_t qio_ch
The vq setup code is repeated several times and can be
easily factorized.
Signed-off-by: Eric Auger
Reviewed-by: Thomas Huth
---
tests/qtest/vhost-user-blk-test.c | 33 +++
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/tests/qtest/vhost-user-blk-tes
Hi Paolo,
On 1/15/22 5:01 PM, Paolo Bonzini wrote:
> On 1/10/22 22:19, Eric Auger wrote:
>> Up to now the virt-machine node contains a virtio-mmio node.
>> However no driver produces any PCI interface node. Hence, PCI
>> tests cannot be run with aarch64 binary.
>>
>> Add a GPEX driver node that pr
ARM does not not support hotplug on pcie.0. Add a flag on the bus
which tells if devices can be hotplugged and skip hotplug tests
if the bus cannot be hotplugged. This is a temporary solution to
enable the other pci tests on aarch64.
Signed-off-by: Eric Auger
Acked-by: Thomas Huth
---
v1 ->v2:
When run on ARM, basic and indirect tests currently fail with the
following error:
ERROR:../tests/qtest/libqos/virtio.c:224:qvirtio_wait_used_elem:
assertion failed (got_desc_idx == desc_idx): (50331648 == 0)
Bail out! ERROR:../tests/qtest/libqos/virtio.c:224: qvirtio_wait_used_elem:
assertion fai
Up to now the virt-machine node contains a virtio-mmio node.
However no driver produces any PCI interface node. Hence, PCI
tests cannot be run with aarch64 binary.
Add a GPEX driver node that produces a pci interface node. This latter
then can be consumed by all the pci tests. One of the first mot
At the moment the IO space limit is hardcoded to
QPCI_PIO_LIMIT = 0x1. When accesses are performed to a bar,
the base address of this latter is compared against the limit
to decide whether we perform an IO or a memory access.
On ARM, we cannot keep this PIO limit as the arm-virt machine
uses [
-netdev vhost-user,vhostforce is deprecated and vhostforce=on
should be used instead.
Signed-off-by: Eric Auger
Reviewed-by: Thomas Huth
---
tests/qtest/vhost-user-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/vhost-user-test.c b/tests/qtest/vhost-user-t
Up to now the virt-machine node only contains a virtio-mmio
driver node but no driver that eventually produces any pci-bus
interface.
Hence, PCI libqos tests cannot be run with aarch64 binary.
This series brings the pieces needed to be able to run PCI tests
with the aarch64 binary: a generic-pcih
On Tue, Jan 18, 2022 at 8:48 AM Christoph Muellner wrote:
>
> The RISC-V base cache management operation ISA extension has been
> ratified [1]. This patch adds support for the defined instructions
> and CSRs.
>
> [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
>
> Co-developed
* Juan Quintela (quint...@redhat.com) wrote:
> This patch adds counters and similar. Logic will be added on the
> following patch.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/multifd.h| 13 -
> migration/multifd.c| 22 +++
* Juan Quintela (quint...@redhat.com) wrote:
> Signed-off-by: Juan Quintela
Erm, why?
Dave
> ---
> migration/ram.h | 2 ++
> migration/ram.c | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/migration/ram.h b/migration/ram.h
> index c515396a9a..6dca396a6b 100644
> ---
* Juan Quintela (quint...@redhat.com) wrote:
> We are going to create a new function for multifd latest in the series.
^^ 'later'
Reviewed-by: Dr. David Alan Gilbert
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 12 +++
* Juan Quintela (quint...@redhat.com) wrote:
> So we use multifd to transmit zero pages.
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 32 +++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/migration/ram.c b/migration/ram.c
> index 3
* Juan Quintela (quint...@redhat.com) wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/migration.h | 3 +++
> hw/core/machine.c | 4 +++-
> migration/migration.c | 11 +++
> 3 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --gi
* Juan Quintela (quint...@redhat.com) wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
>
> ---
>
> Rename num_normal_pages to total_normal_pages (peter)
> ---
> migration/multifd.h | 8 +--
> migration/multifd-zlib.c | 8 +++
> migration/multifd-zstd.c
* Juan Quintela (quint...@redhat.com) wrote:
> This implements the zero page dection and handling.
>
> Signed-off-by: Juan Quintela
>
> ---
>
> Add comment for offset (dave)
> ---
> migration/multifd.h | 4
> migration/multifd.c | 36 ++--
> 2 files change
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/memory-api-20220118
>
> for you to fetch changes up to 9d696cd50442327fd71ec7309e7b0c6fee693b1d:
>
> docs/devel: add some clari
The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.
We're using the BookE Exception Syndrome Register which is different
from the 405.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 16
1 file changed, 16 deletions(-)
Remove references to BookE.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 2efec6d13b..a22b783ecb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
On Tue, 18 Jan 2022 at 17:42, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > I've been working on the ITS to add support for the GICv4 functionality.
> > In the course of that I found a handful of bugs in it and also some
> > places where the code benefited from refactoring to make it a bet
The 405 has no DSISR or DAR, so convert the trace entry to
trace_ppc_excp_print.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 84ec7e094a..e4e513322c 100644
-
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e4e513322c..13674a102f 100644
--- a
405 has no MSR_HV and EPR is BookE only so we can remove it all.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/excp_helper.c | 37 -
1 file changed, 37 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
inde
There's no sc 1.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8fae8aa0be..9a6f8365d6 100644
--- a/target/ppc/excp_helper.c
+++ b/targe
Hello all,
I just want to pose the following problem:
There is a kernel module for a non-native architecture, say, arch 1. For
performance reasons, the rest of all of the software needs to run natively
on a different arch, arch 2. Is there any way to perhaps run multiple QEMU
instances for the di
changes from v1:
- New patch that renames MSR_POW to MSR_WE for the 405.
- New patch that adds just MSR_ME to the msr_mask.
- New patches to cleanup exceptions I missed the first time around.
- Dropped the patch that added all the missing MSR bits. We have an
issue when two different MSR bits
In powerpc_excp_40x the Critical exception is now for 405 only, so we
can remove the BookE and G2 blocks.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/excp_helper.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_he
powerpc_excp_40x applies only to the 405, so remove HV code and
references to BookE.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/excp_helper.c | 26 ++
1 file changed, 2 insertions(+), 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/tar
The following changes since commit 6621441db50d5bae7e34dbd04bf3c57a27a71b32:
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-20220115'
into staging (2022-01-16 20:12:23 +)
are available in the Git repository at:
https://github.com/stsquad/qemu.git tags/pull-for-7.0-180
There is no DSISR in the 405. It uses DEAR which we already set
earlier at ppc_cpu_do_unaligned_access.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 9a6f8365d6..d263f2
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 2 +-
2 files changed,
* Juan Quintela (quint...@redhat.com) wrote:
> We are only sending normal pages through multifd channels.
> Later on this series, we are going to also send zero pages.
> We are going to dectect if a page is zero or non zero in the multifd
^ typo
> channel thread, not on the main
The current Debug exception dispatch is the BookE one, so it is
different from the 405. We effectively don't support the 405 Debug
exception.
This patch removes the BookE code and moves the DEBUG into the "not
implemented" block.
Note that there is in theory a functional change here since we now
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e637
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV or MSR_LE;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Interrupts Little Endian;
- No Alternate Interrupt
Introduce a new powerpc_excp function specific for 40x CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 474 +++
1 file changed, 474 insertions(+)
diff --git a/
18.01.2022 19:37, Hanna Reitz wrote:
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
FleecingState represents state shared between copy-before-write filter
and upcoming fleecing block driver.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/fleecing.h | 135 +
On Tue, Jan 18, 2022 at 7:13 AM Peter Maydell wrote:
>
> On Mon, 17 Jan 2022 at 20:35, John Snow wrote:
> > I do expect this to print more information on failure than it
> > currently is, though (bug somewhere in machine.py, I think).
> > Can you please try applying this temporary patch and runni
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