[PULL 11/42] target/ppc: booke: Watchdog Timer interrupt

From: Fabiano Rosas Remove the switch as this function applies to BookE only. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-11-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(

[PULL 35/42] target/ppc: 7xx: Set SRRs directly in exception code

From: Fabiano Rosas The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas Message-Id: <20220204173430.1457358-11-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 13 ++---

[PATCH v6 07/11] 9p: darwin: *xattr_nofollow implementations

From: Keno Fischer This implements the darwin equivalent of the functions that were moved to 9p-util(-linux) earlier in this series in the new 9p-util-darwin file. Signed-off-by: Keno Fischer [Michael Roitzsch: - Rebase for NixOS] Signed-off-by: Michael Roitzsch Signed-off-by: Will Cohen ---

[PULL 28/42] target/ppc: Simplify powerpc_excp_7xx

From: Fabiano Rosas Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptio

[PULL 23/42] target/ppc: 6xx: System Reset interrupt cleanup

From: Fabiano Rosas There is no HV support in the 6xx. Signed-off-by: Fabiano Rosas Message-Id: <20220203200957.1434641-10-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 18 ++ 1 file changed, 2 insertions(+), 16 deletions(-) diff --git

[PULL 08/42] target/ppc: booke: External interrupt cleanup

From: Fabiano Rosas There is no LPES0 in BookE and no MSR_HV. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-8-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 33 - 1 file changed, 33 deletions(-) diff --

[PULL 24/42] target/ppc: 6xx: Software TLB exceptions cleanup

From: Fabiano Rosas This code applies only to the 6xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas Message-Id: <20220203200957.1434641-11-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 31 +++ 1 fi

[PULL 17/42] target/ppc: Simplify powerpc_excp_6xx

From: Fabiano Rosas Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptio

[PULL 03/42] target/ppc: Simplify powerpc_excp_booke

From: Fabiano Rosas Differences from the generic powerpc_excp code: - No MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - SPEU needs special handling; - Big endian only; - Both 64 and 32 bits; - No System call vectored; -

[PULL 22/42] target/ppc: 6xx: System Call exception cleanup

From: Fabiano Rosas There is no Hypervisor mode in the 6xx CPUs. Signed-off-by: Fabiano Rosas Message-Id: <20220203200957.1434641-9-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 21 ++--- 1 file changed, 2 insertions(+), 19 deletions(-)

[PULL 29/42] target/ppc: 7xx: Machine Check exception cleanup

From: Fabiano Rosas There's no MSR_HV in the 7xx. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas Message-Id: <20220204173430.1457358-5-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 24 1 file changed, 24 deletions

[PULL 09/42] target/ppc: booke: Alignment interrupt cleanup

From: Fabiano Rosas BookE has no DSISR or DAR. The proper registers ESR and DEAR were already set at this point. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-9-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 7 --- 1 file changed,

[PULL 26/42] target/ppc: Merge 7x5 and 7x0 exception model IDs

From: Fabiano Rosas Since we've split the exception code by exception model, the exception model IDs are becoming less useful. These two can be merged. Signed-off-by: Fabiano Rosas Message-Id: <20220204173430.1457358-2-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu-

[PULL 21/42] target/ppc: 6xx: Program exception cleanup

From: Fabiano Rosas There's no ESR in the 6xx CPUs. Signed-off-by: Fabiano Rosas Message-Id: <20220203200957.1434641-8-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/p

[PULL 13/42] target/ppc: Fix radix logging

ppc_radix64_partition_scoped_xlate() logs the host page protection bits variable but it is uninitialized. The value is set later on in ppc_radix64_check_prot(). Remove the output. Fixes: Coverity CID 1468942 Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Message-Id: <20220203142145.13017

[PULL 04/42] target/ppc: booke: Critical exception cleanup

From: Fabiano Rosas Remove 40x and G2 code. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-4-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 17 ++--- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/target/ppc/

[PULL 05/42] target/ppc: booke: Machine Check cleanups

From: Fabiano Rosas There's no MSR_HV in BookE. Also remove 40x code. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-5-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 29 ++--- 1 file changed, 6 insertions(+), 23

[PULL 25/42] target/ppc: 6xx: Set SRRs directly in exception code

From: Fabiano Rosas The 6xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas Message-Id: <20220203200957.1434641-12-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 13 ++---

[PULL 00/42] ppc queue

s/pull-ppc-20220210 for you to fetch changes up to 10717c26dbe1c138ba6af6d09a3bb9958d4fe3f2: spapr/vof: Install rom and nvram binaries (2022-02-09 09:08:56 +0100) ppc-7.0 queue * Exception model rework (Fabiano) * Unused CPU mode

[PULL 33/42] target/ppc: 7xx: System Reset cleanup

From: Fabiano Rosas Thre is no HV support in the 7xx. Signed-off-by: Fabiano Rosas Message-Id: <20220204173430.1457358-9-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 18 ++ 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/

[PULL 07/42] target/ppc: booke: Instruction storage exception cleanup

From: Fabiano Rosas The SRR1 should be set to the MSR value. There are no diagnostic bits in the SRR1 for BookE. Note that this fixes a bug where MSR_GS would be set and Linux would go into KVM code when there's no KVM guest. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-7-f

[PULL 01/42] target/ppc: Remove 440x4 CPU

From: Fabiano Rosas This CPU was partially removed due to lack of support in 2017 by commit aef7796057 ("ppc: remove non implemented cpu models"). Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20220128221611.1221715-1-faro...@linux.ibm.com> Signed-off-by: Cédric Le Go

[PULL 02/42] target/ppc: Introduce powerpc_excp_booke

From: Fabiano Rosas Introduce a new powerpc_excp function specific for BookE CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-2-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- ta

[PULL 36/42] target/ppc: Remove powerpc_excp_legacy

From: Fabiano Rosas Now that all CPU families have their own separate exception dispatching code we can remove powerpc_excp_legacy. Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20220207183036.1507882-2-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- targ

[PULL 32/42] target/ppc: 7xx: System Call exception cleanup

From: Fabiano Rosas Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode. Signed-off-by: Fabiano Rosas Message-Id: <20220204173430.1457358-8-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- targ

[PATCH v3 36/37] target/ppc: Implement xs{max,min}cqp

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 2 ++ target/ppc/helper.h | 2 ++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 2 ++ 4 files changed, 9 insertions(+)

[PATCH v3 35/37] target/ppc: Refactor VSX_MAX_MINC helper

From: Víctor Colombo Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for xs{max,min}cqp implementation. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/ta

[PATCH v3 11/37] target/ppc: Implement Vector Compare Equal Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpequq Vector Compare Equal Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 43 + 2 files changed, 44 insertions(+)

[PATCH v3 31/37] target/ppc: Refactor VSX_SCALAR_CMP_DP

From: Víctor Colombo Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and prepare the helper to be used for quadword comparisons. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 31 ++- 1 file changed, 14 inse

[PULL 14/42] target/ppc: Remove PowerPC 601 CPUs

The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execute most of the instructions of the previous POWER architecture. It was found on the first Macs and IBM RS/6000 workstations. There is not

[PATCH v3 28/37] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]

From: Matheus Ferst Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision

[PULL 18/42] target/ppc: 6xx: Critical exception cleanup

From: Fabiano Rosas This only applies to the G2s, the other 6xx CPUs will not have this vector registered. Signed-off-by: Fabiano Rosas Message-Id: <20220203200957.1434641-5-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 15 --- 1 file change

[PATCH v3 12/37] target/ppc: Implement Vector Compare Greater Than Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpgtsq: Vector Compare Greater Than Signed Quadword vcmpgtuq: Vector Compare Greater Than Unsigned Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.in

[PULL 12/42] target/ppc: booke: System Reset exception cleanup

From: Fabiano Rosas There is no MSR_HV in BookE, so remove all of the HV logic. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-12-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 18 ++ 1 file changed, 2 insertions(+), 16

[PULL 06/42] target/ppc: booke: Data Storage exception cleanup

From: Fabiano Rosas There is no DSISR or DAR in BookE. Change to ESR and DEAR. Signed-off-by: Fabiano Rosas Message-Id: <20220128224018.1228062-6-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[PATCH v3 27/37] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 ++-- target/ppc/helper.h | 16 - target/ppc/insn32.decode| 22 target/ppc/translate/vsx-impl.c.inc | 56 - target/p

[PATCH v3 25/37] target/ppc: Implement xxeval

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 ++ target/ppc/int_helper.c | 42 ++ target/ppc/translate/vsx-impl.c.inc | 121 4 files changed, 172 inse

[PATCH v3 33/37] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 7 +++ target/ppc/helper.h | 6 +++--- target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 28

[PATCH v3 23/37] target/ppc: Implement xxpermx instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 target/ppc/int_helper.c | 20 target/ppc/translate/vsx-impl.c.inc | 22 ++ 4 files changed, 51

[PATCH v3 22/37] target/ppc: Move xxpermdi to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 ++ target/ppc/translate/vsx-impl.c.inc | 71 + target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 36 insertions(+), 41 deletions(-) diff --git a/target/ppc/insn3

[PATCH v3 37/37] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 +++ target/ppc/helper.h | 1 + target/ppc/insn32.decode| 11 +++--- target/ppc/translate/vsx-impl.c.inc | 31 ++

[PATCH v3 32/37] target/ppc: Implement xscmp{eq,ge,gt}qp

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 4 target/ppc/helper.h | 3 +++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 31 +

[PATCH v3 21/37] target/ppc: move xxperm/xxpermr to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 --- target/ppc/helper.h | 2 -- target/ppc/insn32.decode| 5 target/ppc/translate/vsx-impl.c.inc | 42 +++-- target/ppc/translate

[PATCH v3 20/37] target/ppc: Move xxsel to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43 - 4 files

[PATCH v3 34/37] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3

From: Víctor Colombo Also, fixes these instructions not being capitalized. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 8 target/ppc/helper.h | 8 target/ppc/translate/vsx-impl.c.inc | 30

[PATCH v3 29/37] target/ppc: Implement xvtlsbb instruction

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 7 ++ target/ppc/translate/vsx-impl.c.inc | 37 + 2 files changed, 44 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/ins

[PATCH v3 30/37] target/ppc: Remove xscmpnedp instruction

From: Víctor Colombo xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch removes this instruction as it was not in the final version of v3.0. Signed-off-by: Víctor Colombo Acked-by: Greg Kurz Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Signed-off-by: Matheus Fer

[PATCH v3 18/37] target/ppc: implement vgnb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 target/ppc/translate/vmx-impl.c.inc | 44 + 2 files changed, 49 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0a3e39f3e9..7b629

[PATCH v3 13/37] target/ppc: Implement Vector Compare Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpsq: Vector Compare Signed Quadword vcmpuq: Vector Compare Unsigned Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/translate/vmx-impl.c.inc | 45 +

[PATCH v3 26/37] target/ppc: Implement xxgenpcv[bhwd]m instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 ++ target/ppc/insn32.decode| 10 target/ppc/int_helper.c | 84 + target/ppc/translate/vsx-impl.c.inc | 29 ++ 4 files changed, 127 inse

[PATCH v3 17/37] target/ppc: implement vcntmb[bhwd]

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index bf2f3b1e0b..0

[PATCH v3 16/37] target/ppc: implement vclrrb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 43 +++-- 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 4836

[PATCH v3 06/37] target/ppc: Implement vmsumudm instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl

[PATCH v3 10/37] target/ppc: Move Vector Compare Not Equal or Zero to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 9 ++-- target/ppc/insn32.decode| 4 ++ target/ppc/int_helper.c | 50 + target/ppc/translate/vmx-impl.c.inc | 69 +++-- target/ppc/tra

[PATCH v3 24/37] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i

From: Matheus Ferst Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Signed-off-by: Matheus Ferst --- include/tcg/tcg-op-gvec.h | 22 ++ tcg/tcg-op-gvec.c | 146 ++ 2 files changed, 168 i

[PATCH v3 15/37] target/ppc: implement vclrlb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 56 + 2 files changed, 58 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index ea497ecd80..483651c

[PATCH v3 07/37] target/ppc: Move vexts[bhw]2[wd] to decodetree

From: Lucas Coutinho Move the following instructions to decodetree: vextsb2w: Vector Extend Sign Byte To Word vextsh2w: Vector Extend Sign Halfword To Word vextsb2d: Vector Extend Sign Byte To Doubleword vextsh2d: Vector Extend Sign Halfword To Doubleword vextsw2d: Vector Extend Sign Word To Doub

[PATCH v3 01/37] target/ppc: Introduce TRANS*FLAGS macros

From: Luis Pires New macros that add FLAGS and FLAGS2 checking were added for both TRANS and TRANS64. Signed-off-by: Luis Pires [ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E - Use the new macros in load/store vector insns ] Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson

[PATCH v3 19/37] target/ppc: Move vsel and vperm/vpermr to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode| 5 +++ target/ppc/int_helper.c | 13 +- target/ppc/translate/vmx-impl.c.inc | 69 ++--- target/ppc/translate/vmx-ops.

[PATCH v3 04/37] target/ppc: vmulh* instructions use gvec

From: "Lucas Mateus Castro (alqotel)" Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to use gvec instructions Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8 +- target/ppc/int_helper.c | 8 +- target/ppc/transl

[PATCH v3 08/37] target/ppc: Implement vextsd2q

From: Lucas Coutinho Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index

[PATCH v3 14/37] target/ppc: implement vstri[bh][lr]

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 target/ppc/insn32.decode| 10 + target/ppc/int_helper.c | 32 + target/ppc/translate/vmx-impl.c.inc | 24 ++ 4 file

[PATCH v3 09/37] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 30 -- target/ppc/insn32.decode| 24 target/ppc/int_helper.c | 54 - target/ppc/translate/vmx-impl.c.inc | 91 - target

[PATCH v2 1/4] hw/openrisc/openrisc_sim: Create machine state for or1ksim

This will allow us to attach machine state attributes like the device tree fdt. Signed-off-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé --- hw/openrisc/openrisc_sim.c | 30 -- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/hw/openrisc/openri

[PATCH v3 02/37] target/ppc: moved vector even and odd multiplication to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub, vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw, muleuw and vmulouw from legacy to decodetree. Implemented the instructions vmulesd, vmulosd, vmuleud, vmuloud. Signed-off-by: Lucas Mateus Castro

[PATCH v2 0/4] OpenRISC Device Tree Support

Changes since v1: - Fixed typos pointed out by Philippe - Moved usage of machine state to patch 3/4 - added config dependency on FDT This series adds device tree support for the OpenRISC SIM hardware. The simulator will generate an FDT and pass it to the kernel. For example: qemu-system-or1

[PATCH v3 03/37] target/ppc: Moved vector multiply high and low to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to decodetree Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8 target/ppc/insn32.decode| 6 ++

[PATCH v3 00/37] target/ppc: PowerISA Vector/VSX instruction batch

From: Matheus Ferst This patch series implements 5 missing instructions from PowerISA v3.0 and 40 new instructions from PowerISA v3.1, moving 62 other instructions to decodetree along the way. v3: - Dropped patch 33, which caused a regression in xxperm[r] v2: - New patch (30) to remove xscmpn

[PATCH v3 05/37] target/ppc: Implement vmsumcud instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 +++ target/ppc/translate/vmx-im

Re: [PATCH 3/4] hw/openrisc/openrisc_sim; Add support for loading a decice tree

On Thu, Feb 10, 2022 at 12:10:54PM +0100, Philippe Mathieu-Daudé wrote: > Typo "device" in subject. OK. > On 10/2/22 07:30, Stafford Horne wrote: > > Using the device tree means that qemu can now directly tell > > the kernel what hardware is configured rather than use having > > to maintain and u

[PATCH v2 3/4] hw/openrisc/openrisc_sim; Add support for loading a device tree

Using the device tree means that qemu can now directly tell the kernel what hardware is configured rather than use having to maintain and update a separate device tree file. This patch adds device tree support for the OpenRISC simulator. A device tree is built up based on the state of the configur

[PULL 1/5] tests/9pfs: use g_autofree where possible

Signed-off-by: Christian Schoenebeck Reviewed-by: Greg Kurz Message-Id: --- tests/qtest/virtio-9p-test.c | 90 +++- 1 file changed, 27 insertions(+), 63 deletions(-) diff --git a/tests/qtest/virtio-9p-test.c b/tests/qtest/virtio-9p-test.c index 41fed41de1..502e5

Re: [PATCH] vhost: fix repeated memory unmap in error paths

10.02.2022, 15:06, "Philippe Mathieu-Daudé" :On 10/2/22 12:46, Konstantin Khlebnikov wrote: Fuzzing found that on some error paths vhost_memory_unmap() is called twice or for NULL address. Let's reset pointers after unmap and ingnore unmap for NULL.  Signed-off-by: Konstantin Khlebnikov

[PATCH v2 4/4] hw/openrisc/openrisc_sim: Add support for initrd loading

The initrd passed via the command line is loaded into memory. It's location and size is then added to the device tree so the kernel knows where to find it. Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 32 +++- 1 file changed, 31 insertions(+), 1 del

[PATCH v2 2/4] hw/openrisc/openrisc_sim: Parameterize initialization

Move magic numbers to variables and enums. These will be reused for upcoming fdt initialization. Signed-off-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé --- hw/openrisc/openrisc_sim.c | 42 ++ 1 file changed, 34 insertions(+), 8 deletions(-) diff -

[PULL 0/5] 9p queue 2022-02-10

gs/pull-9p-20220210 for you to fetch changes up to de19c79dad6a2cad54ae04ce754d47c07bf9bc93: 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread (2022-02-10 11:56:01 +0100) 9pfs: fixes and cleanup * Fifth pat

Re: [PATCH v2] hw/smbios: fix memory corruption for large guests due to handle overlap

On Fri, 4 Feb 2022, Ani Sinha wrote: > On Fri, Feb 4, 2022 at 17:48 Igor Mammedov wrote: > > > On Fri, 4 Feb 2022 12:05:58 +0100 > > Gerd Hoffmann wrote: > > > > > Hi, > > > > > > > Another question is why we split memory on 16Gb chunks, to begin with. > > > > Maybe instead of doing so, we

Re: [PATCH 2/4] hw/openrisc/openrisc_sim: Paramatarize initialization

On Thu, Feb 10, 2022 at 12:07:02PM +0100, Philippe Mathieu-Daudé wrote: > On 10/2/22 07:30, Stafford Horne wrote: > > Move magic numbers to variables and enums. These will be > > reused for upcoming fdt initialization. > > > > Signed-off-by: Stafford Horne > > --- > > hw/openrisc/openrisc_sim.c

Re: [PATCH 1/4] hw/openrisc/openrisc_sim: Create machine state for or1ksim

On Thu, Feb 10, 2022 at 12:05:22PM +0100, Philippe Mathieu-Daudé wrote: > On 10/2/22 07:30, Stafford Horne wrote: > > This will allow us to attach machine state attributes like > > the device tree fdt. > > > > Signed-off-by: Stafford Horne > > --- > > hw/openrisc/openrisc_sim.c | 31 +++

Re: [PATCH 1/2] vhost-user-blk: handle errors in vhost_user_blk_connect

  10.02.2022, 14:56, "Philippe Mathieu-Daudé" :On 10/2/22 12:46, Konstantin Khlebnikov wrote: Cleanup vhost device and update connection state when initialization fails.  Signed-off-by: Konstantin Khlebnikov  ---   hw/block/vhost-user-blk.c | 10 --   1 file change

Re: [PATCH 1/2] vhost-user-blk: handle errors in vhost_user_blk_connect

On 10/2/22 12:46, Konstantin Khlebnikov wrote: Cleanup vhost device and update connection state when initialization fails. Signed-off-by: Konstantin Khlebnikov --- hw/block/vhost-user-blk.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/block/vhost-user-b

Re: [PATCH] vhost: fix repeated memory unmap in error paths

On 10/2/22 12:46, Konstantin Khlebnikov wrote: Fuzzing found that on some error paths vhost_memory_unmap() is called twice or for NULL address. Let's reset pointers after unmap and ingnore unmap for NULL. Signed-off-by: Konstantin Khlebnikov --- hw/virtio/vhost.c |4 +++- 1 file changed,

Re: [PATCH] meson: put custom CFLAGS after default CFLAGS

Hi Konstantin, On 10/2/22 12:44, Konstantin Khlebnikov wrote: Flags passed to configure must be at the end to override defaults. Signed-off-by: Konstantin Khlebnikov --- meson.build | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build

Re: [PATCH] meson: put custom CFLAGS after default CFLAGS

  10.02.2022, 14:52, "Philippe Mathieu-Daudé" :Hi Konstantin,On 10/2/22 12:44, Konstantin Khlebnikov wrote: Flags passed to configure must be at the end to override defaults.  Signed-off-by: Konstantin Khlebnikov  ---   meson.build | 12 ++--   1 file changed, 6 in

Re: [PATCH v5 1/2] semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFO

Hi Alex, On 10/2/22 12:30, Alex Bennée wrote: The previous numbers were a guess at best and rather arbitrary without taking into account anything that might be loaded. Instead of using guesses based on the state of registers implement a new function that: a) scans the MemoryRegions for the la

[PATCH 2/2] vhost-user-blk: check connection state in vhost_user_blk_set_config

Fuzzing found that ->set_config() could be called without connection. Signed-off-by: Konstantin Khlebnikov --- hw/block/vhost-user-blk.c |4 1 file changed, 4 insertions(+) diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 35ac188ca4..9ac50443bc 100644 --- a/hw/b

[PATCH] vhost: fix repeated memory unmap in error paths

Fuzzing found that on some error paths vhost_memory_unmap() is called twice or for NULL address. Let's reset pointers after unmap and ingnore unmap for NULL. Signed-off-by: Konstantin Khlebnikov --- hw/virtio/vhost.c |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/vi

[PATCH] virtio-net: break gracefully on packet without valid header

Right now too short packet from guest triggers assert in iov_copy(). (because requested offset does not fit into io vector) For legacy virtio without feature VIRTIO_F_ANY_LAYOUT virtio-net header must fit exactly in the first descriptor. With features VIRTIO_F_ANY_LAYOUT or VIRTIO_F_VERSION_1 head

[PATCH] virtio: update memory region cache when queue size changes

Fuzzing found that queue size could be changed after writing queue address. Resulting cached regions might be shorter than that and cause assert later. Let's update cached memory regions after changing queue size. This is no-op if queue address isn't set yet. Buglink: https://gitlab.com/qemu-proj

[PULL 4/5] tests/9pfs: Use g_autofree and g_autoptr where possible

From: Greg Kurz It is recommended to use g_autofree or g_autoptr as it reduces the odds of introducing memory leaks in future changes. Signed-off-by: Greg Kurz Message-Id: <20220201151508.190035-3-gr...@kaod.org> Reviewed-by: Christian Schoenebeck Signed-off-by: Christian Schoenebeck --- tes

[PATCH 1/2] vhost-user-blk: handle errors in vhost_user_blk_connect

Cleanup vhost device and update connection state when initialization fails. Signed-off-by: Konstantin Khlebnikov --- hw/block/vhost-user-blk.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 1a42ae9187..

[PATCH] meson: put custom CFLAGS after default CFLAGS

Flags passed to configure must be at the end to override defaults. Signed-off-by: Konstantin Khlebnikov --- meson.build | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build index 5f43355071..d94f3ee3e3 100644 --- a/meson.build +++ b/meson.b

[PULL 3/5] tests/9pfs: Fix leak of local_test_path

From: Greg Kurz local_test_path is allocated in virtio_9p_create_local_test_dir() to hold the path of the temporary directory. It should be freed in virtio_9p_remove_local_test_dir() when the temporary directory is removed. Clarify the lifecycle of local_test_path while here. Based-on: Sign

[PULL 5/5] 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread

From: Vitaly Chikunov `struct dirent' returned from readdir(3) could be shorter (or longer) than `sizeof(struct dirent)', thus memcpy of sizeof length will overread into unallocated page causing SIGSEGV. Example stack trace: #0 0x559ebeed v9fs_co_readdir_many (/usr/bin/qemu-system-x86_

[PATCH v5 2/2] tests/tcg: port SYS_HEAPINFO to a system test

This allows us to check our new SYS_HEAPINFO implementation generates sane values. Signed-off-by: Alex Bennée --- v5 - static init of heapinfo structure - clean-up comment on why we can test stack position - add memory clobber for semicall - test we can read/write to a portion of the hea

[PULL 2/5] tests/9pfs: fix mkdir() being called twice

The 9p test cases use mkdtemp() to create a temporary directory for running the 'local' 9p tests with real files/dirs. Unlike mktemp() which only generates a unique file name, mkdtemp() also creates the directory, therefore the subsequent mkdir() was wrong and caused errors on some systems. Signed

[PATCH v5 1/2] semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFO

The previous numbers were a guess at best and rather arbitrary without taking into account anything that might be loaded. Instead of using guesses based on the state of registers implement a new function that: a) scans the MemoryRegions for the largest RAM block b) iterates through all "ROM" blo

Re: [PATCH v4] hw/sensor: Add lsm303dlhc magnetometer device

Hi Kevin, On 30/1/22 10:50, Kevin Townsend wrote: This commit adds emulation of the magnetometer on the LSM303DLHC. It allows the magnetometer's X, Y and Z outputs to be set via the mag-x, mag-y and mag-z properties, as well as the 12-bit temperature output via the temperature property. Sensor c

[PATCH v5 0/2] semihosting/next (SYS_HEAPINFO)

Hi, I'm working through the backlog of stalled patches in my queue so here is the latest version of the semihosting info fixes with Peter's comments addressed. Both patches are still missing their elusive r-b tags ;-) Alex Bennée (2): semihosting/arm-compat: replace heuristic for softmmu SYS_HE

Re: [PATCH 1/1] virtio: fix feature negotiation for ACCESS_PLATFORM

On Thu, Feb 10 2022, Halil Pasic wrote: > On Thu, 10 Feb 2022 10:55:13 +0100 > Cornelia Huck wrote: > >> On Wed, Feb 09 2022, Halil Pasic wrote: >> >> > On Wed, 09 Feb 2022 18:24:56 +0100 >> > Cornelia Huck wrote: >> > >> >> On Wed, Feb 09 2022, Halil Pasic wrote: >> >> > @@ -78,16 +78,1

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