在 2022/3/3 上午2:23, Eugenio Perez Martin 写道:
+
+static bool vhost_svq_add_split(VhostShadowVirtqueue *svq,
+VirtQueueElement *elem,
+unsigned *head)
+{
+unsigned avail_idx;
+vring_avail_t *avail = svq->vring.avail;
+
+*h
在 2022/3/1 下午4:50, Eugenio Perez Martin 写道:
On Mon, Feb 28, 2022 at 8:37 AM Jason Wang wrote:
在 2022/2/27 下午9:41, Eugenio Pérez 写道:
Use translations added in VhostIOVATree in SVQ.
Only introduce usage here, not allocation and deallocation. As with
previous patches, we use the dead code pat
Hi
On Wed, Mar 2, 2022 at 3:00 PM zhenwei pi wrote:
> Assigning a NVMe disk by VFIO or emulating a NVMe controller by QEMU,
> a NVMe disk get exposed in guest side. Support NVMe disk bus type and
> implement posix version.
>
> Test PCI passthrough case:
> ~#virsh qemu-agent-command buster '{"exe
On 3/2/22 20:56, Matheus K. Ferst wrote:
On 01/03/2022 05:29, Cédric Le Goater wrote:
On 2/25/22 22:08, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
This patch series implements 5 missing instructions from PowerISA v3.0
and 58 new instructions from PowerISA v3.1, moving 87 other i
在 2022/3/1 下午6:06, Eugenio Perez Martin 写道:
+
+/*
+ * Find a valid hole for the mapping
+ *
+ * Assuming low iova_begin, so no need to do a binary search to
+ * locate the first node.
+ *
+ * TODO: Replace all this with g_tree_node_first/next/last when available
+
在 2022/3/2 上午2:49, Eugenio Perez Martin 写道:
On Mon, Feb 28, 2022 at 3:57 AM Jason Wang wrote:
在 2022/2/27 下午9:40, Eugenio Pérez 写道:
At this mode no buffer forwarding will be performed in SVQ mode: Qemu
will just forward the guest's kicks to the device.
Host memory notifiers regions are left
在 2022/3/3 13:58, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
From: Hyman Huang(黄勇)
query-vcpu-dirty-limit success depends on enabling dirty
page rate limit, so just add it to the list of skipped
command to ensure qmp-cmd-test run successfully.
Signed-off-by: Hyman Huang(黄勇)
R
Eugenio Pérez writes:
> Finally offering the possibility to enable SVQ from the command line.
>
> Signed-off-by: Eugenio Pérez
> ---
> qapi/net.json| 5 -
> net/vhost-vdpa.c | 48
> 2 files changed, 44 insertions(+), 9 deletions(-)
>
> d
huang...@chinatelecom.cn writes:
> From: Hyman Huang(黄勇)
>
> query-vcpu-dirty-limit success depends on enabling dirty
> page rate limit, so just add it to the list of skipped
> command to ensure qmp-cmd-test run successfully.
>
> Signed-off-by: Hyman Huang(黄勇)
> Reported-by: Dr. David Alan Gilbe
On Thu, Mar 3, 2022 at 12:55 AM Fabiano Rosas wrote:
> Howard Spoelstra writes:
>
> > On Wed, Mar 2, 2022 at 9:11 PM BALATON Zoltan
> wrote:
> >
> >> On Wed, 2 Mar 2022, Howard Spoelstra wrote:
> >> > Hi all,
> >> >
> >> > I noticed qemu-system-ppc running OSX guests does not get to the
> deskt
From: Weiwei Li
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Message-Id: <2022
From: Weiwei Li
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220211043920.28981-7-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
1 file chang
From: Weiwei Li
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220211043920.28981-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 4
target/riscv
From: Anup Patel
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anu
From: Weiwei Li
- update extension check REQUIRE_ZHINX_OR_ZFH and
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
- update half float point register read/write
- disable nanbox_h check
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Acked-by: Alistair Fr
From: Weiwei Li
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220211043920.28981-3-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 6 +-
target/riscv/csr.c| 25
From: Weiwei Li
-- update extension check REQUIRE_ZDINX_OR_D
-- update double float point register read/write
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220211043920.28981-5-liw
From: Wilfred Mallawa
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.
The address references can be found [1].
[1]
https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level gue
From: Anup Patel
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-Id: <20220220085526.808674-5-a...@
From: Anup Patel
We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward all wired interrupts
From: Anup Patel
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
From: Philipp Tomsich
While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS]
inadvertently became inverted and slipped through the initial testing (which
used RV64GC_XVentanaCondOps as a target).
This fixes the regression.
Tested against SPEC2017 w/ GCC 12 (prerelease) for RV6
From: Alistair Francis
The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into
staging (2022-03-02 12:38:46 +)
are available in the Git repository at:
g...@github.com:alistair2
On Sat, Feb 19, 2022 at 10:34 AM Atish Patra wrote:
>
> From: Atish Patra
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
> Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
>
>
From: Wilfred Mallawa
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
V2 -> V3 Changes:
1. Fixup commit message typo.
In `opentitan.h`:
1. Revert copyright year change from 2022 to 2020
2. Moved `OPENTITA
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Fra
ram_size has already been set @sz before if statement, so we can remove
the dead code.
Signed-off-by: Lei Chen
---
softmmu/vl.c | 4
1 file changed, 4 deletions(-)
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 1fe028800f..adacbd7016 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -2105,10
tests/tcg/s390x/vxeh2_vcvt.c
tests/tcg/s390x/vxeh2_vs.c
tests/tcg/s390x/vxeh2_vlstr.c
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vxeh2_vcvt.c| 97 +
tests/tcg/s390x/vxeh2_vlstr.c | 146
tes
On Sat, Feb 19, 2022 at 10:26 AM Atish Patra wrote:
>
> The latest version of the SBI specification includes a Performance Monitoring
> Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
> various PMU events. The Sscofpmf ('Ss' for Privileged arch and
> Supervisor-level
>
Hi Gerd,
On 3/1/22 7:42 PM, Gerd Hoffmann wrote:
Unless it architecturally wrong thing i.e. (node size less than 128Mb)
,in which case limiting it in QEMU would be justified, I'd prefer
firmware being fixed or it reporting more useful for user error message.
[include EDK2 developers]
I don't
resolves: https://gitlab.com/qemu-project/qemu/-/issues/738
implements:
VECTOR LOAD ELEMENTS REVERSED (VLER)
VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR)
VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG)
VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ)
V
Extend s390x z15 to support and test Vector Enhancements Facility 2 (vxeh2)
David Miller (2):
s390x/tcg: Implement Vector-Enhancements Facility 2 for s390x
tests/tcg/s390x: Tests for Vector Enhancements Facility 2
include/qemu/bitops.h| 26 ++
target/s390x/gen-features.c
The value of the following field has been used in ACPI PPTT table
to identify the corresponding processor. This takes the same field
as the ACPI processor ID in MADT and SRAT tables.
ms->possible_cpus->cpus[i].props.thread_id
Signed-off-by: Gavin Shan
---
hw/arm/virt-acpi-build.c | 12 +++
The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
when it isn't provided explicitly. However, the CPU topology isn't fully
considered in the default association and it causes CPU topology broken
warnings on booting Linux guest.
For example, the following warning message
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology, except the cluster IDs,
has been populated in virt_possible_cpu_arch_ids() on arm/virt machine.
This avoids to re-calculate the CPU topology by reusing the existing
one in ms->possible_cp
I've run some risu tests for target arm neon on s390x
and have found a couple of bugs.
r~
Richard Henderson (3):
tcg/s390x: Fix tcg_out_dupi_vec vs VGM
tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
tcg/s390x: Fix tcg_out_dup_vec vs general registers
tcg/s390x/tcg-target.c.inc | 7 ---
When the CPU-to-NUMA association isn't provided by user, the default NUMA
node ID for the specific CPU is returned from virt_get_default_cpu_node_id().
Unfortunately, the default NUMA node ID breaks socket boundary and leads to
the broken CPU topology warning message in Linux guest. This series int
The operands are output in the wrong order: the tcg selector
argument is first, whereas the s390x selector argument is last.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/
We copied the data from the general register input to the
vector register output, but have not yet replicated it.
We intended to fall through into the vector-vector case,
but failed to redirect the input register.
This is caught by an assertion failure in tcg_out_insn_VRIc,
which diagnosed the inc
The immediate operands to VGM were in the wrong order,
producing an inverse mask.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 6e65828c09..508f
During the stress test, the IO request coroutine has a probability that it
can't be awakened when the NBD server is killed.
The GDB statck is as follows:
(gdb) bt
0 0x7f2ff990cbf6 in __ppoll (fds=0x55575de85000, nfds=1,
timeout=, sigmask=0x0) at ../sysdeps/unix/sysv/linux/ppoll.c:44
1 0x000
Below is the updated version of the patch adding debugging support to WHPX.
It incorporates feedback from Alex Bennée and Peter Maydell regarding not
changing the emulation logic depending on the gdb connection status.
Instead of checking for an active gdb connection to determine whether QEMU
shou
Howard Spoelstra writes:
> On Wed, Mar 2, 2022 at 9:11 PM BALATON Zoltan wrote:
>
>> On Wed, 2 Mar 2022, Howard Spoelstra wrote:
>> > Hi all,
>> >
>> > I noticed qemu-system-ppc running OSX guests does not get to the desktop
>> or
>> > does not display the menu bars.
>>
>> Cc-ing the relevant pe
On Sat, Feb 19, 2022 at 10:33 AM Atish Patra wrote:
>
> From: Atish Patra
>
> Qemu can monitor the following cache related PMU events through
> tlb_fill functions.
>
> 1. DTLB load/store miss
> 3. ITLB prefetch miss
>
> Increment the PMU counter in tlb_fill function.
>
> Signed-off-by: Atish Patr
On Fri, 25 Feb 2022, BALATON Zoltan wrote:
On Wed, 16 Feb 2022, BALATON Zoltan wrote:
On Tue, 8 Feb 2022, BALATON Zoltan wrote:
On Tue, 25 Jan 2022, BALATON Zoltan wrote:
v2 - Fixed checkpatch errors
Hello,
Ping?
Ping^2
Ping^3
Ping^4 Why is this getting ignored?
https://patchew.org/
On Sat, Feb 19, 2022 at 10:37 AM Atish Patra wrote:
>
> All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
> as a unified counter. Thus, the predicate function doesn't need handle each
> case separately.
>
> Simplify the predicate function so that we just handle things diff
On Sat, Feb 19, 2022 at 10:31 AM Atish Patra wrote:
>
> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> extension allows the perf to handle overflow interrupts and filtering
> support. This patch provides a f
Since PDMA reads/writes are driven by the guest, it is possible that migration
can occur whilst a SCSIRequest is still active. Fortunately active SCSIRequests
are already included in the migration stream and restarted post migration but
this still leaves the reference in ESPState uninitialised.
Im
The current IRQ state and IRQ mask are handled exactly the same as standard
register accesses, so store these values directly in the regs array rather
than having separate variables for them.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/display/macfb.c | 15
Currently when QEMU tries to migrate the macfb framebuffer it crashes randomly
because the opaque provided by the DeviceClass vmsd property for both devices
is set to MacfbState rather than MacfbNubusState or MacfbSysBusState as
appropriate.
Resolve the issue by adding new VMStateDescriptions for
This patchset contains fixes for the macfb and esp devices which enable
migration of the q800 machine to succeed here in local testing.
Patches 1-5 contain fixes and improvements for migrating the macfb device
whilst patches 6-9 change the ESPState pdma_cb field from being a
function pointer to an
This involves (re)adding a PDMA-specific subsection to hold the reference to the
current PDMA callback.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index a818b2b07a..32926834bc 100644
This prepares for the inclusion of the current PDMA callback in the migration
stream since the callback is referenced by an integer instead of a function
pointer.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 44 ++---
This function is to be used to execute the current PDMA callback rather than
dereferencing the ESPState pdma_cb function pointer directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff -
If booting Linux directly in the q800 machine using -kernel rather than using a
MacOS toolbox ROM, the mode control registers are never initialised,
causing macfb_mode_write() to fail to determine the current resolution after
migration. Resolve this by always setting the initial values of the mode
On Wed, 2 Mar 2022 at 18:26, Paolo Bonzini wrote:
>
> The following changes since commit 99c53410bc9d50e556f565b0960673cccb566452:
>
> Merge remote-tracking branch
> 'remotes/thuth-gitlab/tags/pull-request-2022-02-28' into staging (2022-03-01
> 13:25:54 +)
>
> are available in the Git repo
This function is to be used to set the current PDMA callback rather than
accessing the ESPState pdma_cb function pointer directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
di
These fields are required in the migration stream to restore macfb state
correctly.
Signed-off-by: Mark Cave-Ayland
---
hw/display/macfb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/display/macfb.c b/hw/display/macfb.c
index dfdae90144..7371986480 100644
--- a/hw/display/macfb.c
++
The MacOS toolbox ROM accesses a number of addresses between 0x0 and 0x200
during
initialisation and resolution changes. Whilst the function of many of these
registers is unknown, it is worth the minimal cost of saving these extra values
as
part of migration to help future-proof the migration str
In commit 6e657e64cdc478 in 2013 we added some autorelease pools to
deal with complaints from macOS when we made calls into Cocoa from
threads that didn't have automatically created autorelease pools.
Later on, macOS got stricter about forbidding cross-thread Cocoa
calls, and in commit 5588840ff778
From: Richard Henderson
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
4k or 16k pages.
This introduces the DS bit to TCR_ELx, which is RES0 unless the
page size is enabled and supports LPA2, resulting in the ef
From: Richard Henderson
With FEAT_LPA2, rather than introducing translation level 4,
we introduce level -1, below the current level 0. Extend
arm_fi_to_lfsc to handle these faults.
Assert that this new translation level does not leak into
fault types for which it is not defined, which allows so
From: Richard Henderson
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
64k pages. The only thing left at this point is to handle the
extra bits in the TTBR and in the table descriptors.
Note that PAR_EL1 and HP
From: Richard Henderson
We support 16k pages, but do not advertize that in ID_AA64MMFR0.
The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer
to the same support as stage1 lookups. This setting is deprecated, so
indicate support for all stage2 page sizes directly.
Signed-off-
From: Richard Henderson
This field controls the output (intermediate) physical address size
of the translation process. V8 requires to raise an AddressSize
fault if the page tables are programmed incorrectly, such that any
intermediate descriptor address, or the final translated address,
is out
Hi
On Wed, Mar 2, 2022 at 6:02 PM Janosch Frank wrote:
> On 3/2/22 11:30, Marc-André Lureau wrote:
> > Hi
> >
> > On Tue, Mar 1, 2022 at 6:22 PM Janosch Frank
> wrote:
> >>
> >> Just like with the other write functions let's move the 32/64 bit elf
> >> handling to a function to improve readabil
From: Richard Henderson
The macro is a bit more readable than the inlined computation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20220301215958.157011-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 4 ++--
1 file c
From: Richard Henderson
We will shortly share parts of this function with other portions
of address translation.
Reviewed-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20220301215958.157011-5-richard.hender...@lina
From: Richard Henderson
This feature is relatively small, as it applies only to
64k pages and thus requires no additional changes to the
table descriptor walking algorithm, only a change to the
minimum TSZ (which is the inverse of the maximum virtual
address space size).
Note that this feature w
From: Richard Henderson
Pass down the width of the output address from translation.
For now this is still just PAMax, but a subsequent patch will
compute the correct value from TCR_ELx.{I}PS.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220301215958.157011-6-richar
From: Richard Henderson
Set this as the kernel would, to 48 bits, to keep the computation
of the address space correct for PAuth.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220301215958.157011-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
targ
From: Richard Henderson
For FEAT_LPA2, we will need other ARMVAParameters, which themselves
depend on the translation granule in use. We might as well validate
that the given TG matches; the architecture "does not require that
the instruction invalidates any entries" if this is not true.
Review
From: Richard Henderson
Without FEAT_LVA, the behaviour of programming an invalid value
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
minimum value requires a Translation fault.
It is most self-consistent to choose to generate the fault always.
Reviewed-by: Peter Maydell
Si
From: Wentao_Liang
handle_simd_shift_fpint_conv() was accidentally freeing the TCG
temporary tcg_fpstatus too early, before the last use of it. Move
the free down to where it belongs.
Signed-off-by: Wentao_Liang
Reviewed-by: Richard Henderson
[PMM: cleaned up commit message]
Signed-off-by: Pe
The updateUIInfo method makes Cocoa API calls. It also calls back
into QEMU functions like dpy_set_ui_info(). To do this safely, we
need to follow two rules:
* Cocoa API calls are made on the Cocoa UI thread
* When calling back into QEMU we must hold the iothread lock
Fix the places where we g
From: Richard Henderson
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
returning a structure containing both results. Pass in the
ARMMMUIdx, rather than the digested two_ranges boolean.
This is in preparation for FEAT_LPA2, where the interpretation
of 'value' depends on the effe
From: Richard Henderson
Add new macros to manipulate signed fields within the register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20220301215958.157011-2-richard.hender...@linaro.org
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
Signed-of
When we're using KVM, the PSCI implementation is provided by the
kernel, but QEMU has to tell the guest about it via the device tree.
Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine
if the kernel is providing at least PSCI 0.2, but if the kernel
provides a newer version than t
The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into
staging (2022-03-02 12:38:46 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
Message-id: 20220225174451.192304-1-wuhao...@google.com
Signed-off-by: Peter Maydell
---
tests/qtest/npcm7xx_sdhci-test.c | 215 +++
tests/q
From: Richard Henderson
The shift of the BaseADDR field depends on the translation
granule in use.
Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE")
Reported-by: Peter Maydell
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220301215958.157011-14-rich
The AN547 application note URL has changed: update our comment
accordingly. (Rev B is still downloadable from the old URL,
but there is a new Rev C of the document now.)
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-id: 20220221094144
Finally offering the possibility to enable SVQ from the command line.
Signed-off-by: Eugenio Pérez
---
qapi/net.json| 5 -
net/vhost-vdpa.c | 48
2 files changed, 44 insertions(+), 9 deletions(-)
diff --git a/qapi/net.json b/qapi/net.jso
The tsc210x doesn't support anything other than 16-bit reads on the
SPI bus, but the guest can program the SPI controller to attempt
them anyway. If this happens, don't abort QEMU, just log this as
a guest error.
This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800
acceptance test, which hits
From: Richard Henderson
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned
From: Akihiko Odaki
Support the latest PSCI on TCG and HVF. A 64-bit function called from
AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC
Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since
they do not implement mandatory functions.
Signed-off-by: Akihik
On Mon, Feb 28, 2022 at 8:41 AM Jason Wang wrote:
>
>
> 在 2022/2/27 下午9:40, Eugenio Pérez 写道:
> > This series enable shadow virtqueue (SVQ) for vhost-vdpa devices. This
> > is intended as a new method of tracking the memory the devices touch
> > during a migration process: Instead of relay on vhos
On Dienstag, 1. März 2022 20:13:02 CET Volker Rümelin wrote:
The next patch reduces the effective qemu playback buffer size
by timer-period. Increase the number of jack audio buffers by
one to preserve the total effective buffer size. The size of one
jack audio buffer is 512 samples. With audio d
From: Jimmy Brisson
With these interfaces missing, TFM would delegate peripherals 0, 1,
2, 3 and 8, and qemu would ignore the delegation of interface 8, as
it thought interface 4 was eth & USB.
This patch corrects this behavior and allows TFM to delegate the
eth & USB peripheral to NS mode.
(Th
From: Patrick Venture
Previously this device created N subdevices which each owned an i2c bus.
Now this device simply owns the N i2c busses directly.
Tested: Verified devices behind mux are still accessible via qmp and i2c
from within an arm32 SoC.
Reviewed-by: Hao Wu
Signed-off-by: Patrick Ve
Setting the log address would make the device start reporting invalid
dirty memory because the SVQ vrings are located in qemu's memory.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio
This is needed to achieve migration, so the destination can restore its
index.
Setting base as last used idx, so destination will see as available all
the entries that the device did not use, including the in-flight
processing ones.
This is ok for networking, but other kinds of devices might have
Use translations added in VhostIOVATree in SVQ.
Only introduce usage here, not allocation and deallocation. As with
previous patches, we use the dead code paths of shadow_vqs_enabled to
avoid commiting too many changes at once. These are impossible to take
at the moment.
Signed-off-by: Eugenio Pé
Initial version of shadow virtqueue that actually forward buffers. There
is no iommu support at the moment, and that will be addressed in future
patches of this series. Since all vhost-vdpa devices use forced IOMMU,
this means that SVQ is not usable at this point of the series on any
device.
For s
First half of the buffers forwarding part, preparing vhost-vdpa
callbacks to SVQ to offer it. QEMU cannot enable it at this moment, so
this is effectively dead code at the moment, but it helps to reduce
patch size.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 48
This tree is able to look for a translated address from an IOVA address.
At first glance it is similar to util/iova-tree. However, SVQ working on
devices with limited IOVA space need more capabilities, like allocating
IOVA chunks or performing reverse translations (qemu addresses to iova).
The al
It reports the shadow virtqueue address from qemu virtual address space.
Since this will be different from the guest's vaddr, but the device can
access it, SVQ takes special care about its alignment & lack of garbage
data. It assumes that IOMMU will work in host_page_size ranges for that.
Signed-
This iova tree function allows it to look for a hole in allocated
regions and return a totally new translation for a given translated
address.
It's usage is mainly to allow devices to access qemu address space,
remapping guest's one into a new iova space where qemu can add chunks of
addresses.
Si
SVQ is able to log the dirty bits by itself, so let's use it to not
block migration.
Also, ignore set and clear of VHOST_F_LOG_ALL on set_features if SVQ is
enabled. Even if the device supports it, the reports would be nonsense
because SVQ memory is in the qemu region.
The log region is still all
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