Re: [PATCH v3 0/6] Support akcipher for virtio-crypto

On Wed, Mar 23, 2022 at 10:49:06AM +0800, zhenwei pi wrote: > v2 -> v3: > - Introduce akcipher types to qapi > - Add test/benchmark suite for akcipher class > - Seperate 'virtio_crypto: Support virtio crypto asym operation' into: > - crypto: Introduce akcipher crypto class > - virtio-crypto: In

Re: [PATCH v1 1/5] kvm,memory: Optimize dirty page collection for dirty ring

在 2022/3/23 11:18, wuc...@chinatelecom.cn 写道: From: Chongyun Wu When log_sync_global of dirty ring is called, it will collect dirty pages on all cpus, including all dirty pages on memslot, so when memory_region_sync_dirty_bitmap collects dirty pages from KVM, this interface needs to be calle

[PATCH qemu v3 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 28 + 2 files changed, 32 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

[PATCH qemu v3 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 16 1 file changed, 16 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 697c74e8cc..2a8ecf40f5 100644 --- a/target/riscv/vector_helper.c

[PATCH qemu v3 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 + target/riscv/vector_helper.c| 448 +--- 2 files changed, 263 insertions(+), 196 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH qemu v3 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 2 + target/riscv/vector_helper.c| 54 ++--- 2 files changed, 50 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/ta

[PATCH qemu v3 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 860e51154b..e3393f7d99 100644 --- a/target/riscv/vector_helper

[PATCH qemu v3 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 12 2 files changed, 13 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_r

[PATCH qemu v3 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++ target/riscv/vector_helper.c| 32 + 2 files changed, 41 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH qemu v3 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 5 + target/riscv/vector_helper.c| 311 +--- 2 files changed, 178 insertions(+), 138 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH qemu v3 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 77a5629b73..661e78797f 10

[PATCH qemu v3 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 27 + 2 files changed, 31 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

[PATCH qemu v3 00/14] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH qemu v3 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/

[PATCH qemu v3 02/14] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/ve

[PATCH qemu v3 03/14] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/risc

[PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD This is the first commit regarding the tail agnostic behavior. Added option 'rvv_ta_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

Re: [PATCH v2 2/3] hw/acpi/aml-build: Use existing CPU topology to build PPTT table

Hi Igor and Yanan, On 3/18/22 9:28 PM, Igor Mammedov wrote: On Fri, 18 Mar 2022 14:34:12 +0800 "wangyanan (Y)" wrote: On 2022/3/3 11:11, Gavin Shan wrote: When the PPTT table is built, the CPU topology is re-calculated, but it's unecessary because the CPU topology, except the cluster IDs, has

Re: [PATCH v2 1/3] hw/arm/virt: Fix CPU's default NUMA node ID

Hi Yanan, On 3/21/22 10:28 AM, wangyanan (Y) wrote: On 2022/3/18 21:27, Igor Mammedov wrote: On Fri, 18 Mar 2022 21:00:35 +0800 "wangyanan (Y)" wrote: On 2022/3/18 17:56, Igor Mammedov wrote: On Fri, 18 Mar 2022 14:23:34 +0800 "wangyanan (Y)" wrote: Hi Gavin, On 2022/3/3 11:11, Gavin Sha

Re: [PATCH v2 1/3] hw/arm/virt: Fix CPU's default NUMA node ID

Hi Yanan and Igor, On 3/21/22 10:28 AM, wangyanan (Y) wrote: On 2022/3/18 21:27, Igor Mammedov wrote: On Fri, 18 Mar 2022 21:00:35 +0800 "wangyanan (Y)" wrote: On 2022/3/18 17:56, Igor Mammedov wrote: On Fri, 18 Mar 2022 14:23:34 +0800 "wangyanan (Y)" wrote: On 2022/3/3 11:11, Gavin Shan w

[PATCH v1 4/5] kvm: Introduce a dirty rate calculation method based on dirty ring

From: Chongyun Wu A new structure KVMDirtyRingDirtyCounter is introduced in KVMDirtyRingReaper to record the number of dirty pages within a period of time. When kvm_dirty_ring_mark_page collects dirty pages, if it finds that the current dirty pages are not duplicates, it increases the dirty_page

[PATCH v1 3/5] kvm: Dirty ring autoconverge optmization for kvm_cpu_synchronize_kick_all

From: Chongyun Wu Dirty ring feature need call kvm_cpu_synchronize_kick_all to flush hardware buffers into KVMslots, but when aucoverge run kvm_cpu_synchronize_kick_all calling will become more and more time consuming. This will significantly reduce the efficiency of dirty page queries, especiall

[PATCH v1 2/5] kvm: Dynamically adjust the rate of dirty ring reaper thread

From: Chongyun Wu Dynamically adjust the dirty ring collection thread to reduce the occurrence of ring full, thereby reducing the impact on customers, improving the efficiency of dirty page collection, and thus improving the migration efficiency. Implementation: 1) Define different collection sp

[PATCH v1 0/5] Dirty ring and auto converge optimization

From: Chongyun Wu Overview This series of patches is to optimize the performance of online migration using dirty ring and autoconverge. Mainly through the following aspects to do optimization: 1. When using the dirty ring mode to traverse each memslot to obtain dirty pages, only cal

[PATCH qemu v2 10/13] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 + target/riscv/vector_helper.c| 448 +--- 2 files changed, 263 insertions(+), 196 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v1 5/5] migration: Calculate the appropriate throttle for autoconverge

From: Chongyun Wu The current autoconverge algorithm does not obtain the threshold that currently requires the CPU to limit the speed through calculation, but limits the speed of the CPU through continuous attempts. Start from an initial value to limit the speed. If the migration can not be compl

[PATCH qemu v2 09/13] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 77a5629b73..661e78797f 10

[PATCH qemu v2 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 5 + target/riscv/vector_helper.c| 311 +--- 2 files changed, 178 insertions(+), 138 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v1 1/5] kvm, memory: Optimize dirty page collection for dirty ring

From: Chongyun Wu When log_sync_global of dirty ring is called, it will collect dirty pages on all cpus, including all dirty pages on memslot, so when memory_region_sync_dirty_bitmap collects dirty pages from KVM, this interface needs to be called once, instead of traversing every dirty page. Eac

[PATCH qemu v2 12/13] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 27 + 2 files changed, 31 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

[PATCH qemu v2 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 12 2 files changed, 13 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_r

[PATCH qemu v2 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 860e51154b..e3393f7d99 100644 --- a/target/riscv/vector_helper

[PATCH qemu v2 02/13] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/risc

[PATCH qemu v2 08/13] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 28 + 2 files changed, 32 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

[PATCH qemu v2 11/13] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 16 1 file changed, 16 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 697c74e8cc..2a8ecf40f5 100644 --- a/target/riscv/vector_helper.c

[PATCH qemu v2 03/13] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD This is the first commit regarding the tail agnostic behavior. Added option 'rvv_ta_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

[PATCH qemu v2 01/13] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/ve

[PATCH qemu v2 13/13] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 2 + target/riscv/vector_helper.c| 54 ++--- 2 files changed, 50 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/ta

[PATCH qemu v2 04/13] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++ target/riscv/vector_helper.c| 32 + 2 files changed, 41 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH qemu v2 00/13] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH v3 5/6] tests/crypto: Add test suite for crypto akcipher

From: Lei He Add unit test and benchmark test for crypto akcipher. Signed-off-by: lei he Signed-off-by: zhenwei pi --- tests/bench/benchmark-crypto-akcipher.c | 163 ++ tests/bench/meson.build | 6 + tests/bench/test_akcipher_keys.inc | 277 + tests/unit/mes

[PATCH v3 4/6] crypto: Implement RSA algorithm by hogweed

From: Lei He Introduce ASN.1 decoder, and implement RSA algorithm by hogweed from nettle. Thus QEMU supports a 'real' RSA backend to handle request from guest side. It's important to test RSA offload case without OS & hardware requirement. Signed-off-by: lei he Signed-off-by: zhenwei pi --- c

[PATCH v3 6/6] virtio-crypto: Introduce RSA algorithm

There are two parts in this patch: 1, support akcipher service by cryptodev-builtin driver 2, virtio-crypto driver supports akcipher service Then virtio-crypto gets request from guest side, and forwards the request to builtin driver to handle it. Test with a guest linux: 1, The self-test framewor

[PATCH v3 2/6] crypto-akcipher: Introduce akcipher types to qapi

From: Lei He Introduce akcipher types, also include RSA & ECDSA related types. Signed-off-by: Lei He Signed-off-by: zhenwei pi --- qapi/crypto.json | 86 1 file changed, 86 insertions(+) diff --git a/qapi/crypto.json b/qapi/crypto.json index 1

[PATCH v3 3/6] crypto: Introduce akcipher crypto class

Support basic asymmetric operations: encrypt, decrypt, sign and verify. Co-developed-by: lei he Signed-off-by: lei he Signed-off-by: zhenwei pi --- crypto/akcipher.c | 78 + crypto/meson.build| 1 + include/crypto/akcipher.h | 139

[PATCH v3 1/6] virtio-crypto: header update

Update header from linux, support akcipher service. Reviewed-by: Gonglei Signed-off-by: lei he Signed-off-by: zhenwei pi --- .../standard-headers/linux/virtio_crypto.h| 82 ++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/include/standard-headers/linux/virt

[PATCH v3 0/6] Support akcipher for virtio-crypto

v2 -> v3: - Introduce akcipher types to qapi - Add test/benchmark suite for akcipher class - Seperate 'virtio_crypto: Support virtio crypto asym operation' into: - crypto: Introduce akcipher crypto class - virtio-crypto: Introduce RSA algorithm v1 -> v2: - Update virtio_crypto.h from v2 versio

Re: [PATCH-for-6.2 0/2] hw/block/fdc: Fix CVE-2021-3507

On Fri, Mar 18, 2022 at 2:50 PM Thomas Huth wrote: > > On 10/03/2022 18.53, Jon Maloy wrote: > > > > On 3/10/22 12:14, Thomas Huth wrote: > >> On 06/02/2022 20.19, Jon Maloy wrote: > >>> Trying again with correct email address. > >>> ///jon > >>> > >>> On 2/6/22 14:15, Jon Maloy wrote: > > >>

Re: [PATCH for-7.1 2/4] hw/ppc: use qdev to register physical DRC vmstates

On Tue, Mar 22, 2022 at 03:38:52PM -0300, Daniel Henrique Barboza wrote: > Similar to logical DRCs, let's convert physical DRCs to register their > vmstates using dc->vmsd. > > The same constraints with instance_id being set to spapr_drc_index() > also applies in this case. However, since realize_

Re: [PATCH for-7.1 0/4] use dc->vmsd with spapr devices vmstate

On Tue, Mar 22, 2022 at 03:38:50PM -0300, Daniel Henrique Barboza wrote: > Hi, > > This short series converts some spapr devices to use the dc->vmsd > interface to register the vmstate. For most of them it was needed > to use qdev_set_legacy_instance_id() to keep compatibility with the > instance_

Re: [PATCH] net/slirp: Use newer slirp_*_hostxfwd API

Hi, Pinging this. It’s a bit old, though the patch still applies cleanly to master as far as I can tell. Link to patchew is https://patchew.org/QEMU/20210925214820.18078-1-nicho...@ngai.me/. I’d love to get https://gitlab.com/qemu-project/qemu/-/issues/347 addressed once libslirp makes a r

[PATCH v4 1/1] fix cmpxchg and lock cmpxchg instruction

This patch fixes a bug reported on issues #508. The problem is cmpxchg and lock cmpxchg would touch accumulator when the comparison is equal. Signed-off-by: Wei Li --- target/i386/tcg/translate.c | 41 + 1 file changed, 19 insertions(+), 22 deletions(-) diff

Re: [PATCH v2 1/3] qapi: rename BlockDirtyBitmapMergeSource to BlockDirtyBitmapOrStr

On Wed, Mar 16, 2022 at 5:18 PM Eric Blake wrote: > > On Tue, Mar 15, 2022 at 12:32:24AM +0300, Vladimir Sementsov-Ogievskiy wrote: > > From: Vladimir Sementsov-Ogievskiy > > > > Rename the type to be reused. Old name is "what is it for". To be > > natively reused for other needs, let's name it e

[ANNOUNCE] QEMU 7.0.0-rc1 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the second release candidate for the QEMU 7.0 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu-project.org/qemu-7.0.0-rc1.tar.xz http://downl

[PATCH v2 3/3] linux-user/arm: Implement __kernel_cmpxchg64 with host atomics

If CONFIG_ATOMIC64, we can use a host cmpxchg and provide atomicity across processes; otherwise we have no choice but to continue using start/end_exclusive. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 79 +++ 1

[PATCH v2 2/3] linux-user/arm: Implement __kernel_cmpxchg with host atomics

The existing implementation using start/end_exclusive does not provide atomicity across processes. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 87 --- 1 file changed, 62 insertions(+), 25 deletions(-) diff --gi

[PATCH v2 0/3] linux-user/arm: Improvements for commpage atomics

Only the memory_barrer one is a bug; the rest improve system-wide interaction, and would only affect pre-armv6. Changes for v2: * Adjust atomic_mmu_lookup as per laurent. * Fix alignment check for arm_kernel_cmpxchg32_helper. r~ Richard Henderson (3): linux-user/arm: Implement __kernel_

[PATCH v2 1/3] linux-user/arm: Implement __kernel_memory_barrier

This fallback syscall was stubbed out. It would only matter for emulating pre-armv6. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.

Re: [PATCH 2/3] linux-user/arm: Implement __kernel_cmpxchg with host atomics

On 3/22/22 13:08, Laurent Vivier wrote: I have removed this patch and the following one from the branch because it hangs when executed in an armhf/bionic chroot the following example: cat > /tmp/hello.go < I don't see a hang. I see a SIGBUS, due to a silly typo here: +static void arm_kerne

Problem to compile on windows 10

Hi, i would to compile QEMU with a 3DFX-Patch but i have problems to do it. I tested to compile QEMU alone and i have the same problems. First after compiling it will ask for libzstd.dll, i found the github project and downloaded the dll... but there is another problems. I don't know where t

Re: [PULL 0/8] Fix CVE-2021-3611 and heap overflow in sdhci code

On Mon, 21 Mar 2022 at 17:03, Thomas Huth wrote: > > The following changes since commit 2058fdbe81e2985c226a026851dd26b146d3395c: > > Merge tag 'fixes-20220318-pull-request' of git://git.kraxel.org/qemu into > staging (2022-03-19 11:28:54 +) > > are available in the Git repository at: > >

Re: [PULL 00/21] Fixes patches

On Tue, 22 Mar 2022 at 12:26, wrote: > > From: Marc-André Lureau > > The following changes since commit 48fb0a826eea2e7b0135f49e7fa63e7efe2b7677: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2022-03-21 21:27:14 +) > > are available in the Git repository a

Re: [PATCH 2/3] linux-user/arm: Implement __kernel_cmpxchg with host atomics

Le 22/03/2022 à 12:46, Laurent Vivier a écrit : Le 14/03/2022 à 05:43, Richard Henderson a écrit : The existing implementation using start/end_exclusive does not provide atomicity across processes. Signed-off-by: Richard Henderson ---   linux-user/arm/cpu_loop.c | 85 ++

Re: [PATCH] softmmu/physmem: Use qemu_madvise

On Tue, 22 Mar 2022 17:58:19 + "Dr. David Alan Gilbert" wrote: > * Andrew Deason (adea...@sinenomine.net) wrote: > > On Tue, 22 Mar 2022 16:53:05 + > > "Dr. David Alan Gilbert" wrote: > > > > > * Andrew Deason (adea...@sinenomine.net) wrote: > > > > On Wed, 16 Mar 2022 10:41:41 +0100 >

Re: [PATCH 1/2] gdbstub: Set current_cpu for memory read write

On Tue, 22 Mar 2022 at 18:59, Philippe Mathieu-Daudé wrote: > On 22/3/22 16:56, Peter Maydell wrote: > > This works, but I worry a bit that it might have unexpected > > side effects, and setting globals (even if thread-local) to > > cause side-effects elsewhere isn't ideal... > > Yeah, gdbstub is

Re: [PATCH 13/15] iotests: remove qemu_io_pipe_and_status()

On Tue, Mar 22, 2022 at 12:39 PM Hanna Reitz wrote: > > On 18.03.22 21:36, John Snow wrote: > > I know we just added it, sorry. This is done in favor of qemu_io() which > > *also* returns the console output and status, but with more robust error > > handling on failure. > > > > Signed-off-by: John

[PATCH v2 1/2] ci: Add github workflow for getting cirrus working properly

Signed-off-by: Yonggang Luo --- .github/workflows/main.yml | 29 + MAINTAINERS| 4 +++- 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 .github/workflows/main.yml diff --git a/.github/workflows/main.yml b/.github/workflows/main.ym

[PATCH v2 0/2] CI fixes

* Fixes the cirrus CI * Add an empty github actions to get cirrus CI works properly Yonggang Luo (2): ci: Add github workflow for getting cirrus working properly cirrus: upgrade mingw base packages. .cirrus.yml| 2 +- .github/workflows/main.yml | 29 +

[PATCH-for-7.0] target/i386/hvf: Free ressources when vCPU is destroyed

From: Philippe Mathieu-Daudé Both xsave_buf and hvf_caps are allocated in hvf_arch_init_vcpu(), free them in hvf_arch_vcpu_destroy(). Reported-by: Mark Kanda Suggested-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daudé --- target/i386/hvf/hvf.c | 2 ++ 1 file changed, 2 insertions(+) d

Re: [PATCH for-7.0] hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging

On 22/3/22 15:58, Richard Henderson wrote: On 3/22/22 03:38, Philippe Mathieu-Daudé wrote: On 22/3/22 11:28, Peter Maydell wrote: In commit 84d43d2e82da we rearranged the logging of errors in process_mapc(), and inadvertently dropped the trailing newlines from the log messages. Restore them. F

Re: [PATCH 1/2] gdbstub: Set current_cpu for memory read write

+Thomas On 22/3/22 16:56, Peter Maydell wrote: On Tue, 22 Mar 2022 at 15:43, Bin Meng wrote: When accessing the per-CPU register bank of some devices (e.g.: GIC) from the GDB stub context, a segfault occurs. This is due to current_cpu is not set, as the contect is not a guest CPU. Let's set

[PATCH for-7.1 2/4] hw/ppc: use qdev to register physical DRC vmstates

Similar to logical DRCs, let's convert physical DRCs to register their vmstates using dc->vmsd. The same constraints with instance_id being set to spapr_drc_index() also applies in this case. However, since realize_physical() calls drc_realize(), qdev_set_legacy_instance_id() is already being set.

[PATCH for-7.1 0/4] use dc->vmsd with spapr devices vmstate

Hi, This short series converts some spapr devices to use the dc->vmsd interface to register the vmstate. For most of them it was needed to use qdev_set_legacy_instance_id() to keep compatibility with the instance_id being used for awhile. Although no functional changes were made the resulting cod

Re: [PATCH v2] gitlab: disable accelerated zlib for s390x

On Mon, 21 Mar 2022 at 16:11, Alex Bennée wrote: > > There appears to be a bug in the s390 hardware-accelerated version of > zlib distributed with Ubuntu 20.04, which makes our test > /i386/migration/multifd/tcp/zlib hit an assertion perhaps one time in > 10. Fortunately zlib provides an escape ha

[PATCH for-7.1 4/4] hw/ppc: use qdev to register spapr_nvdimm vmsd

Make the code a little more maintainable by using dc->vmsd to register the vmstate instead of using vmstate_(un)register calls. 'instance_id' was being set to VMSTATE_INSTANCE_ID_ANY so there is no need for qdev_set_legacy_instance_id() calls. spapr_nvdimm_unrealize() was removed since it was onl

[PATCH for-7.1 3/4] hw/ppc: use qdev to register spapr_iommu tcet vmstate

Use the dc->vmsd interface to register the vmstate of the tcet. The instance_id is being set to tcet->liobn by calling qdev_set_legacy_instance_id() during spapr_tce_table_realize(). Signed-off-by: Daniel Henrique Barboza --- hw/ppc/spapr_iommu.c | 7 +++ 1 file changed, 3 insertions(+), 4 d

[PATCH for-7.1 1/4] hw/ppc: use qdev to register logical DRC vmstates

Today we use vmstate_register() to register the vmstate of logical DRCs during drc_realize(), following it up with a similar vmstate_unregister() during drc_unrealize(). We can instead use qdev to init the vmstate of the device via the dc->vmsd interface. This will spare us of both vmstate calls a

Re: [PATCH] softmmu/physmem: Use qemu_madvise

* Andrew Deason (adea...@sinenomine.net) wrote: > On Tue, 22 Mar 2022 16:53:05 + > "Dr. David Alan Gilbert" wrote: > > > * Andrew Deason (adea...@sinenomine.net) wrote: > > > On Wed, 16 Mar 2022 10:41:41 +0100 > > > David Hildenbrand wrote: > > > > > > > On 16.03.22 10:37, Dr. David Alan Gi

[PATCH] iotests: update test owner contact information

Quite a few of these tests have stale contact information. This patch updates the stale ones that I happen to be aware of at the moment. Signed-off-by: John Snow --- tests/qemu-iotests/025 | 2 +- tests/qemu-iotests/027 | 2 +- tests/qemu-iotests/028 | 2 +- tests/qemu-iotests/036 | 2 +- tests/

Re: [PATCH] softmmu/physmem: Use qemu_madvise

On Tue, 22 Mar 2022 16:53:05 + "Dr. David Alan Gilbert" wrote: > * Andrew Deason (adea...@sinenomine.net) wrote: > > On Wed, 16 Mar 2022 10:41:41 +0100 > > David Hildenbrand wrote: > > > > > On 16.03.22 10:37, Dr. David Alan Gilbert wrote: > > > > * Peter Maydell (peter.mayd...@linaro.org)

Re: [PATCH v1 4/9] aspeed/wdt: Add AST1030 support

On 3/22/22 03:51, Jamin Lin wrote: From: Steven Lee AST1030 wdt controller is similiar to AST2600's wdt, but it has extra registers. yes. We don't implement all AST2600 registers either but, one day, we should tune the mmio size better for each SoC and output an unimplemented log. That's ok

Re: [PATCH v2 3/3] Use g_new() & friends where that makes obvious sense

On Mar 15 15:41, Markus Armbruster wrote: > g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, > for two reasons. One, it catches multiplication overflowing size_t. > Two, it returns T * rather than void *, which lets the compiler catch > more type errors. > > This commit only

Re: [PATCH 00/15] iotests: add enhanced debugging info to qemu-io failures

On 18.03.22 21:36, John Snow wrote: Howdy, Heya, [...] - Uh, actually, test 040 fails with this patchset and I don't understand if it's intentional, harmless, a test design problem, or worse: == ERROR: test_filterless_co

Re: [PATCH 14/15] iotests: remove qemu_io_silent() and qemu_io_silent_check().

On Tue, Mar 22, 2022 at 1:00 PM Hanna Reitz wrote: > > On 18.03.22 21:36, John Snow wrote: > > Like qemu-img, qemu-io returning 0 should be the norm and not the > > exception. Remove all calls to qemu_io_silent that just assert the > > return code is zero (That's every last call, as it turns out),

Re: [PATCH 04/15] iotests/040: Don't check image pattern on zero-length image

On 22.03.22 17:19, John Snow wrote: On Tue, Mar 22, 2022, 10:22 AM Hanna Reitz wrote: On 18.03.22 21:36, John Snow wrote: > qemu-io fails on read/write with zero-length raw images, so skip these > when running the zero-length image tests. > > Signed-off-by: John Snow

Re: [PATCH 12/15] iotests/migration-permissions: use assertRaises() for qemu_io() negative test

On Tue, Mar 22, 2022 at 12:37 PM Hanna Reitz wrote: > > On 18.03.22 21:36, John Snow wrote: > > Modify this test to use assertRaises for its negative testing of > > qemu_io. If the exception raised does not match the one we tell it to > > expect, we get *that* exception unhandled. If we get no exc

Re: [PATCH 15/15] iotests: make qemu_io_log() check return codes by default

On 18.03.22 21:36, John Snow wrote: Just like qemu_img_log(), upgrade qemu_io_log() to enforce a return code of zero by default. Affected tests: 242 245 255 274 303 307 nbd-reconnect-on-open Signed-off-by: John Snow --- tests/qemu-iotests/iotests.py | 5 +++-- tests/qemu-io

Re: [PULL 00/25] Block patches for 7.0-rc1

On Tue, 22 Mar 2022 at 11:56, Hanna Reitz wrote: > > The following changes since commit 330724977b10f5b92610817e8b7d1dfed122df87: > > Merge tag 'pull-misc-2022-03-21' of git://repo.or.cz/qemu/armbru into > staging (2022-03-21 17:46:40 +) > > are available in the Git repository at: > > htt

Re: [PATCH 10/15] iotests/245: fixup

On Fri, Mar 18, 2022 at 4:37 PM John Snow wrote: > > (Merge with prior patch.) > > Signed-off-by: John Snow > --- > tests/qemu-iotests/242 | 2 +- ^ Oh, there's the stray import changes that needed to be folded into patch #1. Fixed for v2.

Re: [PATCH 14/15] iotests: remove qemu_io_silent() and qemu_io_silent_check().

On 18.03.22 21:36, John Snow wrote: Like qemu-img, qemu-io returning 0 should be the norm and not the exception. Remove all calls to qemu_io_silent that just assert the return code is zero (That's every last call, as it turns out), and replace them with a normal qemu_io() call. Signed-off-by: Jo

Re: [PATCH] softmmu/physmem: Use qemu_madvise

* Andrew Deason (adea...@sinenomine.net) wrote: > On Wed, 16 Mar 2022 10:41:41 +0100 > David Hildenbrand wrote: > > > On 16.03.22 10:37, Dr. David Alan Gilbert wrote: > > > * Peter Maydell (peter.mayd...@linaro.org) wrote: > > >> On Wed, 16 Mar 2022 at 07:53, David Hildenbrand wrote: > > >>> > >

Re: [PATCH v1 2/8] tests/avocado: update aarch64_virt test to exercise -cpu max

On 3/15/22 05:12, Alex Bennée wrote: The Fedora 29 kernel is quite old and importantly fails when running in LPA2 scenarios. As it's not really exercising much of the CPU space replace it with a custom 5.16.12 kernel with all the architecture options turned on. There is a minimal buildroot initra

Re: [PATCH] softmmu/physmem: Use qemu_madvise

On 22.03.22 17:39, Andrew Deason wrote: > On Wed, 16 Mar 2022 10:41:41 +0100 > David Hildenbrand wrote: > >> On 16.03.22 10:37, Dr. David Alan Gilbert wrote: >>> * Peter Maydell (peter.mayd...@linaro.org) wrote: On Wed, 16 Mar 2022 at 07:53, David Hildenbrand wrote: > > On 16.03.22

Re: [PATCH v1 1/2] s390x/cpu_models: drop "msa5" from the TCG "max" model

On 22/03/2022 12.22, David Hildenbrand wrote: We don't include the "msa5" feature in the "qemu" model because it generates a warning. The PoP states: "The message-security-assist extension 5 requires the secure-hash-algorithm (SHA-512) capabilities of the message-security-assist extension 2 as a

Re: [PATCH v3 1/1] fix cmpxchg and lock cmpxchg instruction

On 3/22/22 09:23, Wei Li wrote: Give a better code struture to reduce more code duplication according to the discuss in patch v2. This needs to be a consolidated description of the problem fixed, and not reference previous email conversations. Signed-off-by: Wei Li --- target/i386/tcg/tr

Re: [PATCH 13/15] iotests: remove qemu_io_pipe_and_status()

On 18.03.22 21:36, John Snow wrote: I know we just added it, sorry. This is done in favor of qemu_io() which *also* returns the console output and status, but with more robust error handling on failure. Signed-off-by: John Snow --- tests/qemu-iotests/iotests.py | 3 --- tests/qemu

Re: [PATCH] softmmu/physmem: Use qemu_madvise

On Wed, 16 Mar 2022 10:41:41 +0100 David Hildenbrand wrote: > On 16.03.22 10:37, Dr. David Alan Gilbert wrote: > > * Peter Maydell (peter.mayd...@linaro.org) wrote: > >> On Wed, 16 Mar 2022 at 07:53, David Hildenbrand wrote: > >>> > >>> On 16.03.22 05:04, Andrew Deason wrote: > We have a th

Re: [PATCH 12/15] iotests/migration-permissions: use assertRaises() for qemu_io() negative test

On 18.03.22 21:36, John Snow wrote: Modify this test to use assertRaises for its negative testing of qemu_io. If the exception raised does not match the one we tell it to expect, we get *that* exception unhandled. If we get no exception, we get a unittest assertion failure and the provided emsg p

Re: [PATCH 10/15] iotests/245: fixup

On 22.03.22 17:36, John Snow wrote: On Tue, Mar 22, 2022, 12:30 PM Hanna Reitz wrote: On 18.03.22 21:36, John Snow wrote: > (Merge with prior patch.) > > Signed-off-by: John Snow > --- >   tests/qemu-iotests/242 | 2 +- >   tests/qemu-iotests/245 | 2 +- >   2 f

Re: [PATCH 10/15] iotests/245: fixup

On Tue, Mar 22, 2022, 12:30 PM Hanna Reitz wrote: > On 18.03.22 21:36, John Snow wrote: > > (Merge with prior patch.) > > > > Signed-off-by: John Snow > > --- > > tests/qemu-iotests/242 | 2 +- > > tests/qemu-iotests/245 | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > di

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