On Fri, Apr 22, 2022 at 9:17 AM Peter Xu wrote:
>
> Hi, Jason,
>
> Mostly good to me, just a few nitpicks below.
>
> On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> > We introduce VTDBus structure as an intermediate step for searching
> > the address space. This works well with SID b
On Fri, Apr 22, 2022 at 8:13 AM Peter Xu wrote:
>
> On Wed, Mar 30, 2022 at 04:36:36PM +0800, Jason Wang wrote:
> > > If not, do we want to apply this version scheme only when it
> > > reaches the production quality or also in the experimental phase?
> >
> > Yes. E.g if we think scalable mode is m
Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
patch fixes them by clearing evt before encoding. On top of it, this
patch changes the event log size to 16 bytes per IOMMU specification,
and fixes the event log entry format in amdvi_encode_event().
[1] CID 1487116/1487200/148
On Tue, Mar 8, 2022 at 10:28 PM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 10:15:49PM +0530, Ani Sinha wrote:
> >
> > Change log:
> > v2: rebased the patchset. Laine's response is appended at the end.
> >
> > I am re-introducing the patchset for which got
> > reverted here few months b
This patch series implements ast2600 hace engine with accumulative mode
and unit test against to it.
Verified with following models
- AST2600 with OpenBmc VERSION_ID=2.12.0-dev-660-g4c7b3e692-dirty
- check hash verification in uboot and check whether qemu crashed
during openbmc web gui login
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b
The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
1. Allocating and initiating accumulative hash digest write buffer
with initial state.
* Since QEMU crypto/hash api doesn't provide the API to set initial
state of hash library, and the init
This add two addition test cases for accumulative mode under sg enabled.
The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).
The result was calculated by command line sha512sum/sha256sum uti
Jag Raman writes:
>> On Apr 21, 2022, at 10:55 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Add blocker to prevent hot-unplug of devices
>>
>> Why do you need this? I'm not doubting you do, I just want to read your
>> reasons here :)
>
> Hi Markus, :)
>
> The x-vfio-u
Jag Raman writes:
>> On Apr 21, 2022, at 10:59 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Setup a handler to run vfio-user context. The context is driven by
>>> messages to the file descriptor associated with it - get the fd for
>>> the context and hook up the handler
On 4/21/22 11:40, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
The following changes since commit 28298069afff3eb696e4995e63b2579b27adf378:
Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into
staging (2022-04-21 09:27:54 -0700)
are available in the
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
+Richard
On Wed, Apr 20, 2022 at 4:16 PM Bin Meng wrote:
>
> On Tue, Apr 12, 2022 at 9:11 AM Bin Meng wrote:
> >
> > On Thu, Mar 24, 2022 at 9:48 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
> > >
> > > [1] https://sour
On Fri, Apr 22, 2022 at 10:53 AM Bin Meng wrote:
>
> On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
> wrote:
> >
> > Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> > case, walk_pte will erroneously merge them.
> >
> > Enforce the split up, by tracking the virtual base address
On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000 (4
On 2022/04/22 0:07, Christian Schoenebeck wrote:
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and chmod() respectively if S_IFSOCK
was passed with mode argument.
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by:
On Mon, Apr 18, 2022 at 5:13 AM Ben Dooks wrote:
>
> Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
> the code.
>
> Signed-off-by; Ben Dooks
; should be replaced to :
Not sure how you did that, but you can do with "git commit -s" and git
will take care of the SoB tag.
> ---
> hw/
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Imply the TPM sysbus devices. This allows users to add TPM devices to
> the RISC-V virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtpm socket --tpm2 -t -d --tpmstate dir=/tmp
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Add support for plugging in devices, this was tested with the TPM
> device.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> hw/riscv/virt.c | 35 +
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Similar to the ARM virt machine add support for adding device tree
> entries for dynamically created devices.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> hw/riscv/virt.c | 25
On 4/21/22 10:31, Richard Henderson wrote:
The following changes since commit 401d46789410e88e9e90d76a11f46e8e9f358d55:
Merge tag 'pull-target-arm-20220421' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-21
08:04:43 -0700)
are available in the Git rep
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Create a platform bus to allow dynamic devices to be connected. This is
> based on the ARM implementation.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> include/hw/riscv/virt.h
On Fri, Apr 22, 2022 at 8:48 AM Alistair Francis
wrote:
> On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote:
> >
> > On Wed, Apr 20, 2022 at 5:57 PM wrote:
> > >
> > > From: Frank Chang
> > >
> > > Allow user to set core's marchid, mvendorid, mipid CSRs through
> > > -cpu command line option.
>
On Thu, Apr 21, 2022 at 11:51 PM Richard Henderson
wrote:
>
> On 4/20/22 16:46, Bin Meng wrote:
> > It seems you were trying to build every commit for bisectabliity? Is
> > there an easy way to do such automatically?
>
> git rebase --exec "cd build && make"
>
This works! Thanks Richard.
Regards,
Hi, Jason,
Mostly good to me, just a few nitpicks below.
On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> We introduce VTDBus structure as an intermediate step for searching
> the address space. This works well with SID based matching/lookup. But
> when we want to support SID plus PA
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-6-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-7-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
include/hw/core/tcg-cpu-ops.h | 1 +
1 f
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-5-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/machine.c | 32
1 file ch
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-2-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/deb
On Thu, Apr 21, 2022 at 3:58 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the changes were entirely useless, due to MachineState::kernel_cmdline
> can't
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to
On Thu, Apr 21, 2022 at 3:57 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present the adding '/chosen/stdout-path' property in device tree
> is determined by whether a kernel command line is provided, which is
> wrong. It should be added unconditionally.
>
> Fixes: 8d8897accb1c ("hw/riscv: spike:
From: Niklas Cassel
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU m
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-3-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
On 3/10/2022 9:07 PM, Michael S. Tsirkin wrote:
On Thu, Mar 10, 2022 at 08:28:09PM +0800, Xiaoyao Li wrote:
For PIT, it's straightforward to merge microvm::pit and
pc_machine::pit_enabled into x86ms::pit
For PIC, move microvm::pic to x86ms:pic, which gives PC machine the
ability to dis-/en-able
From: Ralf Ramsauer
The -bios option is silently ignored if used in combination with -enable-kvm.
The reason is that the machine starts in S-Mode, and the bios typically runs in
M-Mode.
Better exit in that case to not confuse the user.
Signed-off-by: Ralf Ramsauer
Reviewed-by: Alistair Francis
On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote:
>
> On Wed, Apr 20, 2022 at 5:57 PM wrote:
> >
> > From: Frank Chang
> >
> > Allow user to set core's marchid, mvendorid, mipid CSRs through
> > -cpu command line option.
> >
> > The default values of marchid and mipid are built with QEMU's versio
From: Dylan Jhong
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
address within 3GB,
but not all platforms have dram_base within 3GB.
This patch adds an exception for dram base not within 3GB,
which will place fdt at dram_end align 16MB.
riscv_setup_rom_reset_vec() al
From: Richard Henderson
The riscv_raise_exception function stores its argument into
exception_index and then exits to the main loop. When we
have already set exception_index, we can just exit directly.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220401125948.
From: Bin Meng
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 tri
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time de
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-4-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4
From: Tsukasa OI
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of supervisor
and user mode, respectively) in `misa' CSR must not be copied since
neither `S' nor `U' are valid single-letter extensions.
This commit also r
From: Weiwei Li
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
the same helper
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220325085902.29500-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Fra
From: Nicolas Pitre
There is an overflow with the current code where a pmpaddr value of
0x1fff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0x.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper resu
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesse
From: Atish Patra
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by:
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-Id: <20220317061817.3856850-2-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --gi
From: Weiwei Li
The spec for vmvr.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Message-Id:
From: Weiwei Li
for some cases, scale is always equal or less than 0, since lmul is not larger
than 3
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20220325085902.29500-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair F
From: Atish Patra
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <2022030
From: Atish Patra
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and seccon
From: Atish Patra
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extend
From: Alistair Francis
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or s
From: Atish Patra
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-
From: Atish Patra
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-3-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertio
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Fra
From: Alistair Francis
The following changes since commit da5006445a92bb7801f54a93452fac63ca2f634c:
Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging
(2022-04-21 15:16:52 -0700)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pu
From: Atish Patra
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis
Signed-
From: Wilfred Mallawa
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220303045426.511588-2-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan
On Tue, Apr 19, 2022 at 12:06 PM Weiwei Li wrote:
>
> - add SEED CSR which must be accessed with a read-write instruction:
>A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
> with uimm=0 will raise an illegal instruction exception.
> - add USEED, SSEED fields for MSEC
On Wed, Mar 30, 2022 at 04:36:36PM +0800, Jason Wang wrote:
> > If not, do we want to apply this version scheme only when it
> > reaches the production quality or also in the experimental phase?
>
> Yes. E.g if we think scalable mode is mature, we can enable 3.0.
Sorry to come back to the discuss
On 4/21/22 08:15, John Snow wrote:
The following changes since commit b1efff6bf031a93b5b8bf3912ddc720cc1653a61:
Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into
staging (2022-04-20 21:54:24 -0700)
are available in the Git repository at:
https://gitlab.com/jsnow/q
On 4/21/22 12:30, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/dino.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 4/21/22 07:31, Markus Armbruster wrote:
The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:
Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into
staging (2022-04-20 16:43:11 -0700)
are available in the Git repository at:
git://repo.or.cz/qemu
On Thu, 21 Apr 2022, Richard Henderson wrote:
On 4/21/22 08:29, Mark Cave-Ayland wrote:
You need (1 << SCSI_DISK_QUIRK_MODE_PAGE_APPLE) instead.
Doh, you're absolutely right. I believe the current recommendation is to
use the BIT() macro in these cases.
I think it's not a recommendation (as
On 4/21/22 14:39, Max Filippov wrote:
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
Reviewed
On 4/21/22 14:39, Max Filippov wrote:
+TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
+
+if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+gen_io_start();
+}
+gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+tcg_temp_free(pc);
Missed conversion to tcg_const
On 4/21/22 14:39, Max Filippov wrote:
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
Reviewed-by: Richard H
On 4/21/22 14:39, Max Filippov wrote:
Exception number, exception cause and debug cause codes are small
numbers, use tcg_contant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
Reviewed-by: Richard Hend
On 4/21/22 14:39, Max Filippov wrote:
dtlb is a boolean flag, use tcg_constant_* for it.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson
r~
On 4/21/22 14:39, Max Filippov wrote:
Replace tcg_const_* for numeric literals with tcg_constant_*.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
Reviewed-by: Richard Henderson
r~
On 4/21/22 13:21, Max Filippov wrote:
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Add missing tcg_temp_free for pc, use tcg_constant_i32
for w.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Signed-off-by: Max Filippov
---
target/xt
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- gen_callw_slot uses callinc (1..3);
- translate_entry passes stack register number (0..15) to the helper;
- gen_check_exclusive passes boolean to the helper;
- translate_ssai passes immediate shift amou
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xt
Replace tcg_const_* for numeric literals with tcg_constant_*.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index f4dac27507fd..3379
Exception number, exception cause and debug cause codes are small
numbers, use tcg_contant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
dtlb is a boolean flag, use tcg_constant_* for it.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 77d2e1303746..82a0dbf46d7c 100644
--- a/target
Hello,
this series replaces tcg_const_* with tcg_constant_* in the xtensa front
end.
Max Filippov (6):
target/xtensa: use tcg_contatnt_* for numeric literals
target/xtensa: use tcg_constant_* for exceptions
target/xtensa: use tcg_constant_* for TLB opcodes
target/xtensa: use tcg_constant_
On 4/21/22 12:03, Peter Maydell wrote:
On Sun, 17 Apr 2022 at 19:02, Richard Henderson
wrote:
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson
---
target/arm/translate-m-nocp.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff -
On Thu, Apr 21, 2022, 2:00 PM Andrea Bolognani wrote:
> On Thu, Apr 21, 2022 at 12:46:48PM -0400, John Snow wrote:
> > Hi Alex: do you have the ability to create a blank/empty "py-qemu.qmp"
> > repo under the qemu-project grouping, and add me and Cleber as
> > maintainers for it? There weren't an
Hi Simon,
On Thu, Apr 21, 2022 at 1:04 PM Simon Safar via wrote:
>
> This is the core used in e.g. ESP8266 chips. Importing them
> using import_core.sh, with the required files sourced from
>
> https://github.com/espressif/xtensa-overlays
>
> core-lx106.c was generated by the script; the only cha
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Add missing tcg_temp_free for pc, use tcg_constant_i32
for w.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 3 ++-
1 file changed,
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/machine.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 3176c7897e..292867a063 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -446,7 +446,7 @@ static void hppa_nmi
Hi, Daniel!
Ok, thank you - then I'll wait until compat machines
for 7.1 are added (after release) and send a new
patch.
Regards,
Vladislav
вт, 19 апр. 2022 г. в 19:03, Daniel P. Berrangé :
> On Sun, Apr 17, 2022 at 04:43:14PM +0300, Vladislav Yaroshchuk wrote:
> > I've CCed all the people from
Now that the board configuration is in one place, the define is only needed when
wiring up the board in machine.c.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 2 --
hw/hppa/machine.c | 3 +++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b/hw/hpp
The functions and definitions in this file are not used anywhere within the
generic hppa machine.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 6
hw/hppa/meson.build | 2 +-
hw/hppa/pci.c| 65
hw/hppa/trace-events | 3 --
Instead of generating the offset based upon the physical address of the
register, add constants for each of the device registers to lasi.h and
update lasi.c to use them.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c | 28 ++--
hw/hppa/lasi.h | 5 +
2 files chang
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/machine.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 13942ec596..dc9950d5d5 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -471,8 +471,8 @@ static void
machine_hppa_mac
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c| 8
hw/hppa/machine.c | 7 +++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 6faa98dca5..753a08d454 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -18,7 +18,6 @@
#inclu
Now that there are no longer any devices in hw/hppa the trace-events file is
empty and can be removed.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/trace-events | 1 -
meson.build | 1 -
2 files changed, 2 deletions(-)
delete mode 100644 hw/hppa/trace-events
diff --git a/hw/hppa/trace-
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c| 7 ---
hw/hppa/machine.c | 5 +
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 65139bb29b..88ff9141e4 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -18,7 +18,6 @@
#include
Move the LASI device implementation from hw/hppa to hw/misc so that it is
located with all the other miscellaneous devices.
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 ++
hw/hppa/Kconfig | 1 +
hw/hppa/machine.c | 2 +-
hw/hp
This is to allow us to decouple the LASI device from the board logic. If it is
decided later that this value needs to be configurable then it can easily be
converted to a qdev property.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Move the DINO device implementation from hw/hppa to hw/pci-host so that it is
located with all the other PCI host bridges.
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 ++
hw/hppa/Kconfig | 2 +-
hw/hppa/machine.c |
Move the simplified lasi_initfn() back to machine.c whilst also renaming it
back to its original lasi_init() name.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 2 --
hw/hppa/lasi.c | 10 --
hw/hppa/machine.c | 12 +++-
3 files changed, 11 insertions(+), 13 delet
This is to allow us to decouple the DINO device from the board logic.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/dino.h | 5 +
hw/hppa/hppa_hardware.h | 5 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/hppa/dino.h b/hw/hppa/dino.h
index ca380515f2..a1b0184
Now that all of the LASI devices are mapped by the board, this parameter is no
longer required.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 2 +-
hw/hppa/lasi.c | 2 +-
hw/hppa/machine.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b
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