[PATCH v4 36/45] target/arm: Implement virtual SError exceptions

Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Honor EAE for reporting VSERR to aa32. --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 +

[PATCH v4 45/45] target/arm: Define neoverse-n1

Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c| 1 + hw/arm/virt.c| 1 + target/arm/cpu64.c | 66 4 files changed,

[PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2

This register is present for either VHE or Debugv8p2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/helper.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/hel

[PATCH v4 39/45] target/arm: Enable FEAT_IESB for -cpu max

This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c| 1 + 2 files

[PATCH v4 37/45] target/arm: Implement ESB instruction

Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Retain m-profile check; improve comments. --- target/arm/helper.h| 1 + target/arm/a32.decode | 16 -- target/arm/t32.decode | 18

[PATCH v4 26/45] target/arm: Update qemu-system-arm -cpu max to cortex-a57

Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Create impdef sysr

[PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS

Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index b4bdd4a4a6.

[PATCH v4 22/45] target/arm: Merge zcr reginfo

Drop zcr_no_el2_reginfo and merge the 3 registers into one array, now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped while registering. Signed-off-by: Richard Henderson --- target/arm/helper.c | 55 ++--- 1 file changed, 17 insertions(+), 38 dele

[PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d1b558385c..7303103016 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3704,6 +3704,11 @@ stati

[PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras

Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ 1 file changed,

[PATCH v4 27/45] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max

We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 4 1 file changed, 4 insertions(+) diff -

[PATCH v4 17/45] target/arm: Perform override check early in add_cpreg_to_hashtable

Perform the override check early, so that it is still done even when we decide to discard an unreachable cpreg. Use assert not printf+abort. Signed-off-by: Richard Henderson --- target/arm/helper.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/targe

[PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks

Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local vpidr_regs definition, and rely on the squasing to ARM_CP_CONST while registering. Signed-off-by: Richard Henderson --- target/arm/helper.c | 158 1 file changed, 13 insertions(+), 14

[PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 for -cpu max

This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell Signed-off-by: Richard

[PATCH v4 25/45] target/arm: Move cortex impdef sysregs to cpu_tcg.c

Previously we were defining some of these in user-only mode, but none of them are accessible from user-only, therefore define them only in system mode. This will shortly be used from cpu_tcg.c also. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: New patch. --- target/arm/i

[PATCH v4 28/45] target/arm: Split out aa32_max_features

Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 + target/arm/cpu64.c | 50 +- target/arm/cpu_tcg.c | 114 +++

[PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable

Since ee3eb3a7ce72, our host endian indicator is unconditionally set, which means that we can use a normal C condition. Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c

[PATCH v4 14/45] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable

Put most of the value writeback to the same place, and improve the comment that goes with them. Signed-off-by: Richard Henderson --- target/arm/helper.c | 28 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c in

[PATCH v4 16/45] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable

Computing isbanked only once makes the code a bit easier to read. Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c6d407f93b..f1fbbdb9e0 100644 --- a/target/arm/help

[PATCH v4 13/45] target/arm: Hoist computation of key in add_cpreg_to_hashtable

Move the computation of key to the top of the function. Hoist the resolution of cp as well, as an input to the computation of key. This will be required by a subsequent patch. Signed-off-by: Richard Henderson --- target/arm/helper.c | 49 + 1 file cha

[PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers

Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 100 +---

[PATCH v4 20/45] target/arm: Handle cpreg registration for missing EL

More gracefully handle cpregs when EL2 and/or EL3 are missing. If the reg is entirely inaccessible, do not register it at all. If the reg is for EL2, and EL3 is present but EL2 is not, either discard, squash to const, or keep unchanged. Per rule RJFFP, mark the 4 aarch32 hypervisor access register

[PATCH v4 12/45] target/arm: Merge allocation of the cpreg and its name

Simplify freeing cp_regs hash table entries by using a single allocation for the entire value. This fixes a theoretical bug if we were to ever free the entire hash table, because we've been installing string literal constants into the cpreg structure in define_arm_vh_e2h_redirects_aliases. However

[PATCH v4 08/45] target/arm: Name CPState type

Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 6 +++--- target/arm/helper.c | 6 -- 2 files changed, 7 insertions(+)

[PATCH v4 18/45] target/arm: Reformat comments in add_cpreg_to_hashtable

Put the block comments into the current coding style. Signed-off-by: Richard Henderson --- target/arm/helper.c | 24 +++- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2ed07795d8..b690346469 100644 --- a/target/

[PATCH v4 06/45] target/arm: Avoid bare abort() or assert(0)

Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report. Signed-off-by: Richard Henderson --- v4: new. --- target/arm/helper.c | 7 +++ target/arm/hvf/hvf.c| 2 +- target/arm/kvm-stub.c | 4 ++-- target/arm

[PATCH v4 09/45] target/arm: Name CPSecureState type

Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 7 --- target/arm/helper.

[PATCH v4 15/45] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable

Bool is a more appropriate type for these variables. Signed-off-by: Richard Henderson --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b2887d63b6..c6d407f93b 100644 --- a/target/arm/helper.c +++ b/targ

[PATCH v4 10/45] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases

The new_key field is always non-zero -- drop the if. Signed-off-by: Richard Henderson --- v4: Drop change to crn et al. --- target/arm/helper.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 50ad2e3e37

[PATCH v4 11/45] target/arm: Store cpregs key in the hash table directly

Cast the uint32_t key into a gpointer directly, which allows us to avoid allocating storage for each key. Use g_hash_table_lookup when we already have a gpointer (e.g. for callbacks like count_cpreg), or when using get_arm_cp_reginfo would require casting away const. Signed-off-by: Richard Hender

[PATCH v4 03/45] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h

Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k.

[PATCH v4 01/45] target/arm: Split out cpregs.h

Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h| 413 + target/arm/cpu.h | 368 --

[PATCH v4 05/45] target/arm: Reorg ARMCPRegInfo type field bits

Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson --- v4: Revert merge of ARM_CP_CONST

[PATCH v4 02/45] target/arm: Reorg CPAccessResult and access_check_cp_reg

Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h| 26 ++

[PATCH v4 04/45] target/arm: Make some more cpreg data static const

These particular data structures are not modified at runtime. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helpe

[PATCH v4 00/45] target/arm: Cleanups, new features, new cpus

Changes for v4: * Rebase on master, where the first third is upstream. * Split changes to add_cpreg_to_hashtable into bite sized chunks. * Add ARM_CP_EL3_NO_EL2_{UNDEF,KEEP} flags. * Fix access check for SCXTNUM_ELx (damien). Patches lacking review: 05-target-arm-Reorg-ARMCPRegInfo-type-

[PATCH v4 07/45] target/arm: Change cpreg access permissions to enum

Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 44 +++- target/arm/helper.c |

Re: [PATCH v3 32/60] target/arm: Update sysreg fields when redirecting for E2H

On 4/22/22 03:39, Peter Maydell wrote: On Sun, 17 Apr 2022 at 19:07, Richard Henderson wrote: The new_key is always non-zero during redirection, so remove the if. Update opc0 et al from the new key. Signed-off-by: Richard Henderson --- target/arm/helper.c | 35 +++-

Re: [PATCH v3 26/60] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h

On 4/22/22 08:36, Alex Bennée wrote: +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ +do {\ +QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ +if (ARRAY_SIZE(REGS) == 1)

[PATCH] tcg: Special case split barriers before/after load

When st:ld is not required by the guest but ld:st is, we can put ld:ld+ld:st barriers after loads, and then st:st barriers before stores to enforce all required barriers. The st:st barrier is often special cased by hosts, and that is expected to be more efficient than a full barrier. Signed-off-b

Re: [PATCH] tcg: fix guest memory ordering enforcement

On 4/28/22 04:32, Redha Gouicem wrote: This commit allows memory ordering enforcement to be performed more precisely. The previous scheme with fences always inserted before the memory access made it impossible to correctly enforce the x86 model on weakly ordered architectures such as arm. With th

Re: [PULL 0/7] 9p queue 2022-04-30

On 4/30/22 12:29, Christian Schoenebeck wrote: I suggest I just s/AT_SYMLINK_NOFOLLOW_ANY/AT_SYMLINK_NOFOLLOW/ on my end and post v2 PR, for consistency and as it does not really make a huge difference IMO which one of the two is used in create_socket_file_at_cwd(). Any objections? Sounds good

Re: [PULL v3 00/25] Misc patches for 2022-04-29

On 4/30/22 09:41, Richard Henderson wrote: On 4/30/22 07:05, Paolo Bonzini wrote: The following changes since commit 731340813fdb4cb8339edb8630e3f923b7d987ec:    Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into staging (2022-04-29 08:46:55 -0700) are available in t

Re: [RFC PATCH 12/12] configure: enable cross compilation of vof

On 4/29/22 07:18, Paolo Bonzini wrote: While container-based cross compilers are not supported, this already makes it possible to build vof on any machine that has an installation of GCC and binutils for 32- or 64-bit PowerPC. Signed-off-by: Paolo Bonzini --- configure| 10

Re: [PATCH v3 0/5] qga: Implement shutdown/network-get-interfaces on Solaris

On Tue, 26 Apr 2022 14:55:21 -0500 Andrew Deason wrote: > This implements the guest agent commands guest-network-get-interfaces and > guest-shutdown on Solaris. The implementation for these on Solaris is very > similar as on Linux, since both platforms have a similar getifaddrs() and a > 'shutdow

Re: [RFC PATCH 11/12] configure: enable cross-compilation of optionrom

On 4/29/22 07:18, Paolo Bonzini wrote: While container-based cross compilers are not supported, this already makes it possible to build x86 optionroms on any machine that has an installation of GCC and binutils for 32- or 64-bit x86. Signed-off-by: Paolo Bonzini --- configure

Re: [RFC PATCH 10/12] pc-bios/optionrom: compile with -Wno-array-bounds

On 4/29/22 07:18, Paolo Bonzini wrote: Avoids the following bogus warning: pvh_main.c: In function ‘pvh_load_kernel’: pvh_main.c:101:42: warning: array subscript 0 is outside array bounds of ‘uint16_t[0]’ {aka ‘short unsigned int[]’} [-Warray-bounds] 101 | uint32_t ebda_paddr = ((uin

Re: [RFC PATCH 09/12] pc-bios/optionrom: detect -fno-pie

On 4/29/22 07:18, Paolo Bonzini wrote: Do not rely on the detection that was done in the configure script, since in the future we may want to cross-compile this file. Signed-off-by: Paolo Bonzini --- configure | 1 - pc-bios/optionrom/Makefile | 3 ++- 2 files changed, 2 ins

Re: [RFC PATCH 08/12] configure: enable cross-compilation of s390-ccw

On 4/29/22 07:18, Paolo Bonzini wrote: -# Only build s390-ccw bios if we're on s390x and the compiler has -march=z900 -# or -march=z10 (which is the lowest architecture level that Clang supports) -if test "$cpu" = "s390x" ; then +# Only build s390-ccw bios the compiler has -march=z900 or -march=z

Re: [RFC PATCH 07/12] configure: move symlink configuration earlier

On 4/29/22 07:18, Paolo Bonzini wrote: Ensure that the pc-bios/optionrom and pc-bios/s390-ccw directory exist at the time when we'll write out the compiler configuration for them. Signed-off-by: Paolo Bonzini --- configure | 49 - 1 file changed

Re: [RFC PATCH 06/12] configure, meson: move symlinking of ROMs to meson

On 4/29/22 07:18, Paolo Bonzini wrote: This is useful because pc-bios/meson.build already has a list of all ROM files, and thus does not need to use wildcards. The problems with wildcards are mentioned above the definition of the LINKS variable, but then the recommendation is disattended. Signe

Re: [RFC PATCH 05/12] configure: include more binutils in tests/tcg makefile

On 4/29/22 07:18, Paolo Bonzini wrote: Firmware builds require paths to all the binutils; it is not enough to use only cc, or even as/ld as in the case of tests/tcg/tricore. Adjust the cross-compiler configurator to detect also ar, nm, objcopy, ranlib and strip. Signed-off-by: Paolo Bonzini ---

Re: [RFC PATCH 04/12] configure: introduce --cross-prefix-*=

On 4/29/22 07:18, Paolo Bonzini wrote: # cross compilers defaults, can be overridden with --cross-cc-ARCH -: ${cross_cc_aarch64="aarch64-linux-gnu-gcc"} +: ${cross_prefix_aarch64="aarch64-linux-gnu-"} +: ${cross_prefix_aarch64_be="$cross_prefix_aarch64"} +: ${cross_prefix_alpha="alpha-linux-gnu

Re: [RFC PATCH 02/12] configure: add missing cross compiler fallbacks

On 4/29/22 07:18, Paolo Bonzini wrote: -: ${cross_cc_cflags_sparc="-m32 -mv8plus -mcpu=ultrasparc"} : ${cross_cc_sparc64="sparc64-linux-gnu-gcc"} : ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"} +: ${cross_cc_sparc="$cross_cc_sparc64"} +: ${cross_cc_cflags_sparc="-m32 -mv8plus -mcpu=ultra

Re: [PULL 0/7] 9p queue 2022-04-30

/qemu > >into staging (2022-04-29 08:46:55 -0700)> > > are available in the Git repository at: > >https://github.com/cschoenebeck/qemu.git tags/pull-9p-20220430 > > > > for you to fetch changes up to e8fb9ed725fe2ed00a275674a84beb5ba6e538a7: > >9pf

[PATCH v4 14/17] tests/tcg/m68k: Add trap.c

Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc, and the signals and addresses that we expect from them. Signed-off-by: Richard Henderson --- tests/tcg/m68k/trap.c | 129 + tests/tcg/m68k/Makefile.target | 3 + 2 files changed, 13

[PATCH v4 17/17] target/m68k: Mark helper_raise_exception as noreturn

Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Signed-off-by: Richard Henderson --- target/m68k/helper.h| 2 +- target/m68k/op_helper.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/m68k/

[PATCH v4 13/17] target/m68k: Implement FTRAPcc

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0cd7ef89e3..a3141d7f77 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -55

[PATCH v4 16/17] linux-user/strace: Adjust get_thread_area for m68k

Unlike i386, m68k get_thread_area has no arguments. Signed-off-by: Richard Henderson --- linux-user/strace.list | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/strace.list b/linux-user/strace.list index 278596acd1..72e17b1acf 100644 --- a/linux-user/strace.list +++ b/linux-us

[PATCH v4 10/17] target/m68k: Implement TRAPcc

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ linux-user/m68k/cpu_loop.c | 1 + target/m68k/cpu.c | 1 + target/m68k/op_helper.c| 6 + target/m68k/translate.c| 49 +++

[PATCH v4 12/17] target/m68k: Implement TRAPV

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index bb5ed1b7b1..0cd7ef89e3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4911,6 +4911,14 @@ DISAS_

[PATCH v4 09/17] target/m68k: Fix stack frame for EXCP_ILLEGAL

According to the M68040 Users Manual, section 8.4.3, Four word stack frame (format 0), includes Illegal Instruction. Use the correct frame format, which does not use the ADDR argument. Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 5 - 1 file changed, 4 insertions(+), 1 del

[PATCH v4 11/17] target/m68k: Implement TPF in terms of TRAPcc

TPF stands for "trap false", and is a long-form nop for ColdFire. Re-use the immediate consumption code from trapcc; the insn will already expand to a nop because of the TCG_COND_NEVER test within do_trapcc. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 18 +- 1

[PATCH v4 06/17] target/m68k: Fix address argument for EXCP_CHK

According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mm

[PATCH v4 08/17] target/m68k: Fix address argument for EXCP_TRACE

According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Trace (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create gen_raise_exception_format2 to record the trapping pc in env->mmu.ar. Update m68k_inter

[PATCH v4 02/17] target/m68k: Switch over exception type in m68k_interrupt_all

Replace an if ladder with a switch for clarity. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 49 + 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/target/m6

[PATCH v4 05/17] target/m68k: Remove retaddr in m68k_interrupt_all

The only value this variable holds is now env->pc. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m

[PATCH v4 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0

According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented a

[PATCH v4 15/17] linux-user/strace: Fix print_syscall_err

Errors are not all negative numbers, but only the top 4k. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/strace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/strace.c b/linux-user/strace.c index 2cdbf030ba..dc4f810bd3 1

[PATCH v4 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15

These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 56417f7401..6ca3e1e

[PATCH v4 01/17] target/m68k: Raise the TRAPn exception with the correct pc

Rather than adjust the PC in all of the consumers, raise the exception with the correct PC in the first place. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 1 - target/m68k/op_helper.c| 9 - target/m68k/translate.c| 2 +- 3 files

[PATCH v4 03/17] target/m68k: Fix coding style in m68k_interrupt_all

Add parenthesis around & vs &&. Remove assignment to sr in function call argument -- note that sr is unused after the call, so the assignment was never needed, only the result of the & expression. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c

[PATCH v4 00/17] target/m68k: Conditional traps + trap cleanup

Changes for v4: - Rebase, which requires QEMU_NORETURN -> G_NORETURN. - Cast -4096 to abi_ulong for print_syscall_err. r~ v1: https://lore.kernel.org/qemu-devel/20211130103752.72099-1-richard.hender...@linaro.org/ v2: https://lore.kernel.org/qemu-devel/20211202204900.50973-1-richard.hende

Re: [PATCH v3 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

On 4/29/22 03:07, Xiaojuan Yang wrote: This patch realize the PCH-PIC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 1 + hw/intc/Kconfig | 4 + hw/intc/loongarch_pch_pic.c | 431 +++

Re: [PATCH v3 26/43] target/loongarch: Add LoongArch IOCSR instruction

On 4/29/22 03:07, Xiaojuan Yang wrote: This includes: - IOCSR{RD/WR}.{B/H/W/D} Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c| 44 target/loongarch/cpu.h| 25 +++ target/loongarch/disas.c

Re: [PATCH v3 25/43] target/loongarch: Add LoongArch CSR instruction

On 4/29/22 03:07, Xiaojuan Yang wrote: +[LOONGARCH_CSR_CPUID] = { +.offset = -1, +.flags = CSRFL_READONLY, +.readfn = gen_helper_csrrd_cpuid, +.writefn = NULL +}, The offset should be (int)offsetof(CPUState, cpu_index) - (int)offsetof(LoongArchCPU, e

Re: Building tools on unsupported cpu/arch

30.04.2022 19:57, Richard Henderson wrote: .. What's the way to build tools on an unsupported architecture these days? Hmm, well, there isn't a way.  This seems like a bug in common-user/meson.build. We should not add this include directory if neither linux-user and bsd-user are enabled. Aft

[PATCH 2/2] target/m68k: Enable halt insn for 68060

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4026572ed8..e4efd988d2 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6003,6 +6003,7 @@ void register_m6

[PATCH 1/2] target/m68k: Clear mach in m68k_cpu_disas_set_info

Zero selects all cpu features in disas/m68k.c, which is really what we want -- not limited to 68040. Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c7aeb7da9c..5671067923

[PATCH 0/2] target/m68k: Enable halt insn for 68060

While looking at semihosting, I noticed that 060 does have halt. Then I was a bit surprised that it wasn't being disassembled and thought trying to exactly match disassembly to cpu was a bit frought with peril -- one also wants to know what the insn was *supposed* to be when it raises SIGILL. r~

Re: Building tools on unsupported cpu/arch

On 4/30/22 07:11, Michael Tokarev wrote: Hello! Previously, it was possible to build qemu tools (such as qemu-img, or qemu-ga) on an unsupported cpu/architecture.  In a hackish way, by specifying --enable-tcg-interpreter on the ./configure line. Today (with 7.0), it does not work anymore, with

Re: [PULL v3 00/25] Misc patches for 2022-04-29

On 4/30/22 07:05, Paolo Bonzini wrote: The following changes since commit 731340813fdb4cb8339edb8630e3f923b7d987ec: Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into staging (2022-04-29 08:46:55 -0700) are available in the Git repository at: https://gitlab.com/

Re: [PULL 0/7] 9p queue 2022-04-30

https://github.com/cschoenebeck/qemu.git tags/pull-9p-20220430 for you to fetch changes up to e8fb9ed725fe2ed00a275674a84beb5ba6e538a7: 9pfs: fix qemu_mknodat() to always return -1 on error on macOS host (2022-04-30 13:11:48 +0200) ---

[PATCH] hw/usb/hcd-ehci.c: print diagnostics when cpage out of range

Making it easier to diagnose what is going on when it happens Signed-off-by: Arnout Engelen --- hw/usb/hcd-ehci.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 33a8a377bd..8e2f6578c2 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@

Building tools on unsupported cpu/arch

Hello! Previously, it was possible to build qemu tools (such as qemu-img, or qemu-ga) on an unsupported cpu/architecture. In a hackish way, by specifying --enable-tcg-interpreter on the ./configure line. Today (with 7.0), it does not work anymore, with the following error during configure: co

[PULL v3 20/25] build: move vhost-scsi configuration to Kconfig

vhost-scsi and vhost-user-scsi are two devices of their own; it should be possible to enable/disable them with --without-default-devices, not --without-default-features. Compute their default value in Kconfig to obtain the more intuitive behavior. Reviewed-by: Marc-André Lureau Signed-off-by: Pa

[PULL v3 00/25] Misc patches for 2022-04-29

The following changes since commit 731340813fdb4cb8339edb8630e3f923b7d987ec: Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into staging (2022-04-29 08:46:55 -0700) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you

[PATCH 41/43] target/nios2: Move nios2-semi.c to nios2_softmmu_ss

Semihosting is not enabled for nios2-linux-user. Signed-off-by: Richard Henderson --- target/nios2/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/nios2/meson.build b/target/nios2/meson.build index 2bd60ba306..c6e2243cc3 100644 --- a/target/nios2/meson.

[PULL v3 19/25] build: move vhost-vsock configuration to Kconfig

vhost-vsock and vhost-user-vsock are two devices of their own; it should be possible to enable/disable them with --without-default-devices, not --without-default-features. Compute their default value in Kconfig to obtain the more intuitive behavior. Reviewed-by: Marc-André Lureau Signed-off-by:

[PATCH 37/43] target/m68k: Do semihosting call as a normal helper

There's no need to raise an exception; just call the helper function directly. The test for the required surrounding insns is easier as well. Move the load of nr inside the helper. Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 -- target/m68k/helper.h| 1 + target/m68k

[PATCH 39/43] target/m68k: Remove EXCP_HALT_INSN

Now that semihosting is not attached to EXCP_HALT_INSN, we can use EXCP_HLT. Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 1 - target/m68k/op_helper.c | 5 - target/m68k/translate.c | 3 ++- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/m68k/cpu.h b/

[PATCH 38/43] target/m68k: Enable semihosting for non-coldfire

The libgloss m68k-semi.txt spec says that bkpt #0 may be used when the halt insn is not available. While halt is available for 68060, continue to support bkpt #0 for all m68k processors. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 9 + 1 file changed, 9 insertions(+)

[PATCH 32/43] semihosting: Create semihost_sys_gettimeofday

This syscall will be used by m68k and nios2 semihosting. Signed-off-by: Richard Henderson --- include/semihosting/guestfd.h | 3 +++ semihosting/guestfd.c | 42 +++ 2 files changed, 45 insertions(+) diff --git a/include/semihosting/guestfd.h b/include/se

[PATCH 40/43] target/nios2: Eliminate nios2_semi_is_lseek

Reorg nios2_semi_return_* to gdb_syscall_complete_cb. Use the 32-bit version normally, and the 64-bit version for HOSTED_LSEEK. Signed-off-by: Richard Henderson --- target/nios2/nios2-semi.c | 59 +++ 1 file changed, 23 insertions(+), 36 deletions(-) diff --g

[PATCH 30/43] semihosting: Split out semihost_sys_system

Split out the non-ARM specific portions of SYS_SYSTEM to a reusable function. This doesn't use GuestFD, but it does reuse validate_strlen() from semihost_sys_open. Signed-off-by: Richard Henderson --- include/semihosting/guestfd.h | 3 +++ semihosting/arm-compat-semi.c | 12 +-- semiho

[PATCH 43/43] target/nios2: Do semihosting call as a normal helper

There's no need to raise an exception; just call the helper function directly. Signed-off-by: Richard Henderson --- target/nios2/cpu.h| 3 --- target/nios2/helper.h | 1 + target/nios2/helper.c | 7 --- target/nios2/nios2-semi.c | 3 ++- target/nios2/translate.c | 2 +- 5 fi

[PATCH 36/43] target/m68k: Use guestfd.h to implement syscalls.

This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Signed-off-by: Richard Henderson --- target/m68k/m68k-semi.c | 268 ++-- 1 file changed, 38 insertions(+), 230 deletions(-) diff

[PATCH 35/43] target/m68k: Make semihosting system only

While we had a call to do_m68k_semihosting in linux-user, it wasn't actually reachable. We don't include DISAS_INSN(halt) as an instruction unless system mode. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 5 - target/m68k/m68k-semi.c| 37 +--

[PATCH 29/43] semihosting: Split out semihost_sys_rename

Split out the non-ARM specific portions of SYS_RENAME to a reusable function. This doesn't use GuestFD, but it does reuse validate_strlen() from semihost_sys_open. Signed-off-by: Richard Henderson --- include/semihosting/guestfd.h | 4 +++ semihosting/arm-compat-semi.c | 21 + semi

[PATCH 34/43] target/m68k: Eliminate m68k_semi_is_fseek

Reorg m68k_semi_return_* to gdb_syscall_complete_cb. Use the 32-bit version normally, and the 64-bit version for HOSTED_LSEEK. Signed-off-by: Richard Henderson --- target/m68k/m68k-semi.c | 55 + 1 file changed, 23 insertions(+), 32 deletions(-) diff --gi

  1   2   >