and make routine aspeed_soc_get_irq() common to all SoCs. This will be
useful to share code.
Cc: Jamin Lin
Cc: Peter Delevoryas
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_ast10x0.c | 5 +++--
hw/arm/aspeed_ast2600.c | 5 +++--
Markus Armbruster writes:
> Commit 05ebf841ef "qapi: Enforce command naming rules" inserted new
> code between a comment and the code it applies to. Move the comment
> back to its code, and add one for the new code.
>
> Signed-off-by: Markus Armbruster
Queued.
Queued.
Andrea Bolognani writes:
> If patch 8/8 is accepted, 7/8 should be squashed into it to reduce
> churn.
Done & queued. Thanks!
Markus Armbruster writes:
> Eric Blake writes:
>
>> On Tue, May 03, 2022 at 09:37:37AM +0200, Andrea Bolognani wrote:
>>> Perfectly aligned things look pretty, but keeping them that
>>> way as the schema evolves requires churn, and in some cases
>>> newly-added lines are not aligned properly.
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
slirp | 2 +-
target/riscv/cpu.c | 23 ---
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/slirp b/slirp
index 9d59bb775d..a88d9ace23 16
- enable zb* extensions by default will make cpu types(such as sifive-u34)
implicitly support zb* extensions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c
在 2022/5/15 上午10:56, Tsukasa OI 写道:
We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.
Signed-off-by: Tsukasa OI
---
target/riscv/cpu.c | 31 ---
1 file changed, 16 insertions(+), 15
With the latest, manually built TF-A, I was able to boot a72, but not
max. Since `max` type is supported by TF-A, I think it might be
a Qemu issue.
On Mon, May 16, 2022 at 8:21 AM Itaru Kitayama wrote:
>
> Leif,
>
> I've so far only booted sbsa-ref with cortex-a57, is this only CPU
> type
t; > staging (2022-05-03 09:13:17 -0700)
> >
> > are available in the Git repository at:
> >
> >https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
> >
> > for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
> &
Leif,
I've so far only booted sbsa-ref with cortex-a57, is this only CPU
type supported by the board? I'm using TF-A's latest branch, but the
PLAT=qemu_sbsa is at this moment, kind of outdated.
Itaru.
/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
target/openrisc: Do not reset delay slot flag on early tb exit (2022-05-15
10:33:01 +0900)
OpenRISC Fixes
> On May 15, 2022, at 2:10 PM, Cédric Le Goater wrote:
>
> and make routine aspeed_soc_get_irq() common to all SoCs. This will be
> useful to share code.
>
> Cc: Jamin Lin
> Cc: Peter Delevoryas
> Signed-off-by: Cédric Le Goater
> ---
> include/hw/arm/aspeed_soc.h | 3 +++
>
> On May 15, 2022, at 2:19 PM, Cédric Le Goater wrote:
>
> [ ... ]
>
>>> The problem is that it is breaking compatibility with previous QEMUs.
>> It is? We can still run things the old way too, I specifically
>> wrote this with the intention that it would support backwards
>> compatibility.
>
[ ... ]
The problem is that it is breaking compatibility with previous QEMUs.
It is? We can still run things the old way too, I specifically
wrote this with the intention that it would support backwards
compatibility.
You are right. Let's start with your patchset. We can add the "uart"
and make routine aspeed_soc_get_irq() common to all SoCs. This will be
useful to share code.
Cc: Jamin Lin
Cc: Peter Delevoryas
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_ast10x0.c | 3 ++-
hw/arm/aspeed_ast2600.c | 3 ++-
在 2022/5/15 下午10:45, Tsukasa OI 写道:
On 2022/05/15 23:37, Weiwei Li wrote:
在 2022/5/15 上午10:56, Tsukasa OI 写道:
QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.
This commit adds certain checks for consistent FP arithmetic:
- F requires
On 2022/05/15 23:37, Weiwei Li wrote:
>
> 在 2022/5/15 上午10:56, Tsukasa OI 写道:
>> QEMU allowed inconsistent configurations that made floating point
>> arithmetic effectively unusable.
>>
>> This commit adds certain checks for consistent FP arithmetic:
>>
>> - F requires Zicsr
>> - Zfinx
在 2022/5/15 上午10:56, Tsukasa OI 写道:
QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.
This commit adds certain checks for consistent FP arithmetic:
- F requires Zicsr
- Zfinx requires Zicsr
- Zfh/Zfhmin require F
- D requires F
- V
Add a new 'guest-get-diskstats' command for report disk io statistics
for Linux guests. This can be usefull for getting io flow or handling
IO fault, no need to enter guests.
Signed-off-by: luzhipeng
---
Changes v2->v3:
bugfix for memory leak
Changes v1->v2:
Hi All,
I am trying to create a virtual mem2mem scaler device in QEMU (for the
purposes of writing a mem2mem driver tutorial). I created the mem2mem
device as shown here.
https://github.com/karthikpoduval/qemu/blob/scaler-bringup/hw/misc/m2m_scaler.c
I added this MMIO device to the arm virt.c
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