Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V

On Tue, May 17, 2022 at 1:54 PM Alistair Francis wrote: > > On Tue, May 17, 2022 at 6:52 PM Daniel P. Berrangé > wrote: > > > > On Tue, May 17, 2022 at 03:03:38PM +1000, Alistair Francis wrote: > > > On Sat, May 7, 2022 at 6:30 AM Atish Kumar Patra > > > wrote: > > > > > > > > On Fri, May 6, 2

Attaching qcow2 images to containers

Hi Kirill, I saw your "[PATCH 0/4] dm: Introduce dm-qcow2 driver to attach QCOW2 files as block device" patch series: https://lore.kernel.org/linux-kernel/ykme5zs2cpxun...@infradead.org/T/ There has been recent work in vDPA (VIRTIO Data Path Acceleration) to achieve similar functionality. The qemu

RE: QEMU cpu socket allocation

Hi Peter Thanks. Yes, I believe (Sockets,Cores,Threads) = (1,16,1) should be the best performance, as the VM does not need to access the memory of another NUMA node. So, is it a bug that Virt Manager uses more Sockets by default, when i choose "Copy host CPU Configuration" ? regards, Rajesh A

Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

On Sat, May 14, 2022 at 12:46 AM Frank Chang wrote: > > On Fri, May 13, 2022 at 11:58 PM Atish Kumar Patra > wrote: >> >> On Thu, May 12, 2022 at 11:29 PM Frank Chang wrote: >> > >> > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote: >> >> >> >> From: Atish Patra >> >> >> >> mcycle/minstret

Re: [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability

pin On Mon, May 16, 2022 at 9:54 PM Wang,Liang(ACG CCN01) wrote: > When vfio-pci devices are attached to the downstream, pcie acs > > capability may be needed, Consistent with physical machine. > > > It has been tested in our environment, and pcie acs capability > > is required in some scenarios

Re: [PATCH 4/9] vfio/migration: Skip pre-copy if dirty page tracking is not supported

On Tue, 17 May 2022 14:39:37 -0300 Jason Gunthorpe wrote: > On Tue, May 17, 2022 at 11:22:32AM -0600, Alex Williamson wrote: > > > > > It seems like a better solution would be to expose to management > > > > tools that the VM contains a device that does not support the > > > > pre-copy phase so

[PULL 6/8] net/vmnet: update qemu-options.hx

From: Vladislav Yaroshchuk Update qemu-options.hx to support vmnet networking backend. Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- qemu-options.hx | 25 + 1 file changed, 25 insertions(+) diff

[PULL 3/8] net/vmnet: implement shared mode (vmnet-shared)

From: Vladislav Yaroshchuk Interaction with vmnet.framework in different modes differs only on configuration stage, so we can create common `send`, `receive`, etc. procedures and reuse them. Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Phillip Tennen Signed-off-by: Vladi

[PULL 5/8] net/vmnet: implement bridged mode (vmnet-bridged)

From: Vladislav Yaroshchuk Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- net/vmnet-bridged.m | 137 ++-- 1 file changed, 132 insertions(+), 5 deletions(-) diff --git a/net/vmnet-b

[PULL 7/8] net/vmnet: update hmp-commands.hx

From: Vladislav Yaroshchuk Update HMP for supporting vmnet. Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- hmp-commands.hx | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hmp-commands.hx b/hmp-co

[PULL 1/8] net/vmnet: add vmnet dependency and customizable option

From: Vladislav Yaroshchuk vmnet.framework dependency is added with 'vmnet' option to enable or disable it. Default value is 'auto'. used vmnet features are available since macOS 11.0, but new backend can be built and work properly with subset of them on 10.15 too. Reviewed-by: Akihiko Odaki T

[PULL 8/8] tulip: Assign default MAC address if not specified

From: Helge Deller The MAC of the tulip card is stored in the EEPROM and at startup tulip_fill_eeprom() is called to initialize the EEPROM with the MAC address given on the command line, e.g.: -device tulip,mac=00:11:22:33:44:55 In case the mac address was not given on the command line, tuli

[PULL 0/8] Net patches

The following changes since commit eec398119fc6911d99412c37af06a6bc27871f85: Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2022-05-16 16:31:01 -0700) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request

[PULL 4/8] net/vmnet: implement host mode (vmnet-host)

From: Vladislav Yaroshchuk Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- net/vmnet-host.c | 116 --- 1 file changed, 110 insertions(+), 6 deletions(-) diff --git a/net/vmnet-h

[PULL 2/8] net/vmnet: add vmnet backends to qapi/net

From: Vladislav Yaroshchuk Create separate netdevs for each vmnet operating mode: - vmnet-host - vmnet-shared - vmnet-bridged Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Acked-by: Markus Armbruster Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- net/clients.h

Re: [PATCH v22 3/7] net/vmnet: implement shared mode (vmnet-shared)

On Wed, May 18, 2022 at 11:01 AM osy wrote: > > On Thu, Mar 17, 2022 at 10:28 AM Vladislav Yaroshchuk > wrote: > > > > Interaction with vmnet.framework in different modes > > differs only on configuration stage, so we can create > > common `send`, `receive`, etc. procedures and reuse them. > > >

Re: [PATCH qemu] spapr: Use address from elf parser for kernel address

On 5/18/22 04:58, Daniel Henrique Barboza wrote: Alexey, I had to amend your commit due to Gitlab CI complaining about ... On 5/4/22 03:55, Alexey Kardashevskiy wrote: tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on. QEMU loads the kernel at 0x40 by default which wo

[PATCH] target/riscv: add support for zmmul extension v0.1

- includes all multiplication operations for M extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_rvm.c.inc | 18 -- 3 files changed,

[PATCH v4] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

- setting ext_g will implicitly set ext_i Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d0

Re: [PATCH 1/2] acpi/nvdimm: Create _LS{I,R,W} method for NVDIMM device

On Fri, 2022-05-06 at 11:23 +0200, Igor Mammedov wrote: > > > > > No, sorry, I didn't explain it clear. > > No extra interface/ABI but these 3 must _LS{I,R,W} nvdimm-sub- > > device > > methods. Of course, I'm going to extract 'SystemIO' and > > 'SystemMemory' > > operation regions out of NACL to

Re: [RFC PATCH 9/9] iotests: use tests/venv for running tests

On Mon, May 16, 2022 at 3:41 AM Paolo Bonzini wrote: > > On 5/14/22 17:55, John Snow wrote: > > On Fri, May 13, 2022, 11:33 AM Paolo Bonzini > > wrote: > > IIRC we have some cases (FreeBSD?) where only the python3.x executable > > is available. This is why we

Re: [PATCH v2] gitlab-ci: Switch the container of the 'check-patch' & 'check-dco' jobs

On Mon, May 16, 2022 at 4:26 AM Daniel P. Berrangé wrote: > > On Mon, May 16, 2022 at 10:23:10AM +0200, Thomas Huth wrote: > > The 'check-patch' and 'check-dco' jobs only need Python and git for > > checking the patches, so it's not really necessary to use a container > > here that has all the oth

The fate of iotest 297

Hi Kevin, I remember that you wanted some minimum Niceness threshold in order to agree to me removing iotest 297. I've already moved it onto GitLab CI in the form of the check-python-pipenv job, but I recall you wanted to be able to run it locally as well before agreeing to axe 297. I remember th

RE: [PATCH] target/arm: Make number of counters in PMCR follow the CPU

Hi, Peter. > Shuuichirou, Itaru: this is another patch where we need to know > an A64FX register value... Sorry for the late reply. The initial value of the pmcr_el0 register in A64FX is 0x46014040. After applying this Peter's patch, should we submit a new patch as a64fx patch from us? or do y

Re: [PATCH v3] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

On Tue, May 17, 2022 at 5:28 PM Weiwei Li wrote: > > - setting ext_g will implicitly set ext_i > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/cpu.c | 26 +- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/target/ris

Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V

On Tue, May 17, 2022 at 6:52 PM Daniel P. Berrangé wrote: > > On Tue, May 17, 2022 at 03:03:38PM +1000, Alistair Francis wrote: > > On Sat, May 7, 2022 at 6:30 AM Atish Kumar Patra > > wrote: > > > > > > On Fri, May 6, 2022 at 4:00 AM Peter Maydell > > > wrote: > > > > > > > > On Fri, 6 May 20

Re: [PATCH v2] hw/arm: add versioning to sbsa-ref machine DT

On Tue, May 17, 2022 at 11:50 AM Peter Maydell wrote: > > On Tue, 17 May 2022 at 14:27, Rob Herring wrote: > > > > On Thu, May 5, 2022 at 6:41 AM Leif Lindholm > > wrote: > > > > > > The sbsa-ref machine is continuously evolving. Some of the changes we > > > want to make in the near future, to

Re: QEMU cpu socket allocation

Hi Rajesh, Would the more intuitive CPU setting of (Sockets,Cores,Threads) = (1,16,1) be ok? Thanks. On Tue, May 17, 2022 at 10:03 AM Rajesh A wrote: > Hi QEMU dev > > > > Virt Manager is able to configure a QEMU VM with more CPU sockets than the > physical host has. > > For example, in the b

[PATCH v6 12/13] tests: Add postcopy tls recovery migration test

It's easy to build this upon the postcopy tls test. Rename the old postcopy recovery test to postcopy/recovery/plain. Signed-off-by: Peter Xu --- tests/qtest/migration-test.c | 33 ++--- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/tests/qtest/migra

[PATCH v6 08/13] migration: Export tls-[creds|hostname|authz] params to cmdline too

It's useful for specifying tls credentials all in the cmdline (along with the -object tls-creds-*), especially for debugging purpose. The trick here is we must remember to not free these fields again in the finalize() function of migration object, otherwise it'll cause double-free. The thing is w

[PATCH v6 13/13] tests: Add postcopy preempt tests

Four tests are added for preempt mode: - Postcopy plain - Postcopy recovery - Postcopy tls - Postcopy tls+recovery Signed-off-by: Peter Xu --- tests/qtest/migration-test.c | 54 1 file changed, 54 insertions(+) diff --git a/tests/qtest/migration-tes

[PATCH v6 11/13] tests: Add postcopy tls migration test

We just added TLS tests for precopy but not postcopy. Add the corresponding test for vanilla postcopy. Rename the vanilla postcopy to "postcopy/plain" because all postcopy tests will only use unix sockets as channel. Signed-off-by: Peter Xu --- tests/qtest/migration-test.c | 50 +++

[PATCH v6 07/13] migration: Add helpers to detect TLS capability

Add migrate_channel_requires_tls() to detect whether the specific channel requires TLS, leveraging the recently introduced migrate_use_tls(). No functional change intended. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Peter Xu --- migration/channel.c | 9 ++--- migration/migration.

[PATCH v6 10/13] migration: Respect postcopy request order in preemption mode

With preemption mode on, when we see a postcopy request that was requesting for exactly the page that we have preempted before (so we've partially sent the page already via PRECOPY channel and it got preempted by another postcopy request), currently we drop the request so that after all the other p

[PATCH v6 04/13] migration: Postcopy recover with preempt enabled

To allow postcopy recovery, the ram fast load (preempt-only) dest QEMU thread needs similar handling on fault tolerance. When ram_load_postcopy() fails, instead of stopping the thread it halts with a semaphore, preparing to be kicked again when recovery is detected. A mutex is introduced to make

[PATCH v6 09/13] migration: Enable TLS for preempt channel

This patch is based on the async preempt channel creation. It continues wiring up the new channel with TLS handshake to destionation when enabled. Note that only the src QEMU needs such operation; the dest QEMU does not need any change for TLS support due to the fact that all channels are establi

[PATCH v6 05/13] migration: Create the postcopy preempt channel asynchronously

This patch allows the postcopy preempt channel to be created asynchronously. The benefit is that when the connection is slow, we won't take the BQL (and potentially block all things like QMP) for a long time without releasing. A function postcopy_preempt_wait_channel() is introduced, allowing the

[PATCH v6 06/13] migration: Add property x-postcopy-preempt-break-huge

Add a property field that can conditionally disable the "break sending huge page" behavior in postcopy preemption. By default it's enabled. It should only be used for debugging purposes, and we should never remove the "x-" prefix. Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Manish Mishra

[PATCH v6 03/13] migration: Postcopy preemption enablement

This patch enables postcopy-preempt feature. It contains two major changes to the migration logic: (1) Postcopy requests are now sent via a different socket from precopy background migration stream, so as to be isolated from very high page request delays. (2) For huge page enabled hosts:

[PATCH v6 02/13] migration: Postcopy preemption preparation on channel creation

Create a new socket for postcopy to be prepared to send postcopy requested pages via this specific channel, so as to not get blocked by precopy pages. A new thread is also created on dest qemu to receive data from this new channel based on the ram_load_postcopy() routine. The ram_load_postcopy(PO

[PATCH v6 00/13] migration: Postcopy Preemption

This is v6 of postcopy preempt series. It can also be found here: https://github.com/xzpeter/qemu/tree/postcopy-preempt RFC: https://lore.kernel.org/qemu-devel/20220119080929.39485-1-pet...@redhat.com V1: https://lore.kernel.org/qemu-devel/20220216062809.57179-1-pet...@redhat.com V2: https:/

[PATCH v6 01/13] migration: Add postcopy-preempt capability

Firstly, postcopy already preempts precopy due to the fact that we do unqueue_page() first before looking into dirty bits. However that's not enough, e.g., when there're host huge page enabled, when sending a precopy huge page, a postcopy request needs to wait until the whole huge page that is sen

Re: [PATCH v3 0/3] Misc AC97 clean ups

On Mon, 9 May 2022, BALATON Zoltan wrote: On Mon, 2 May 2022, BALATON Zoltan wrote: On Sat, 23 Apr 2022, BALATON Zoltan wrote: During trying to implement via-ac97 I did some small clean ups to ac97 which is in this series. The via-ac97 is not working yet so that's not included but these unrelat

Re: [PATCH v3 8/8] linux-user: Add PowerPC ISA 3.1 and MMA to hwcap

On 5/17/22 11:37, Lucas Mateus Castro(alqotel) wrote: From: Joel Stanley These are new hwcap bits added for power10. Signed-off-by: Joel Stanley Signed-off-by: Lucas Mateus Castro (alqotel) --- linux-user/elfload.c | 4 1 file changed, 4 insertions(+) Reviewed-by: Richard Henderson

Re: [PATCH v3 5/8] target/ppc: Implemented xvf16ger*

On 5/17/22 11:37, Lucas Mateus Castro(alqotel) wrote: +static inline float32 bfp32_negate(float32 a) +{ +if (unlikely(((a & 0x7f80) == 0x7f80) && (a & 0x007f))) { float32_is_any_nan. +if (neg_mul) { +msum = bfp32_negate(msum); +

Re: [PATCH v3 4/8] target/ppc: Implemented xvf*ger*

On 5/17/22 11:37, Lucas Mateus Castro(alqotel) wrote: +if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) { +if (acc) { +muladd(at, a, b, i, j, op_flags, excp_ptr); +} else { +mul(at, a, b, i, j, op_flags, excp_ptr); +

Re: [PATCH v3 3/8] target/ppc: Implemented pmxvi*ger* instructions

On 5/17/22 11:37, Lucas Mateus Castro(alqotel) wrote: From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Uns

Re: [PATCH RESEND 10/10] target/ppc: implement cdtbcd

On 5/17/22 09:47, Víctor Colombo wrote: From: Matheus Ferst Implements the Convert Declets To Binary Coded Decimal instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero exponent is used as an intermediate

Re: [PATCH RESEND 09/10] target/ppc: implement cbcdtd

On 5/17/22 09:47, Víctor Colombo wrote: From: Matheus Ferst Implements the Convert Binary Coded Decimal To Declets instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to decimal32 format, from which the de

Re: [PATCH RESEND 08/10] target/ppc: implement addg6s

On 5/17/22 09:47, Víctor Colombo wrote: +static bool trans_ADDG6S(DisasContext *ctx, arg_X *a) +{ +const uint64_t nibbles = 0x0f0f0f0f0f0f0f0fULL, + carry_bits = 0x1010101010101010ULL; +TCGv t0, t1, t2; + +REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206); + +t0 = tcg_temp_

Re: [PATCH v3] mos6522: fix linking error when CONFIG_MOS6522 is not set

On 5/16/22 11:33, Thomas Huth wrote: On 16/05/2022 16.14, Daniel Henrique Barboza wrote: On 5/10/22 20:54, Murilo Opsfelder Araujo wrote: When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails: /usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158): und

Re: [PATCH] target/ppc: Fix tlbie

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 5/3/22 13:39, Leandro Lupori wrote: Commit 74c4912f097bab98 changed check_tlb_flush() to use tlb_flush_all_cpus_synced() instead of calling tlb_flush() on each CPU. However, as side effect of this, a CPU executing a ptesync af

Re: [PATCH RESEND 04/10] target/ppc: Move mffsce to decodetree

On 5/17/22 09:47, Víctor Colombo wrote: -static void do_mffsc(int rt, uint64_t set_mask) +static void do_mffsc(int rt, TCGv_i64 t1, uint64_t set_mask, + uint64_t clear_mask, uint32_t fpscr_mask) { TCGv_i64 fpscr; @@ -618,6 +619,12 @@ static void do_mffsc(int rt, uin

Re: [PATCH qemu] spapr: Use address from elf parser for kernel address

Alexey, I had to amend your commit due to Gitlab CI complaining about ... On 5/4/22 03:55, Alexey Kardashevskiy wrote: tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on. QEMU loads the kernel at 0x40 by default which works most of the time as Linux kernels are relocatable

Re: [PATCH] hostmem: default the amount of prealloc-threads to smp-cpus

On 5/17/22 14:38, dzej...@gmail.com wrote: From: Jaroslav Jindrak Prior to the introduction of the prealloc-threads property, the amount of threads used to preallocate memory was derived from the value of smp-cpus passed to qemu, the amount of physical cpus of the host and a hardcoded maximum v

Re: [PATCH RESEND 07/10] target/ppc: Add flag for ISA v2.06 BCDA instructions

On 5/17/22 09:47, Víctor Colombo wrote: From: Matheus Ferst Adds an insns_flags2 for the BCD assist instructions introduced in Power ISA 2.06. These instructions are not listed in the manuals for e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10 models. [1]https://www.nxp.com/f

Re: [PATCH 01/16] configure: do not define or use the CPP variable

On 5/17/22 20:07, Richard Henderson wrote: Although I'm surprised we need to do this pipe thing. Surely just rely on the assembler-with-cpp rule built into the compiler driver.  Are we using a custom AS in this case? No, I don't think so. I'm also surprised, but decided to change as little a

Re: [PATCH RESEND 06/10] target/ppc: Implement mffscdrn[i] instructions

On 5/17/22 09:47, Víctor Colombo wrote: Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 5 + target/ppc/translate/fp-impl.c.inc | 35 ++ 2 files changed, 40 insertions(+) Reviewed-by: Richard Henderson r~

[PATCH v3 8/8] linux-user: Add PowerPC ISA 3.1 and MMA to hwcap

From: Joel Stanley These are new hwcap bits added for power10. Signed-off-by: Joel Stanley Signed-off-by: Lucas Mateus Castro (alqotel) --- linux-user/elfload.c | 4 1 file changed, 4 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 61063fd974..0908692e62 100

[PATCH v3 7/8] target/ppc: Implemented [pm]xvbf16ger2*

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update) xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Negative accumulate xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negati

[PATCH v3 6/8] target/ppc: Implemented pmxvf*ger*

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate

[PATCH v3 3/8] target/ppc: Implemented pmxvi*ger* instructions

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Po

[PATCH v3 2/8] target/ppc: Implemented xvi*ger* instructions

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate xvi8ger4: VSX

Re: [PATCH RESEND 03/10] target/ppc: Move mffsl to decodetree

On 5/17/22 09:47, Víctor Colombo wrote: -do_mffsc(a->rt); +do_mffsc(a->rt, 0xULL); BTW, prefer -1 or ~0 or UINT64_MAX. No one needs to count F's. r~

[PATCH v3 5/8] target/ppc: Implemented xvf16ger*

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvf16ger2: VSX Vector 16-bit Floating-Point GER (rank-2 update) xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate xvf16ger2np: VSX Vector 16-bit Float

[PATCH v3 4/8] target/ppc: Implemented xvf*ger*

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update) xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate xvf32gernp: VSX Vector 32-bit Floating

[PATCH v3 1/8] target/ppc: Implement xxm[tf]acc and xxsetaccz

From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xxmfacc: VSX Move From Accumulator xxmtacc: VSX Move To Accumulator xxsetaccz: VSX Set Accumulator to Zero The PowerISA 3.1 mentions that for the current version of the architecture, "the hardware implement

[PATCH v3 0/8] VSX MMA Implementation

From: "Lucas Mateus Castro (alqotel)" Based-on: <20220517161522.36132-1-victor.colo...@eldorado.org.br> This patch series is a patch series of the Matrix-Multiply Assist (MMA) instructions implementation from the PowerISA 3.1 These and the VDIV/VMOD implementation are the last new PowerISA 3.1

[PATCH] linux-user: fix ioctl() arguments printing in strace support

When both of the following conditions are satisfied, ioctl() arguments printing in strace support is not working: - highest bit of ioctl() request command is 1 - sizeof abi_long is 8 bytes print_ioctl() and print_syscall_ret_ioctl() find IOCTLEntry by this way: /* ie->target_cmd is in

Re: [PATCH RESEND 03/10] target/ppc: Move mffsl to decodetree

On 5/17/22 09:47, Víctor Colombo wrote: Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 4 target/ppc/translate/fp-impl.c.inc | 27 --- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 12 insertions(+), 21 deletions(-) Review

Re: [PATCH RESEND 02/10] target/ppc: Move mffs[.] to decodetree

On 5/17/22 09:47, Víctor Colombo wrote: index cfb27bd020..e167f7a478 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -607,6 +607,31 @@ static void gen_mffs(DisasContext *ctx) tcg_temp_free_i64(t0); } +static void do_mffsc(int rt) Perhaps cl

Re: [PATCH RESEND 01/10] target/ppc: Fix insn32.decode style issues

On 5/17/22 09:47, Víctor Colombo wrote: Some lines in insn32.decode have inconsistent alignment when compared to others. Fix this by changing the alignment of some lines, making it more consistent throughout the file. Signed-off-by: Víctor Colombo Reviewed-by: Richard Henderson r~

Re: [PATCH 09/16] configure: handle host compiler in probe_target_compiler

On 5/17/22 02:26, Paolo Bonzini wrote: In preparation for handling more binaries than just cc, handle the case of "probe_target_compiler $cpu" directly in the function, setting the target_* variables based on the ones that are used to build QEMU. The clang check also needs to be moved after this

Re: [PATCH 08/16] configure: add missing cross compiler fallbacks

On 5/17/22 02:26, Paolo Bonzini wrote: The arm compiler can be used for armeb, and the sparc64 compiler can be used for sparc. Signed-off-by: Paolo Bonzini --- configure | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 07/16] tests/tcg: merge configure.sh back into main configure script

On 5/17/22 02:26, Paolo Bonzini wrote: tests/tcg/configure.sh has a complicated story. In the beginning its code ran as part of the creation of config-target.mak files, and that is where it placed the information on the target compiler. However, probing for the buildability of TCG tests required

Re: [PATCH 06/16] tests/tcg: correct target CPU for sparc32

On 5/17/22 02:26, Paolo Bonzini wrote: We do not want v8plus for pure sparc32, as the difference with the V8 ABI are only meaningful on 64-bit CPUs suh as ultrasparc; supersparc is the best CPU to use for 32-bit. s/suh/such/ Reviewed-by: Richard Henderson r~

Re: [PATCH 04/16] build: do a full build before running TCG tests

On 5/17/22 02:26, Paolo Bonzini wrote: TCG tests need both QEMU and firmware to be built, so do "ninja all" before trying to run them. Signed-off-by: Paolo Bonzini --- tests/Makefile.include | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 02/16] build: clean up ninja invocation

On 5/17/22 02:26, Paolo Bonzini wrote: Fix an incorrect "@@:" and move "-d keepdepfile" to the NINJAFLAGS variable. Signed-off-by: Paolo Bonzini --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 01/16] configure: do not define or use the CPP variable

On 5/17/22 02:26, Paolo Bonzini wrote: Just hardcode $(CC) -E, it should be enough. Signed-off-by: Paolo Bonzini --- configure | 3 --- pc-bios/optionrom/Makefile | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) Reviewed-by: Richard Henderson %.o: %.S -

Re: [PATCH] target/arm: Fix PAuth keys access checks for disabled SEL2

On 5/17/22 07:52, Florian Lugou wrote: As per the description of the HCR_EL2.APK field in the ARMv8 ARM, Pointer Authentication keys accesses should only be trapped to Secure EL2 if it is enabled. Signed-off-by: Florian Lugou --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH 4/9] vfio/migration: Skip pre-copy if dirty page tracking is not supported

On Tue, May 17, 2022 at 11:22:32AM -0600, Alex Williamson wrote: > > > It seems like a better solution would be to expose to management > > > tools that the VM contains a device that does not support the > > > pre-copy phase so that downtime expectations can be adjusted. > > > > I don't expect

Re: [PATCH 11/12] target/ppc: declare vmsumuhm helper with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with TCG_CALL_NO_RWG, and drop the unused env argument. Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 ++-- target/ppc/in

Re: [PATCH 12/12] target/ppc: declare vmsumshm helper with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: -DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr) -DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr) +DEF_HELPER_FLAGS_4(VMSUMSHM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) +DEF_HELPER_5(VMSUMSHS, void, env, avr, avr, avr, avr) Si

Re: [PATCH 11/12] target/ppc: declare vmsumuhm helper with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with TCG_CALL_NO_RWG, and drop the unused env argument. Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 ++-- target/ppc/insn

Re: [PATCH 10/12] target/ppc: declare vmsum[um]bm helpers with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Move vmsumubm and vmsummbm to decodetree, declare both helpers with TCG_CALL_NO_RWG, and drop the unused env argument. Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 ++-- target/ppc/insn32.d

Re: [PATCH 09/12] target/ppc: introduce do_va_helper

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/translate/vmx-impl.c.inc | 32 + 1 file changed, 5 insertions(+), 27 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 08/12] target/ppc: declare xxextractuw and xxinsertw helpers with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Move xxextractuw and xxinsertw to decodetree, declare both helpers with TCG_CALL_NO_RWG, and drop the unused env argument. Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 +- target/ppc/insn3

Re: [PATCH 07/12] target/ppc: declare xvxsigsp helper with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Move xvxsigsp to decodetree, declare helper_xvxsigsp with TCG_CALL_NO_RWG, and drop the unused env argument. Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 2 +- target/ppc/helper.h

Re: [PATCH 4/9] vfio/migration: Skip pre-copy if dirty page tracking is not supported

On Tue, 17 May 2022 13:08:44 -0300 Jason Gunthorpe wrote: > On Tue, May 17, 2022 at 10:00:45AM -0600, Alex Williamson wrote: > > > > This is really intended to be a NOP from where things are now, as if > > > you use mlx5 live migration without a patch like this then it causes a > > > botched pre

Re: [PATCH v2] hw/arm: add versioning to sbsa-ref machine DT

On Tue, 17 May 2022 at 14:27, Rob Herring wrote: > > On Thu, May 5, 2022 at 6:41 AM Leif Lindholm > wrote: > > > > The sbsa-ref machine is continuously evolving. Some of the changes we > > want to make in the near future, to align with real components (e.g. > > the GIC-700), will break compatibi

Re: [PATCH] target/i386: Remove LBREn bit check when access Arch LBR MSRs

On 5/17/22 17:50, Yang Weijiang wrote: Live migration can happen when Arch LBR LBREn bit is cleared, e.g., when migration happens after guest entered SMM mode. In this case, we still need to migrate Arch LBR MSRs. Signed-off-by: Yang Weijiang --- target/i386/kvm/kvm.c | 21 +--

Re: [PATCH 06/12] target/ppc: declare xscvspdpn helper with call flags

On 5/17/22 05:39, matheus.fe...@eldorado.org.br wrote: -uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb) +uint64_t helper_XSCVSPDPN(uint64_t xb) { return helper_todouble(xb >> 32); } Ideally, this helper would not exist and you'd just use helper_todouble... +bool trans_XSCVS

[PATCH RESEND 09/10] target/ppc: implement cbcdtd

From: Matheus Ferst Implements the Convert Binary Coded Decimal To Declets instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to decimal32 format, from which the declets are extracted. Where the behavior

[PATCH RESEND 10/10] target/ppc: implement cdtbcd

From: Matheus Ferst Implements the Convert Declets To Binary Coded Decimal instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero exponent is used as an intermediate value to convert the declets. Signed-of

[PATCH RESEND 06/10] target/ppc: Implement mffscdrn[i] instructions

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 5 + target/ppc/translate/fp-impl.c.inc | 35 ++ 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 682990b7f0..a3e87a0867 100644 --- a/ta

[PATCH RESEND 08/10] target/ppc: implement addg6s

From: Matheus Ferst Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 4 +++ target/ppc/translate/fixedpoint-impl.c.inc | 35 ++

[PATCH RESEND 07/10] target/ppc: Add flag for ISA v2.06 BCDA instructions

From: Matheus Ferst Adds an insns_flags2 for the BCD assist instructions introduced in Power ISA 2.06. These instructions are not listed in the manuals for e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10 models. [1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM

[PATCH RESEND 04/10] target/ppc: Move mffsce to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 1 + target/ppc/translate/fp-impl.c.inc | 45 +++--- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 18 insertions(+), 30 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/i

[PATCH RESEND 03/10] target/ppc: Move mffsl to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 4 target/ppc/translate/fp-impl.c.inc | 27 --- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 12 insertions(+), 21 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/i

[PATCH RESEND 05/10] target/ppc: Move mffscrn[i] to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 5 ++ target/ppc/internal.h | 3 -- target/ppc/translate/fp-impl.c.inc | 80 ++ target/ppc/translate/fp-ops.c.inc | 4 -- 4 files changed, 20 insertions(+), 72 deletions(-) diff --

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