On Sat, May 14, 2022 at 4:39 AM Atish Patra wrote:
>
> stimecmp allows the supervisor mode to update stimecmp CSR directly
> to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra
> ---
> target/riscv/cpu.c
In fetch_or_create_notifier, idx begins with 0. So the GPtrArray size
should be idx + 1 and g_ptr_array_set_size should be called with idx + 1.
This wrong GPtrArray size causes fetch_or_create_notifier return an invalid
address. Passing this invalid pointer to vhost_user_host_notifier_remove
cause
On 5/24/2022 4:29 PM, Gerd Hoffmann wrote:
On Tue, May 24, 2022 at 04:11:56PM +0800, Xiaoyao Li wrote:
On 5/24/2022 2:59 PM, Gerd Hoffmann wrote:
On Tue, May 24, 2022 at 12:19:51PM +0800, Xiaoyao Li wrote:
On 5/23/2022 5:39 PM, Gerd Hoffmann wrote:
So, how is this supposed to work? Patch #2
On 5/24/2022 3:09 PM, Gerd Hoffmann wrote:
On Thu, May 12, 2022 at 11:17:47AM +0800, Xiaoyao Li wrote:
Before a TD can run, it needs to
- setup/configure TD HOB list;
- initialize TDVF into TD's private memory;
- initialize TD vcpu state;
Register a machine_init_done callback to all those
On 5/24/2022 3:08 PM, Gerd Hoffmann wrote:
On Thu, May 12, 2022 at 11:17:45AM +0800, Xiaoyao Li wrote:
TDX guest cannot go to real mode, so just skip the setup of isa-bios.
Does isa-bios setup cause any actual problems?
(same question for patch #19).
It causes mem_region split and mem_slot d
On Wed, May 25, 2022 at 11:56 PM Peter Xu wrote:
>
> On Wed, May 25, 2022 at 11:38:26PM +0800, Hyman Huang wrote:
> > > 2. Also this algorithm only control or limits dirty rate by guest
> > > writes. There can be some memory dirtying done by virtio based devices
> > > which is accounted only at qe
On 5/24/2022 3:02 PM, Gerd Hoffmann wrote:
Hi,
+static int tdvf_parse_section_entry(const TdvfSectionEntry *src,
+ TdxFirmwareEntry *entry)
+/* sanity check */
That is what the whole function is doing. So rename it to
tdvf_check_section_entry to
On 5/25/2022 11:43 AM, Yuan Yao wrote:
On Tue, May 24, 2022 at 10:03:02PM +0800, Chenyi Qiang wrote:
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window means
From: Iris Chen
Add the W# pin and SRWD bit which control the status register write
ability.
Signed-off-by: Iris Chen
---
hw/block/m25p80.c | 72 +++
tests/qtest/aspeed_smc-test.c | 62 ++
2 files changed, 134 insertions(+
From: Iris Chen
Hey everyone,
My patch adds the W# pin and SRWD bit which work together to control the
status register write ability.
Accordingly, when W# is low and SRWD bit is high, hardware protection
mode (HPM) is initiated. All other cases result in software protection.
Acceptance test
On Sat, May 14, 2022 at 4:37 AM Atish Patra wrote:
>
> Historically, The mtime/mtimecmp has been part of the CPU because
> they are per hart entities. However, they actually belong to aclint
> which is a MMIO device.
>
> Move them to the ACLINT device. This also emulates the real hardware
> more c
If you invoke the check script from outside of the tests/qemu-iotests
directory, the directories initialized as source_iotests and
build_iotests will be incorrect.
We can use the location of the source file itself to be more accurate.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tes
This is needed to be able to add a venv-building step to 'make check';
the clang-user job in particular needs this to be able to run
check-unit.
Signed-off-by: John Snow
---
tests/docker/dockerfiles/debian10.docker | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/docker/dockerfiles/debi
Le 26/05/2022 à 00:26, Richard Henderson a écrit :
On 5/25/22 14:40, Laurent Vivier wrote:
+DISAS_INSN(trapcc)
+{
+ DisasCompare c;
+
+ /* Consume and discard the immediate operand. */
+ switch (extract32(insn, 0, 3)) {
+ case 2: /* trapcc.w */
+ (void)read_im16(env, s);
+
Remove the sys.path hacking from device-crash-test, and add in a little
user-friendly message for anyone who was used to running this script
directly from the source tree.
Modify the GitLab job recipes to create the tests/venv first, then run
device-crash-test from that venv.
Signed-off-by: John
This patch adds the "qemu" namespace package to the $build/tests/venv
directory. It does so in "editable" mode, which means that changes to
the source python directory will actively be reflected by the venv.
This patch also then removes any sys.path hacking from the avocado test
scripts directly.
Use "python3" instead of "python" as per PEP0394:
https://peps.python.org/pep-0394/
This should always be defined (in a venv, at least!), matching the
preferred python shebang of "#!/usr/bin/env python3".
Signed-off-by: John Snow
---
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+)
Turn off the nag warning coaxing us to upgrade pip. It's not really that
interesting to see in CI logs, and as long as nothing is broken --
nothing is broken.
Signed-off-by: John Snow
---
tests/Makefile.include | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/Makefil
This patch co-opts the virtual environment being used by avocado tests
to also run the basevm.py tests. This is being done in preparation for
for the qemu.qmp package being removed from qemu.git.
As part of the change, remove any sys.path() hacks and treat "qemu" as a
normal third-party import.
S
This is a convenience feature: $(PYTHON) points to the Python executable
we were instructed to use by the configure script. We use that Python to
create a virtual environment with the "check-venv" target in
tests/Makefile.include.
$(TESTS_PYTHON) points to the Python executable belonging to the vi
Factor out the "test venv pip" macro; rewrite the "check-venv" rule to
be a little more compact. Replace the "PIP" pseudo-command output with
"VENVPIP" to make it 1% more clear that we are talking about using pip
to install something into a venv.
Signed-off-by: John Snow
---
tests/Makefile.inclu
typeshed (included in mypy) recently updated to improve the typing for
WriteTransport objects. I was working around this, but now there's a
version where I shouldn't work around it.
Unfortunately this creates some minor ugliness if I want to support both
pre- and post-0.950 versions. For now, for
GitLab CI: https://gitlab.com/jsnow/qemu/-/pipelines/548326343
This series collects some of the uncontroversial elements that serve as
pre-requisites for a later series that seeks to generate a testing venv
by default.
This series makes the following material changes:
- Install the 'qemu' packag
Stefan Hajnoczi writes:
> [[PGP Signed Part:Undecided]]
> On Tue, May 24, 2022 at 04:40:56PM +0100, Alex Bennée wrote:
>> We don't have a virtio-gpio implementation in QEMU and only
>> support a vhost-user backend. The QEMU side of the code is minimal so
>> it should be enough to instantiate th
On 5/25/22 14:40, Laurent Vivier wrote:
+DISAS_INSN(trapcc)
+{
+ DisasCompare c;
+
+ /* Consume and discard the immediate operand. */
+ switch (extract32(insn, 0, 3)) {
+ case 2: /* trapcc.w */
+ (void)read_im16(env, s);
+ break;
+ case 3: /* trapcc.l */
+ (voi
On 5/25/22 12:28, Paolo Bonzini wrote:
The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:
Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into
staging (2022-05-20 08:04:30 -0700)
are available in the Git repository at:
https://gitlab.com/bo
Le 24/04/2022 à 18:49, Mark Cave-Ayland a écrit :
When initialising a drive ready to install MacOS, Apple HD SC Setup first
attempts
to format the drive. Add a simple FORMAT UNIT command which simply returns
success
to allow the format to succeed.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Trace (and others) is
supposed to record the next insn in PC and the address
of the trapping instruction in ADDRESS.
Create gen_raise_exception_format2 to reco
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Also mark raise_exception_ra and raise_exception, lest we
generate a warning about helper_raise_exception returning.
Signed-off-by: Richard Henderson
---
target/m68k/helper.h| 2 +-
target/m68k/op_helper.c | 5 +++--
2 files changed, 4
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Signed-off-by: Richard Henderson
---
tests/tcg/m68k/trap.c | 129 +
test
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 0cd7ef89e3..a3141d7f77 100644
--- a/targe
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index bb5ed1b7b1..0cd7ef89e3 100644
--- a/target/m68k/translate.c
+++
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
TPF stands for "trap false", and is a long-form nop for ColdFire.
Re-use the immediate consumption code from trapcc; the insn will
already expand to a nop because of the TCG_COND_NEVER test
within do_trapcc.
Signed-off-by: Richard Henderson
---
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754
Signed-off-by: Richard Henderson
---
target/m68k/cpu.h | 2 ++
linux-user/m68k/cpu_loop.c | 1 +
target/m68k/cpu.c | 1 +
target/m68k/op_helper.c| 6 +
On 5/25/2022 3:56 PM, Moger, Babu wrote:
On 5/24/22 18:23, Alejandro Jimenez wrote:
On 5/24/2022 3:48 PM, Moger, Babu wrote:
On 5/24/22 10:19, Igor Mammedov wrote:
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
CCing AMD folks as that might be of interest to them
I am trying
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
According to the M68040 Users Manual, section 8.4.3, Four word
This is in section 8.4.1
Reviewed-by: Laurent Vivier
stack frame (format 0), includes Illegal Instruction. Use the
correct frame format, which does not use the ADDR argument.
On 5/25/22 13:27, Anton Johansson wrote:
On 5/25/22 22:16, Richard Henderson wrote:
No:
* one patch to update libvirt-ci and does nothing else.
* one patch to update yml template.
* one patch to refresh.
Just like you enumerated before.
r~
Ah, right! Thanks for clarifying. Should I keep
Some points to consider:
The injected MCE has _done_ the damages to guest workload. Recovering
the guest poisoned memory doesn't help with the already happened guest
workload memory corruption / loss / interruption due to injected MCEs.
The hypervisor _must_ emulate poisons identified in guest ph
Signed-off-by: Peter Delevoryas
---
hw/i2c/aspeed_i2c.c | 118 ++--
include/hw/i2c/aspeed_i2c.h | 14 +++--
2 files changed, 124 insertions(+), 8 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 3f2dbe46df..01af647e0c 100644
--- a
The AST2600/AST1030 new register mode patches[1] and the I2C slave device
patches[2] will be really useful, but we still need DMA slave device
handling in the new register mode too for the use-cases I'm thinking of
(OpenBIC Zephyr kernel using Aspeed SDK drivers[3]).
My test images are on Github[4
https://github.com/legoater/qemu/ tags/pull-aspeed-20220525
for you to fetch changes up to 52bcd997800fab67d57bea6d93e368f6f7a93b24:
hw/arm/aspeed: Add i2c devices for AST2600 EVB (2022-05-25 16:22:37 +0200)
aspeed queue:
* Aspeed
On 5/25/22 22:16, Richard Henderson wrote:
No:
* one patch to update libvirt-ci and does nothing else.
* one patch to update yml template.
* one patch to refresh.
Just like you enumerated before.
r~
Ah, right! Thanks for clarifying. Should I keep all 3 patches in this
series?
--
Anton J
On 5/25/22 13:14, Anton Johansson wrote:
Just to make sure I understood you correctly, I should:
1. Make a standalone patch that updates libvirt-ci and runs
the refresh script, in case any package mappings changed
2. Change this patch to add flex/bison to QEMU's qemu.yml,
On 5/25/22 18:38, Alex Bennée wrote:
Richard Henderson writes:
On 5/25/22 05:29, Anton Johansson wrote:
For clarity's sake, here are the exact steps taken to produce this patch:
1. Update QEMU's libvirt-ci to the commit
https://gitlab.com/libvirt/libvirt-ci/-/commit/43927ff508e8ecb1ac2
On 5/25/22 12:45, Laurent Vivier wrote:
+DEF_HELPER_2(raise_exception, noreturn, env, i32)
...
-static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
+G_NORETURN static void
+raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
CPUState *cs = env_cpu(env
On 5/25/22 02:05, Igor Mammedov wrote:
> On Tue, 24 May 2022 14:48:29 -0500
> "Moger, Babu" wrote:
>
>> On 5/24/22 10:19, Igor Mammedov wrote:
>>> On Tue, 24 May 2022 11:10:18 -0400
>>> Igor Mammedov wrote:
>>>
>>> CCing AMD folks as that might be of interest to them
>> I am trying to recreat
On 5/24/22 18:23, Alejandro Jimenez wrote:
> On 5/24/2022 3:48 PM, Moger, Babu wrote:
>>
>> On 5/24/22 10:19, Igor Mammedov wrote:
>>> On Tue, 24 May 2022 11:10:18 -0400
>>> Igor Mammedov wrote:
>>>
>>> CCing AMD folks as that might be of interest to them
>>
>> I am trying to recreate the bug on
From: Vitaly Kuznetsov
rSTify docs/hyperv.txt and link it from docs/system/target-i386.rst.
Signed-off-by: Vitaly Kuznetsov
Message-Id: <20220525115949.1294004-7-vkuzn...@redhat.com>
Signed-off-by: Paolo Bonzini
---
docs/hyperv.txt | 303
docs/
From: Vitaly Kuznetsov
Hyper-V specification allows to pass parameters for certain hypercalls
using XMM registers ("XMM Fast Hypercall Input"). When the feature is
in use, it allows for faster hypercalls processing as KVM can avoid
reading guest's memory.
KVM supports the feature since v5.14.
R
From: Vitaly Kuznetsov
Previously, HV_CPUID_NESTED_FEATURES.EAX CPUID leaf was handled differently
as it was only used to encode the supported eVMCS version range. In fact,
there are also feature (e.g. Enlightened MSR-Bitmap) bits there. In
preparation to adding these features, move HV_CPUID_NEST
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Also mark raise_exception_ra and raise_exception, lest we
generate a warning about helper_raise_exception returning.
Signed-off-by: Richard Henderson
---
target/m68k/helper.h| 2 +-
target/m68k/op_helper.c | 5 +++--
2 files changed, 4
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Unlike i386, m68k get_thread_area has no arguments.
Signed-off-by: Richard Henderson
---
linux-user/strace.list | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index 278596acd1..72e17b
From: Lev Kujawski
Prior to this patch, the pre-GRUB Solaris x86 bootloader would fail to
load on QEMU with the following screen output:
SunOS Secondary Boot version 3.00
prom_panic: Could not mount filesystem.
Entering boot debugger:
[136419]: _
This occurs because the bootloader issues an AT
From: "Maciej S. Szmigiero"
Since KVM commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when
guest MPX disabled")
it is not possible to disable MPX on a "-cpu host" just by adding "-mpx"
there if the host CPU does indeed support MPX.
QEMU will fail to set MSR_IA32_VMX_TRUE_{EXIT,EN
From: Vitaly Kuznetsov
The newly introduced enlightenment allow L0 (KVM) and L1 (Hyper-V)
hypervisors to collaborate to avoid unnecessary updates to L2
MSR-Bitmap upon vmexits.
Signed-off-by: Vitaly Kuznetsov
Message-Id: <20220525115949.1294004-3-vkuzn...@redhat.com>
Signed-off-by: Paolo Bonzin
From: BALATON Zoltan
Several functions have a local variable that is just a copy of one of
the function parameters. This is unneeded complication so just get rid
of these.
Signed-off-by: BALATON Zoltan
Reviewed-by: Peter Maydell
Message-Id:
Signed-off-by: Paolo Bonzini
---
hw/audio/ac97.c
From: Vitaly Kuznetsov
Hyper-V TLFS allows for L0 and L1 hypervisors to collaborate on L2's
TLB flush hypercalls handling. With the correct setup, L2's TLB flush
hypercalls can be handled by L0 directly, without the need to exit to
L1.
Signed-off-by: Vitaly Kuznetsov
Message-Id: <20220525115949
From: Viktor Prutyanov
Add ELF header checking to prevent processing input file which is not
QEMU x86_64 guest memory dump or even not ELF.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1013
Signed-off-by: Viktor Prutyanov
Reviewed-by: Richard Henderson
Message-Id: <20220520084339.1
Just setting the max threads to 0 is enough to stop all workers.
Message-Id: <20220514065012.1149539-4-pbonz...@redhat.com>
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Nicolas Saenz Julienne
Signed-off-by: Paolo Bonzini
---
util/thread-pool.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletio
From: Vitaly Kuznetsov
KVM kind of supported "extended GVA ranges" (up to 4095 additional GFNs
per hypercall) since the implementation of Hyper-V PV TLB flush feature
(Linux-4.18) as regardless of the request, full TLB flush was always
performed. "Extended GVA ranges for TLB flush hypercalls" fea
From: BALATON Zoltan
Signed-off-by: BALATON Zoltan
Reviewed-by: Víctor Colombo
Message-Id:
<62862a057e9c9ec0bb45248b2b9a3a1babb346a6.1650706617.git.bala...@eik.bme.hu>
Signed-off-by: Paolo Bonzini
---
hw/audio/ac97.c | 727
1 file changed, 357
Since commit f9fc8932b1 ("thread-posix: remove the posix semaphore
support", 2022-04-06) QemuSemaphore has its own mutex and condition
variable; this adds unnecessary overhead on I/O with small block sizes.
Check the QTAILQ directly instead of adding the indirection of a
semaphore's count. Using
The completion bottom half was scheduled within the pool->lock
critical section. That actually results in worse performance,
because the worker thread can run its own small critical section
and go to sleep before the bottom half starts running.
Note that this simple change does not produce an imp
From: Yang Weijiang
Live migration can happen when Arch LBR LBREn bit is cleared,
e.g., when migration happens after guest entered SMM mode.
In this case, we still need to migrate Arch LBR MSRs.
Signed-off-by: Yang Weijiang
Message-Id: <20220517155024.33270-1-weijiang.y...@intel.com>
Signed-off
From: BALATON Zoltan
The warm_reset() and cold_reset() functions are not implemented and do
nothing so no point in calling them or keep around as dead code.
Therefore remove them for now.
Signed-off-by: BALATON Zoltan
Reviewed-by: Víctor Colombo
Message-Id:
Signed-off-by: Paolo Bonzini
---
From: Jaroslav Jindrak
Prior to the introduction of the prealloc-threads property, the amount
of threads used to preallocate memory was derived from the value of
smp-cpus passed to qemu, the amount of physical cpus of the host
and a hardcoded maximum value. When the prealloc-threads property
was
The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:
Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into
staging (2022-05-20 08:04:30 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you t
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Errors are not all negative numbers, but only the top 4k.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/strace.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/strace
On 25/05/2022 12:45, Peter Maydell wrote:
On Wed, 25 May 2022 at 10:51, Damien Hedde wrote:
On 5/24/22 19:44, Mark Cave-Ayland wrote:
Sorry for coming late into this series, however one of the things I've
been thinking about a lot recently is that with the advent of QOM and
qdev, is there rea
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
These are raised by guest instructions, and should not
fall through into the default abort case.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/m68k/cpu_loop.c
On 5/25/22 09:19, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Fix when building HVF on macOS Aarch64:
target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did
you mean 'ARMCPUInfo'?
const ARMCPRegInfo *ri;
^~~~
On 5/25/22 05:49, Stefan Hajnoczi wrote:
The following changes since commit 0cac736e73723850a99e5142e35d14d8f8efb232:
Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into
staging (2022-05-24 15:55:12 -0700)
are available in the Git repository at:
Le 30/04/2022 à 19:53, Richard Henderson a écrit :
Add parenthesis around & vs &&.
Remove assignment to sr in function call argument -- note that
sr is unused after the call, so the assignment was never needed,
only the result of the & expression.
Suggested-by: Philippe Mathieu-Daudé
Signed-of
ll request linux-user 20220525
s390x fixes
CPUArchState cleanup
elfload cleanup
fix for uclibc-ng and by musl
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
Fabrice Fontaine (1):
The correct A20 masking is done if paging is enabled (protected mode) but it
seems to have been forgotten in real mode. For example from the AMD64 APM Vol. 2
section 1.2.4:
> If the sum of the segment base and effective address carries over into bit 20,
> that bit can be optionally truncated to mi
On 22/05/2022 22:24, Bernhard Beschow wrote:
Just like the real hardware, create the PIIX4 ACPI controller as part of
the PIIX4 southbridge. This also mirrors how the IDE and USB functions
are already created.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c| 14 +++
cpregs.h was previously split out from cpu.h into a separate file, but
I think this was forgotten to be included in hvf.c. I got a build failure
when trying to build on Apple Silicon:
[...]
../target/arm/hvf/hvf.c:591:33: error: use of undeclared identifier
'ARM_CP_NO_RAW'
assert(!(r
From: Philippe Mathieu-Daudé
Fix when building HVF on macOS Aarch64:
target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you
mean 'ARMCPUInfo'?
const ARMCPRegInfo *ri;
^~~~
ARMCPUInfo
target/arm/cpu-qom.h:38:3: note: 'A
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
.gitlab-ci.d/buildtest-template.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitlab-ci.d/buildtest-template.yml
b/.gitlab-ci.d/buildtest-template.yml
index dc6d67aacf..b381345dbc 100644
--- a/.gitlab-ci.d/buildtest-temp
Instead of generating each table entry inline, move the individual PCI host
bridge
table entry generation to a separate build_pci_host_range() function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
---
hw/acpi/viot.c | 48 +
Signed-off-by: Mark Cave-Ayland
Acked-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
This is in preparation for separating out the VIOT ACPI table build from the
PCI host bridge numeration.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
---
hw/acpi/viot.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/acpi
This ensures that the VIOT ACPI table output is always stable for a given PCI
topology by ensuring that entries are ordered according to min_bus.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
---
hw/acpi/viot.c | 17 +
1 file changed
Differences between disassembled ASL files for VIOT:
+++ /tmp/asl-V69GM1.dsl 2022-05-18 10:22:27.239796759 +0100
@@ -36,11 +36,11 @@
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
-[044h 0068 4] Endpoint start : 3000
+[0
Perform the generation of the VIOT ACPI table in 2 separate passes: the first
pass
enumerates all of the PCI host bridges and adds the min_bus and max_bus
information
to an array.
Once this is done the VIOT table header is generated using the size of the array
to calculate the node count, which
I was working away at some improvements for PS2 devices when I noticed that one
small change to the instantiation of a PS2 mouse device caused a regression in
tests/qtest/bios-tables-test, specifically the /x86_64/acpi/q35/viot subtest.
Closer examination of the failed test output showed the probl
On Tue, May 24, 2022 at 04:40:45PM +0100, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> include/hw/virtio/vhost.h | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Stefan Hajnoczi
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On Tue, May 24, 2022 at 04:40:44PM +0100, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> include/hw/virtio/vhost.h | 11 +++
> 1 file changed, 11 insertions(+)
Reviewed-by: Stefan Hajnoczi
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Richard Henderson writes:
> On 5/25/22 05:29, Anton Johansson wrote:
>> For clarity's sake, here are the exact steps taken to produce this patch:
>> 1. Update QEMU's libvirt-ci to the commit
>> https://gitlab.com/libvirt/libvirt-ci/-/commit/43927ff508e8ecb1ac225dabbc95b37c890db917
>>
On Tue, May 24, 2022 at 04:40:42PM +0100, Alex Bennée wrote:
> We were not building the vhost-user-blk server due to 32 bit
> compilation problems. The problem was due to format string types so
> fix that and then enable the build. Tweak the rule to follow the same
> rules as other vhost-user daemo
From: Howard Chiu
Add EEPROM and LM75 temperature sensor according to hardware schematic
Signed-off-by: Howard Chiu
Reviewed-by: Cédric Le Goater
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.
Konstantin Kostiuk writes:
> v1 -> v2: Fix spelling in the commit message
> v1: https://patchew.org/QEMU/2022052418.922031-1-kkost...@redhat.com/
>
> Konstantin Kostiuk (1):
> tests: Bump Fedora image version for cross-compilation
Queued to testing/next, thanks.
--
Alex Bennée
On 5/25/22 02:29, Konstantin Kostiuk wrote:
The following changes since commit 0cac736e73723850a99e5142e35d14d8f8efb232:
Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into
staging (2022-05-24 15:55:12 -0700)
are available in the Git repository
From: Jamin Lin
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Message-Id: <20220525053444.27228-4-jamin_...@aspeedtech.com>
Signed-off-by: Cédric Le Goater
---
include/hw/gpio/aspeed_gpio.h | 14 +++
hw/gpio/aspeed_gpio.c
From: Jamin Lin
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Message-Id: <20220525053444.27228-2-jamin_...@aspeedtech.com>
Signed-off-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 54 +++
h
On Tue, May 24, 2022 at 04:40:56PM +0100, Alex Bennée wrote:
> We don't have a virtio-gpio implementation in QEMU and only
> support a vhost-user backend. The QEMU side of the code is minimal so
> it should be enough to instantiate the device and pass some vhost-user
> messages over the control soc
On Tue, May 24, 2022 at 04:40:41PM +0100, Alex Bennée wrote:
> Hi,
>
> This series ostensibly adds virtio-user-gpio stubs to the build for
> use with an external vhost-user daemon. We've been testing it with our
> rust daemons from:
>
> https://github.com/rust-vmm/vhost-device
>
> Getting the
From: Peter Delevoryas
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030
from UART6 to UART13. The addresses and interrupt numbers for these two
later chips are identical.
On Tue, May 24, 2022 at 04:40:43PM +0100, Alex Bennée wrote:
> When debugging a new vhost user you may be surprised to see
> VHOST_USER_F_PROTOCOL getting squashed in the maze of
> backend_features, acked_features and guest_features. Expand the
> description here to help the next poor soul trying t
On Wed, Mar 16, 2022 at 10:54:55AM +0100, Damien Hedde wrote:
> +def raw_load(file: TextIO) -> List[QMPMessage]:
> +"""parse a raw qmp command file.
> +
> +JSON formatted commands can expand on several lines but must
> +be separated by an end-of-line (two commands can not share the
>
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