On 2022/06/19 9:41, Imran Yusuff wrote:
This applies only on macOS using cocoa UI library.
In zoom-to-fit fullscreen mode, upon graphics mode switch,
the viewport size is wrong, and the usual consequence
is only a part of the screen is visible. One have to exit
and reenter fullscreen mode to fix
Hello all,
Suppose I am wanting to implement and test for the TCG. Is there any set of
interactive binaries or other things that I could use to work with it?
Could I open a shell to it? Perhaps feed it specific byte sequences for
tests to ensure correct operation? Are there a canonical set of uni
In machvirt_init we create a cpu but do not fully initialize it.
Thus the propagation of V7VE to LPAE has not been done, and we
compute the wrong value for some v7 cpus, e.g. cortex-a15.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1078
Signed-off-by: Richard Henderson
---
target/arm/
Nicely summarized by the reporter, but I thought it would be
nicer to pull all of the logic into arm_pamax, rather than
leave it separated.
r~
Richard Henderson (2):
target/arm: Extend arm_pamax to more than aarch64
target/arm: Check V7VE as well as LPAE in arm_pamax
hw/arm/virt.c| 10
Move the code from hw/arm/virt.c that is supposed
to handle v7 into the one function.
Signed-off-by: Richard Henderson
---
hw/arm/virt.c| 10 +-
target/arm/ptw.c | 24
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/vir
Add a helper to set a property from a set of strings
to reduce the following code:
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
(char **)&clint_compat, ARRAY_SIZE(clint_compa
I've been doing a bit of looking at riscv and dt creation, and
was thinking the following two helper functions would be useful
so implemented qemu_fdt_setprop_reg64_map() and qemu_fdt_setprop_strings()
and then applied them to the hw/riscv/sifive_u.c ma
Add a macro qemu_fdt_setprop_reg64_map() to set the given
node's reg property directly from the memory map entry
to avoid open coding of the following:
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_DEV_OTP].base,
0x0, memmap[SIFIVE_U_DEV_OTP].size);
Signed-
Use the qemu_fdt_setprop_reg64_map() to replace the code
that sets the property manually.
Signed-off-by: Ben Dooks
--
v2:
- changed to qemu_fdt_setprop_reg64_map() from previous
---
hw/riscv/sifive_u.c | 41 +++--
1 file changed, 11 insertions(+), 30 deletions
Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
the code.
Signed-off-by: Ben Dooks
---
hw/riscv/sifive_u.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 89d7aa2a52..16b18d90bd 100644
--- a/hw/ri
On Fri, Apr 22, 2022 at 10:19:34AM +0800, Bin Meng wrote:
> On Mon, Apr 18, 2022 at 5:13 AM Ben Dooks wrote:
> >
> > Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
> > the code.
> >
> > Signed-off-by; Ben Dooks
>
> ; should be replaced to :
>
> Not sure how you did that, but you ca
On 6/17/22 11:52, Frederic Barrat wrote:
The 'resume_as_sreset' attribute of a cpu is set when a thread is
entering a stop state on ppc books. It causes the thread to be
re-routed to vector 0x100 when woken up by an exception. So it must be
cleared on reset or a thread might be re-routed unexpect
It's unneeded. No other PCIE_BUS implements this interface.
Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/p
The function is working today by getting all the child objects of the
chip, interacting with each of them to check whether the child is a PHB,
and then doing what needs to be done.
We have all the chip PHBs in the phbs[] array so interacting with all
child objects is unneeded. Open code pnv_ics_ge
We already have access to the 'dev' object.
Reviewed-by: Frederic Barrat
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 4 ++--
hw/pci-host/pnv_phb4.c | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
i
It's unneeded. No other PCIE_BUS implements this interface.
Fixes: 9ae1329ee2fe ("ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge")
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/p
pnv_ics_resend() is scrolling through all the child objects of the chip
to search for the PHBs. It's faster and simpler to just use the phbs[]
array.
pnv_ics_resend_child() was folded into pnv_ics_resend() since it's too
simple to justify its own function.
Signed-off-by: Daniel Henrique Barboza
It is not advisable to execute an object_dynamic_cast() to poke into
bus->qbus.parent and follow it up with a C cast into the PnvPHB type we
think we got.
A better way is to access the PnvPHB object via a QOM macro accessing
the existing parent links of the DeviceState. For a given
pnv-phb3/4-root
Creating a root port is something related to the PHB, not the PEC. It
also makes the logic more in line with what pnv-phb3 does.
Reviewed-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 4
hw/pci-host/pnv_phb4_pec.c
At this moment we leave the pnv-phb3(4)-root-port unattached in QOM:
/unattached (container)
(...)
/device[2] (pnv-phb3-root-port)
/bus master container[0] (memory-region)
/bus master[0] (memory-region)
/pci_bridge_io[0] (memory-region)
/pci_bridge_io[1] (memory-regio
It's inneficient to scroll all child objects when we have all PHBs
available in chip8->phbs[].
pnv_chip_power8_pic_print_info_child() ended up folded into
pic_print_info() for simplicity.
Reviewed-by: Frederic Barrat
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 22
This second version contains changes and fixes suggested by Frederic and Cedric
in the v1 review.
As I've mentioned in the v1, I cropped patches that are more related with
the user created device logic. Patches 8-11 will be resend later in another
series.
I ended up sliding in a couple of new pat
On 6/17/22 08:07, Alexey Kardashevskiy wrote:
The new PAPR 2.12 defines a watchdog facility managed via the new
H_WATCHDOG hypercall.
This adds H_WATCHDOG support which a proposed driver for pseries uses:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=303120
This was tested by r
On 6/17/22 08:07, Alexey Kardashevskiy wrote:
It keeps repeating, move it to the header. This uses __builtin_ctzl() to
allow using the macros in #define.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Cédric Le Goater
Thanks Alexey,
C.
---
include/hw/pci-host/pnv_phb3_regs.h | 16 --
Peter Delevoryas, le mer. 15 juin 2022 18:05:26 -0700, a ecrit:
> With this change, you can now request the out-of-band MAC address from
> slirp in fby35-bmc:
>
> wget
> https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
> qemu-system-arm -machine fby35-b
Peter Delevoryas, le mer. 15 juin 2022 18:05:25 -0700, a ecrit:
> This lets you set the manufacturer's ID for a slirp netdev, which can be
> queried from the guest through the Get Version ID NC-SI command. For
> example, by setting the manufacturer's ID to 0x8119:
>
> wget
> https://github.co
Hello,
Peter Delevoryas, le mer. 15 juin 2022 18:05:24 -0700, a ecrit:
> I think we probably need a new Slirp release
> (4.8.0) and a switch statement here instead, right?
>
> So that we can preserve the behavior for 4.7.0?
Yes, that's the idea.
Samuel
Signed-off-by: Joel Stanley
---
hw/misc/aspeed_hace.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 4b5997e18fad..731234b78c4c 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -340,12 +340,12 @@ static
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