[PULL 18/60] include/exec: Define errno values in gdbstub.h

Define constants for the errno values defined by the gdb remote fileio protocol. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/gdbstub.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/include/exec/gdbstub.h

[PULL 06/60] semihosting: Add target_strlen for softmmu-uaccess.h

Mirror the interface of the user-only function of the same name. Use probe_access_flags for the common case of ram, and cpu_memory_rw_debug for the uncommon case of mmio. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use probe_access_flags (pmm) ---

[PATCH v4 41/45] linux-user: Rename sve prctls

Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 linux-user/syscall.c | 12 ++-- 2 files changed, 10 insertions(+), 10

[PULL 09/60] semihosting: Inline set_swi_errno into common_semi_cb

Do not store 'err' into errno only to read it back immediately. Use 'ret' for the return value, not 'reg0'. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git

[PULL 10/60] semihosting: Adjust error checking in common_semi_cb

The err parameter is non-zero if and only if an error occured. Use this instead of ret == -1 for determining if we need to update the saved errno. This fixes the errno setting of SYS_ISTTY, which returns 0 on error, not -1. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson ---

[PULL 01/60] semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.h

We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- .../{exec/softmmu-semi.h => semihosting/softmmu-uaccess.h}

[PULL 04/60] semihosting: Move softmmu-uaccess.h functions out of line

Rather that static (and not even inline) functions within a header, move the functions to semihosting/uaccess.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/semihosting/softmmu-uaccess.h | 42 +++--- semihosting/uaccess.c | 51

[PULL 08/12] libvhost-user: Fix VHOST_USER_ADD_MEM_REG reply

From: Kevin Wolf With REPLY_NEEDED, libvhost-user sends both the acutal result and an additional ACK reply for VHOST_USER_ADD_MEM_REG. This is incorrect, the spec mandates that it behave the same with and without REPLY_NEEDED because it always sends a reply. Fixes:

[PULL 05/60] accel/stubs: Add tcg stub for probe_access_flags

Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- accel/stubs/tcg-stub.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index ea4a0dd2fb..6ce8a34228 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -21,6

[PATCH v4 39/45] linux-user/aarch64: Move sve record checks into restore

Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51

[PULL 02/60] semihosting: Return failure from softmmu-uaccess.h functions

We were reporting unconditional success for these functions; pass on any failure from cpu_memory_rw_debug. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/semihosting/softmmu-uaccess.h | 91 --- 1 file changed, 39 insertions(+), 52 deletions(-)

[PULL 12/12] include/hw/virtio: document vhost_ack_features

From: Alex Bennée Signed-off-by: Alex Bennée Message-Id: <20220524154056.2896913-5-alex.ben...@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Stefan Hajnoczi --- include/hw/virtio/vhost.h | 10 ++ 1 file changed, 10 insertions(+) diff

[PULL 03/60] semihosting: Improve condition for config.c and console.c

While CONFIG_SEMIHOSTING is currently only set for softmmu, this will not continue to be true. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- semihosting/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/semihosting/meson.build

[PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded

Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6

[PULL 11/12] include/hw/virtio: document vhost_get_features

From: Alex Bennée Signed-off-by: Alex Bennée Message-Id: <20220524154056.2896913-4-alex.ben...@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Stefan Hajnoczi --- include/hw/virtio/vhost.h | 11 +++ 1 file changed, 11 insertions(+) diff

[PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context

Make sure to zero the currently reserved fields. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 ---

[PULL 05/12] virtio-iommu: Fix migration regression

From: Zhenzhong Duan We also need to switch to the right address space on dest side after loading the device status. DMA to wrong address space is destructive. Fixes: 3facd774962fd ("virtio-iommu: Add bypass mode support to assigned device") Suggested-by: Eric Auger Signed-off-by: Zhenzhong

[PULL 10/12] contrib/vhost-user-blk: fix 32 bit build and enable

From: Alex Bennée We were not building the vhost-user-blk server due to 32 bit compilation problems. The problem was due to format string types so fix that and then enable the build. Tweak the rule to follow the same rules as other vhost-user daemons. Signed-off-by: Alex Bennée Message-Id:

[PULL 09/12] MAINTAINERS: Collect memory device files in "Memory devices"

From: David Hildenbrand Xiao Guangrong doesn't have enough time to actively review or contribute to our NVDIMM implementation. Let's dissolve the "NVDIMM" section, moving relevant ACPI parts to "ACPI/SMBIOS" and moving memory device stuff into a new "Memory devices" section. Make that new

[PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls

Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 + 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b273f6299..4af6996d57 100644 --- a/linux-user/aarch64/cpu_loop.c +++

[PULL 00/12] virtio: fixes

The following changes since commit 097ccbbbaf2681df1e65542e5b7d2b2d0c66e2bc: Merge tag 'qemu-sparc-20220626' of https://github.com/mcayland/qemu into staging (2022-06-27 05:21:05 +0530) are available in the Git repository at: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git

[PULL 07/12] libvhost-user: Fix VHOST_USER_GET_MAX_MEM_SLOTS reply

From: Kevin Wolf With REPLY_NEEDED, libvhost-user sends both the acutal result and an additional ACK reply for VHOST_USER_GET_MAX_MEM_SLOTS. This is incorrect, the spec mandates that it behave the same with and without REPLY_NEEDED because it always sends a reply. Fixes:

[PULL 01/12] virtio-iommu: Fix the partial copy of probe request

From: Zhenzhong Duan The structure of probe request doesn't include the tail, this leads to a few field missed to be copied. Currently this isn't an issue as those missed field belong to reserved field, just in case reserved field will be used in the future. Changed 4th parameter of

[PATCH v4 32/45] target/arm: Enable SME for -cpu max

Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 target/arm/cpu64.c|

[PATCH v4 43/45] target/arm: Only set ZEN in reset if SVE present

There's no reason to set CPACR_EL1.ZEN if SVE disabled. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4a35890853..20cb622083 100644 --- a/target/arm/cpu.c +++

[PATCH v7 4/4] target/riscv: Force disable extensions if priv spec version does not match

We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to

[PATCH v4 26/45] target/arm: Implement FMOPA, FMOPS (widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c| 68 ++ target/arm/translate-sme.c | 1 + 4 files changed, 72 insertions(+) diff --git a/target/arm/helper-sme.h

[PATCH v7 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel --- target/riscv/cpu.h| 5 + target/riscv/cpu_helper.c

[PULL 04/12] vhost: setup error eventfd and dump errors

From: Konstantin Khlebnikov Vhost has error notifications, let's log them like other errors. For each virt-queue setup eventfd for vring error notifications. Signed-off-by: Konstantin Khlebnikov [vsementsov: rename patch, change commit message and dump error like other errors in

[PATCH v7 0/4] QEMU RISC-V nested virtualization fixes

This series does fixes and improvements to have nested virtualization on QEMU RISC-V. These patches can also be found in riscv_nested_fixes_v7 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required

[PATCH v4 18/45] target/arm: Implement SME ZERO

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix ZA[] comment in helper_sme_zero. --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 4 target/arm/sme_helper.c| 25 + target/arm/translate-sme.c | 13 + 4

[PATCH v4 31/45] target/arm: Reset streaming sve state on exception boundaries

We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c

[PATCH v4 44/45] target/arm: Enable SME for user-only

Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 20cb622083..87d836fb2f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c

[PATCH v4 21/45] target/arm: Export unpredicated ld/st from translate-sve.c

Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 -- 2

[PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL

These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 48 +++ linux-user/syscall.c | 16 +++ 2 files changed,

[PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS

Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++

[PATCH v4 28/45] target/arm: Implement PSEL

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 + target/arm/translate-sve.c | 57

[PATCH v4 20/45] target/arm: Implement SME LD1, ST1

We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 82 + target/arm/sme.decode | 9 +

[PATCH v4 30/45] target/arm: Implement SCLAMP, UCLAMP

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 18 +++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c |

[PATCH v4 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add streaming_{vec,pred}_reg_size. --- target/arm/translate-a64.h | 12 target/arm/sve.decode

[PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling

Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 162 +--- 1 file changed, 151 insertions(+), 11

[PATCH v4 25/45] target/arm: Implement BFMOPA, BFMOPS

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c| 52 ++ target/arm/translate-sme.c | 30 ++ 4 files changed, 86 insertions(+) diff --git

[PATCH v4 29/45] target/arm: Implement REVD

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c| 16

[PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records

In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 - 1 file changed, 4 insertions(+), 1

[PATCH v4 22/45] target/arm: Implement SME LDR, STR

We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++ target/arm/translate-sme.c | 24 2 files changed, 31

[PATCH v4 14/45] target/arm: Mark LD1RO as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git

[PATCH v4 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return

Fold the return value setting into the goto, so each point of failure need not do both. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c

[PATCH v4 24/45] target/arm: Implement FMOPA, FMOPS (non-widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 5 +++ target/arm/sme.decode | 9 ++ target/arm/sme_helper.c| 63 ++ target/arm/translate-sme.c | 32 +++ 4 files changed, 109 insertions(+) diff --git

[PATCH v4 19/45] target/arm: Implement SME MOVA

We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 12 target/arm/helper-sve.h| 2 + target/arm/translate-a64.h | 8 +++

[PATCH v4 12/45] target/arm: Mark gather prefetch as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/sve.decode

[PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA

Signed-off-by: Richard Henderson --- v4: Drop restrict. --- target/arm/helper-sme.h| 5 +++ target/arm/sme.decode | 11 + target/arm/sme_helper.c| 90 ++ target/arm/translate-sme.c | 31 + 4 files changed, 137 insertions(+) diff

[PATCH v4 11/45] target/arm: Mark gather/scatter load/store as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 9 - target/arm/translate-sve.c | 6 ++ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git

[PATCH v4 27/45] target/arm: Implement SME integer outer product

This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 16 target/arm/sme.decode | 10 + target/arm/sme_helper.c| 82 ++

[PATCH v4 16/45] target/arm: Handle SME in sve_access_check

The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 22 -- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c

[PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 9 ++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git

[PATCH v4 10/45] target/arm: Mark string/histo/crypto as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 35 ++- 2 files changed, 18 insertions(+), 18

[PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 18 ++ 2 files changed, 10 insertions(+), 10 deletions(-)

[PATCH v4 04/45] target/arm: Mark ADR as non-streaming

Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Signed-off-by: Richard Henderson --- target/arm/translate.h | 7 +++

[PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 15 +++ 2 files changed, 11 insertions(+), 7 deletions(-) diff

[PATCH v4 15/45] target/arm: Add SME enablement checks

These functions will be used to verify that the cpu is in the correct state for a given instruction. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 21 + target/arm/translate-a64.c | 34 ++ 2 files changed, 55 insertions(+)

[PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 22 -- 2 files changed, 12 insertions(+), 13

[PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active

This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought

[PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state

Dump SVCR, plus use the correct access check for Streaming Mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bb44ad45aa..4a35890853 100644 ---

[PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 12 ++-- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git

[PATCH v4 02/45] target/arm: Add infrastructure for disas_sme

This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 target/arm/translate-a64.c |

[PATCH v4 00/45] target/arm: Scalable Matrix Extension

Changes for v4: * Rebase on mainline (20 patches upstreamed). * Adjust sve_access_check when PSTATE.SM set. * Adjust sve insns to indicate not valid while streaming. * Other misc adjustments per review. r~ Richard Henderson (45): target/arm: Handle SME in aarch64_cpu_dump_state

Re: [PATCH 2/2] tap: initialize TAPState->enabled according to the actual state of queue

在 2022/6/14 19:21, Andrey Ryabinin 写道: Currently TAPState->enabled initialized as true. If fd was passed to qemu in a disabled state it will cause an assert at the attempt to detach queue in virtio_net_set_queues(): virtio_net_set_queues() : r = peer_detach() -> tap_disable():

Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Tue, Jun 28, 2022 at 4:47 AM Alistair Francis wrote: > > On Sat, Jun 11, 2022 at 6:07 PM Anup Patel wrote: > > > > We should disable extensions in riscv_cpu_realize() if minimum required > > priv spec version is not satisfied. This also ensures that machines with > > priv spec v1.11 (or

Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Tue, Jun 28, 2022 at 4:48 AM Alistair Francis wrote: > > On Thu, Jun 9, 2022 at 1:31 PM Anup Patel wrote: > > > > We should write transformed instruction encoding of the trapped > > instruction in [m|h]tinst CSR at time of taking trap as defined > > by the RISC-V privileged specification

[PATCH] include: set vm hva aligned with huge pagesize on loongarch

On loongarch system, page size is 16K rather than 4K like general platforms, and huge pagesize is 32M. This patch sets hva for vm aligned with huge pagesize on loongarch host system. Signed-off-by: Mao Bibo --- include/qemu/osdep.h | 3 +++ 1 file changed, 3 insertions(+) diff --git

Re: [PATCH 2/4] libvduse: Replace strcpy() with strncpy()

On Tue, Jun 28, 2022 at 8:26 AM Richard Henderson wrote: > > On 6/27/22 14:32, Xie Yongji wrote: > > -strcpy(dev_config->name, name); > > +strncpy(dev_config->name, name, VDUSE_NAME_MAX); > > +dev_config->name[VDUSE_NAME_MAX - 1] = '\0'; > > g_strlcpy > Now we don't have a dependency

Re: [PATCH qemu v2 1/2] ppc: Define SETFIELD for the ppc target

On 6/28/22 04:04, Daniel Henrique Barboza wrote: On 6/27/22 01:54, Alexey Kardashevskiy wrote: On 6/25/22 06:12, Daniel Henrique Barboza wrote: Alexey, The newer version of this patch is having trouble with Gitlab runners, as you can read in my feedback there. I've tested this one

Re: [PATCH v4 1/2] hw: canokey: Remove HS support as not compliant to the spec

On Sat, Jun 25, 2022 at 10:21:37PM +0800, MkfsSion wrote: > Canokey core currently using 16 bytes as maximum packet size for > control endpoint, but to run the device in high-speed a 64 bytes > maximum packet size is required according to USB 2.0 specification. > Since we don't acutally need to

Re: [PATCH v4] docs/system/devices/canokey: Document limitations on usb-ehci

On Sat, Jun 25, 2022 at 10:26:51PM +0800, MkfsSion wrote: > Suggested-by: Hongren (Zenithal) Zheng > Signed-off-by: YuanYang Meng > --- > v4: > Adopt Zenithal's suggestion of repharsing the limitation > > docs/system/devices/canokey.rst | 5 + > 1 file changed, 5 insertions(+) > >

[PATCH v1 2/2] migration/multifd: Warn user when zerocopy not working

Some errors, like the lack of Scatter-Gather support by the network interface(NETIF_F_SG) may cause sendmsg(...,MSG_ZEROCOPY) to fail on using zero-copy, which causes it to fall back to the default copying mechanism. After each full dirty-bitmap scan there should be a zero-copy flush happening,

[PATCH v1 0/2] Zero copy improvements (QIOChannel + multifd)

The first patch avoid spuriously returning 1 [*] when zero-copy flush is attempted before any buffer was sent using MSG_ZEROCOPY. [*] zero-copy not being used, even though it's enabled and supported by kernel The second patch should be applied on top of Juan Quintela's patchset that reduces the

[PATCH v1 1/2] QIOChannelSocket: Fix zero-copy flush returning code 1 when nothing sent

If flush is called when no buffer was sent with MSG_ZEROCOPY, it currently returns 1. This return code should be used only when Linux fails to use MSG_ZEROCOPY on a lot of sendmsg(). Fix this by returning early from flush if no sendmsg(...,MSG_ZEROCOPY) was attempted. Fixes: 2bc58ffc2926

Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

> On Jun 28, 2022, at 3:33 AM, Klaus Jensen wrote: > > On Jun 27 13:17, Keith Busch wrote: >> On Thu, Jun 16, 2022 at 08:34:07PM +0800, Jinhao Fan wrote: >>> } >>> sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq); >>> >>> +if (n->dbbuf_enabled) { >>> +

Re: [PATCH 3/4] libvduse: Pass positive value to strerror()

On 6/27/22 14:32, Xie Yongji wrote: The value passed to strerror() should be positive. So let's fix it. Fixes: Coverity CID 1490226, 1490223 Signed-off-by: Xie Yongji --- subprojects/libvduse/libvduse.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard

Re: [PATCH 2/4] libvduse: Replace strcpy() with strncpy()

On 6/27/22 14:32, Xie Yongji wrote: -strcpy(dev_config->name, name); +strncpy(dev_config->name, name, VDUSE_NAME_MAX); +dev_config->name[VDUSE_NAME_MAX - 1] = '\0'; g_strlcpy r~

Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints

On Wed, Jun 8, 2022 at 4:20 PM Alistair Francis wrote: > > From: Alistair Francis > > We previously stored the device tree at a 16MB alignment from the end of > memory (or 3GB). This means we need at least 16MB of memory to be able > to do this. We don't actually need the FDT to be 16MB aligned,

Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Thu, Jun 9, 2022 at 1:31 PM Anup Patel wrote: > > We should write transformed instruction encoding of the trapped > instruction in [m|h]tinst CSR at time of taking trap as defined > by the RISC-V privileged specification v1.12. > > Signed-off-by: Anup Patel This fails to pass checkpatch

Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Sat, Jun 11, 2022 at 6:07 PM Anup Patel wrote: > > We should disable extensions in riscv_cpu_realize() if minimum required > priv spec version is not satisfied. This also ensures that machines with > priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter > extensions. > >

Re: [RFC v2] Adding block layer APIs resembling Linux ZoneBlockDevice ioctls.

On 6/25/22 00:49, Stefan Hajnoczi wrote: > On Fri, Jun 24, 2022 at 11:14:32AM +0800, Sam Li wrote: >> Hi Stefan, >> >> Stefan Hajnoczi 于2022年6月20日周一 15:55写道： >>> >>> On Mon, Jun 20, 2022 at 11:36:11AM +0800, Sam Li wrote: >>> >>> Hi Sam, >>> Is this version 2 of "[RFC v1] Add support for zoned

Re: [PATCH v4 48/53] semihosting: Use console_in_gf for SYS_READC

On 6/27/22 14:37, Alex Bennée wrote: Richard Henderson writes: Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 27 ++- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c

Re: [PULL 00/25] target-arm queue

097ccbbbaf2681df1e65542e5b7d2b2d0c66e2bc: Merge tag 'qemu-sparc-20220626' of https://github.com/mcayland/qemu into staging (2022-06-27 05:21:05 +0530) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220627 for you to fetch changes up

Re: [PATCH] target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem

On 6/27/22 19:16, Peter Maydell wrote: In commit 39a1fd25287f5d we fixed a bug in the handling of LPAE block descriptors where we weren't correctly zeroing out some RES0 bits. However this fix has a bug because the calculation of the mask is done at the wrong width: in descaddr &= ~(page_size

Re: [PATCH V8 24/39] pci: export export msix_is_pending

On Wed, Jun 15, 2022 at 07:52:11AM -0700, Steve Sistare wrote: > Export msix_is_pending for use by cpr. No functional change. > > Signed-off-by: Steve Sistare the subject repeats export twice. With that fixed: Acked-by: Michael S. Tsirkin > --- > hw/pci/msix.c | 2 +- >

[PATCH 13/14] aspeed: Add intel-me on i2c6 instead of BMC

Signed-off-by: Peter Delevoryas --- hw/arm/aspeed.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 88e9a47dc2..375d87e6c7 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1448,6 +1448,7 @@ static void oby35_cl_i2c_init(AspeedMachineState *bmc)

Re: [PATCH] microvm: turn off io reservations for pcie root ports

On Thu, Jun 09, 2022 at 09:28:38AM +0200, Gerd Hoffmann wrote: > On Wed, Jun 08, 2022 at 12:06:17PM -0400, Michael S. Tsirkin wrote: > > On Fri, Jun 03, 2022 at 10:59:20AM +0200, Gerd Hoffmann wrote: > > > The pcie host bridge has no io window on microvm, > > > so io reservations will not work. >

[PATCH 14/14] aspeed: Add I2C new register DMA slave mode support

Signed-off-by: Peter Delevoryas --- hw/i2c/aspeed_i2c.c | 133 include/hw/i2c/aspeed_i2c.h | 3 + 2 files changed, 124 insertions(+), 12 deletions(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 8a8514586f..fc8b6b62cf 100644 ---

[PATCH 12/14] hw/misc: Add intel-me

Signed-off-by: Peter Delevoryas --- hw/arm/aspeed.c | 1 + hw/misc/intel_me.c | 176 hw/misc/meson.build | 3 +- 3 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 hw/misc/intel_me.c diff --git a/hw/arm/aspeed.c

Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests

On Mon, Jun 27, 2022 at 12:58:55PM +0530, Ani Sinha wrote: > The README file is added describing the directory structure and the purpose > of every file it contains. It also describes how to add new tests, make > changes > to existing tests or bits config files or regenerate the bits software. >

Re: [PATCH qemu v2] spapr/ddw: Reset DMA when the last non-default window is removed

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 6/22/22 02:29, Alexey Kardashevskiy wrote: PAPR+/LoPAPR says: === The platform must restore the default DMA window for the PE on a call to the ibm,remove-pe-dma-window RTAS call when all of the following are true: a. The

Re: [PATCH 0/7] Remove CONFIG_INT128 conditional code from target/ppc/*

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 6/6/22 12:00, Matheus Ferst wrote: PPC-specific methods to handle 128-bits integers operations, like avr_qw_not and avr_qw_add, are currently only tested indirectly (through the behavior of the insns that use them) in

Re: [PATCH qemu] spapr/ddw: Implement 64bit query extension

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 6/23/22 04:31, Alexey Kardashevskiy wrote: PAPR 2.8 (2018) defines an extension to return 64bit value for the largest TCE block in "ibm,query-pe-dma-window". Recent Linux kernels support this already. This adds the extension

Re: [PATCH] target/ppc: Change FPSCR_* to follow POWER ISA numbering convention

On 6/22/22 16:32, Víctor Colombo wrote: FPSCR_* bit values in QEMU are in the 'inverted' order from what Power ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h). Now that PPC_BIT_NR macro was introduced to fix this situation for the MSR bits, we can use it for the FPSCR bits

Re: [PATCH v3 0/8] pnv-phb related cleanups

Queued in gitlab.com/danielhb/qemu/tree/ppc-next after fixing the "We're retrieving a PHB reference PHB just to access" in the commit msg of patch 03. Thanks, Daniel On 6/21/22 14:34, Daniel Henrique Barboza wrote: This version present changes in patch 03. We're now setting chassis and

Re: Slowness with multi-thread TCG?

Frederic Barrat writes: > [ Resending as it was meant for the qemu-ppc list ] > > Hello, > > I've been looking at why our qemu powernv model is so slow when > booting a compressed linux kernel, using multiple vcpus and > multi-thread tcg. With only one vcpu, the decompression time of the >

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