On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
fby35 machines have 1 BMC on a baseboard and 2-4 server boards with BIC's.
There are also CPLD's on each of the boards, one type of CPLD on the
baseboard and another type on each of the server boards. This commit adds an
implement
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
This introduces a really basic PECI controller that responses to
commands by always setting the response code to success and then raising
an interrupt to indicate the command is done. This helps avoid getting
hit with constant err
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
This adds the ISL69259, using all the same functionality as the existing
ISL69260 but overriding the IC_DEVICE_ID.
Signed-off-by: Peter Delevoryas
---
hw/sensor/isl_pmbus_vr.c | 28
1 file changed
On Thu, Jun 30, 2022 at 11:42 AM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v9 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC-V nested virtualization was test
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v9 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required hyperviso
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
It is good practice to keep the Reviewed/Tested/Acked tags sent on
the previous version of a patchset. I should have told you in v2.
For next time ! :)
Thanks,
C.
v3:
- hw/i2c/pmbus_device:
- Removed commit that resets the
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
From: Peter Delevoryas
The fby35 machine includes 4 server boards, each of which has a "bridge
interconnect" (BIC). This chip abstracts the pinout for the server board
into a single endpoint that the baseboard management controller (BMC)
can talk to using IPMB.
This commit adds a machine for tes
From: Peter Delevoryas
The Intel Management Engine is an IPMI endpoint that responds to various
IPMI commands. In this commit, I've added some very basic functionality that
will respond back with a respond code of zero (success), while also setting
an appropriate response NetFN (request NetFN + 1
From: Peter Delevoryas
Signed-off-by: Peter Delevoryas
---
hw/i2c/pmbus_device.c | 9 +
include/hw/i2c/pmbus_device.h | 7 +++
2 files changed, 16 insertions(+)
diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c
index 62885fa6a1..f89fea65f3 100644
--- a/hw/i2c/pmbus
From: Peter Delevoryas
fby35 machines have 1 BMC on a baseboard and 2-4 server boards with BIC's.
There are also CPLD's on each of the boards, one type of CPLD on the
baseboard and another type on each of the server boards. This commit adds an
implementation of some of the logic performed by the
From: Klaus Jensen
Allow slaves to master the bus by registering a bottom halve. If the bus
is busy, the bottom half is queued up. When a slave has succesfully
mastered the bus, the bottom half is scheduled.
Signed-off-by: Klaus Jensen
[ clg : - fixed typos in commit log ]
Message-Id: <20220601
From: Peter Delevoryas
This introduces a really basic PECI controller that responses to
commands by always setting the response code to success and then raising
an interrupt to indicate the command is done. This helps avoid getting
hit with constant errors if the driver continuously attempts to s
From: Peter Delevoryas
This adds the ISL69259, using all the same functionality as the existing
ISL69260 but overriding the IC_DEVICE_ID.
Signed-off-by: Peter Delevoryas
---
hw/sensor/isl_pmbus_vr.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/sensor/isl
From: Peter Delevoryas
This commit adds support for DMA RX in slave mode while using the new
register set in the AST2600 and AST1030. This patch also pretty much
assumes packet mode is enabled, I'm not sure if this will work in DMA
step mode.
This is particularly useful for testing IPMB exchange
From: Peter Delevoryas
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]
/* 0x1C : I2CM Master DMA Transfer Length Register */
I
From: Klaus Jensen
Add slave mode functionality for the Aspeed I2C controller in old
register mode. This is implemented by realizing an I2C slave device
owned by the I2C controller and attached to its own bus.
The I2C slave device only implements asynchronous sends on the bus, so
slaves not supp
From: Peter Delevoryas
This commit adds a passthrough for PMBUS_IC_DEVICE_ID to allow Renesas
voltage regulators to return the integrated circuit device ID if they
would like to.
The behavior is very device specific, so it hasn't been added to the
general PMBUS model. Additionally, if the device
From: Peter Delevoryas
v3:
- hw/i2c/pmbus_device:
- Removed commit that resets the out buf.
- Removed IC_DEVICE_ID
- Added commit to allow devices to move to an idle state that
avoids enqueuing excess data into the out buf.
- hw/sensor/isl_pmbus_vr:
- Added IC_DEVICE_ID commit just fo
From: Peter Delevoryas
Very minor, doesn't effect functionality, but this is supposed to be
R_I2CC_FUN_CTRL (new-mode, not old-mode).
Fixes: ba2cccd64e9 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas
---
hw/i2c/aspeed_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
From: Peter Delevoryas
aspeed_i2c_bus_is_master is checking if master mode is enabled in the I2C
bus controller's function-control register, not that slave mode is enabled
or something. The error here is that the guest is trying to trigger an I2C
master mode command while master mode is not enab
From: Klaus Jensen
Add an asynchronous version of i2c_send() that requires the slave to
explicitly acknowledge on the bus with i2c_ack().
The current master must use the new i2c_start_send_async() to indicate
that it wants to do an asynchronous transfer. This allows the i2c core
to check if the
Add property "ioeventfd" which is enabled by default. When this is
enabled, updates on the doorbell registers will cause KVM to signal
an event to the QEMU main loop to handle the doorbell updates.
Therefore, instead of letting the vcpu thread run both guest VM and
IO emulation, we now use the main
When EXECUTE sets ex_value to interrupt the constructed instruction,
we implicitly disable interrupts so that the value is not corrupted.
Exit to the main loop after execution, so that we re-evaluate any
pending interrupts.
Reported-by: Sven Schnelle
Signed-off-by: Richard Henderson
---
Hi Sven
at 4:13 AM, Klaus Jensen wrote:
> On Jun 27 18:48, Jinhao Fan wrote:
>> Add property "ioeventfd" which is enabled by default. When this is
>> enabled, updates on the doorbell registers will cause KVM to signal
>> an event to the QEMU main loop to handle the doorbell updates.
>> Therefore, instead
On 6/29/22 16:16, Sven Schnelle wrote:
Thanks, that was very helpful. I added debugging and it turned out
that the TB is left because of a pending irq. The code then calls
s390_cpu_exec_interrupt:
bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CP
> That looks correct since we don't need the ioevent is an optional
> optimization.
>
> I would just suggest making this easier to read. For example, in
> nvme_init_sq_ioeventfd(), instead of assigning within a conditional:
>
>if ((ret = event_notifier_init(&cq->notifier, 0))) {
>
> Do ea
> On Jun 29, 2022, at 11:28 AM, Peter Delevoryas wrote:
>
>
>
>> On Jun 29, 2022, at 11:05 AM, Titus Rwantare wrote:
>>
>> On Tue, 28 Jun 2022 at 20:36, Peter Delevoryas
>> wrote:
>>>
>>> When a pmbus device switches pages, it should clears its output buffer so
>>> that the next transacti
sqeq.off here is the offset to read within the disk image, so obviously
not 'nread' (the amount we just read), but as the author meant to write
its current value incremented by the amount we just read.
Normally recent versions of linux will not issue short reads,
but it can happen so we should fix
New integer array parameter, 'monitor' is for specifying the target
monitors where individual GTK windows are placed upon launching.
Monitor numbers in the array are associated with virtual consoles
in the order of [VC0, VC1, VC2 ... VCn].
Every GTK window containing each VC will be placed in the
Detaching any addtional guest displays in case multiple displays are
assigned to the guest OS (e.g. max_outputs=n) so that all of them are
visible upon lauching.
v2: - making sure type of VC is GD_VC_GFX before qemu_console_is_graphic
(Gerd Hoffman)
- vc[0] is always primary guest displa
This patch seires is for adding some useful features for the guest os with
multi-displays. First patch is to make all of guest displays visible
when guest os is launched using "detach". Second patch is for providing
a method to assign each guest display to specific physical monitor,
which would be
4:59 +0200)
trivial patches pull request 20220629
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
Bernhard Beschow (3):
hw/pci-host/i440fx: Remove unused parameter from i
With the prior patch in this series adding support for RE^WE PAM
semantics, the '#ifndef BROKEN' segments of test_i440fx_pam can now be
enabled.
* tests/qtest/i440fx-test.c
test_i440fx_pam:
- Verify that changing attributes does not affect the initial contents
of the PAM region;
- Verify that th
The Programmable Attribute Registers (PAM) of QEMU's emulated i440FX
chipset now fully support the exclusive Read Enable (RE) and Write
Enable (WE) modes by forwarding reads of the applicable PAM region to
RAM and writes to the bus or vice versa, respectively. This chipset
functionality is often u
As detailed in the first patch of this series (8e64de1c), the
previously contiguous RAM aliased for the i440FX and Q35 machines was
broken into conventional [0-0xA] and extended regions
[0x10-...], creating a need for a new E820 entry to account for
the ISA MMIO area gap. This new entry sl
Hello,
This patch series (v4) implements full PAM emulation for the i440FX
and Q35 x86 platforms (see commit log for details.) Prior versions
did not support executing code from ROMs within the ISA MMIO range
when mode 2 was active (PAM_WE), but this series adds the requisite
support for new romd
On Thu, Jun 16, 2022 at 1:17 PM Anup Patel wrote:
>
> The latest AIA draft v0.3.0 addresses comments from the architecture
> review committee.
> (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
>
> There are primarily two changes:
> 1) Removing various [m|s|vs]seteienum, [m|
On Tue, Jun 28, 2022 at 10:17 AM Daniel P. Berrangé wrote:
>
> On Tue, Jun 28, 2022 at 05:49:39PM +0400, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > QMP accept is currently synchronous. If qemu dies before the connection
> > is established, it will wait there. Instead t
On Thu, Jun 16, 2022 at 1:17 PM Anup Patel wrote:
>
> The latest AIA draft v0.3.0 defines a relatively simpler scheme for
> default priority assignments where:
> 1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
>and have implementation specific default priority.
> 2) remai
On Thu, Jun 16, 2022 at 1:18 PM Anup Patel wrote:
>
> Based on architecture review committee feedback, the [m|s|vs]seteienum,
> [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
> removed in the latest AIA draft v0.3.0 specification.
> (Refer, https://github.com/riscv/riscv-aia/
On Mon, Jun 27, 2022 at 6:16 PM Christoph Müllner
wrote:
>
>
>
> On Mon, Jun 27, 2022 at 7:20 AM Alistair Francis wrote:
>>
>> On Fri, Jun 24, 2022 at 1:31 AM Christoph Muellner
>> wrote:
>> >
>> > This patch adds support for the Zawrs ISA extension.
>> > Given the current (incomplete) implement
From: Alistair Francis
The Ibex CPU supports version 1.11 of the priv spec [1], so let's
correct that in QEMU as well.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 del
From: Alistair Francis
There is nothing in the RISC-V spec that mandates version 1.12 is
required for ePMP and there is currently hardware [1] that implements
ePMP (a draft version though) with the 1.11 priv spec.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Fixes:
From: Alistair Francis
This fixes some issues discovered on the Ibex SoC when running OpenTitan tests.
Alistair Francis (2):
target/riscv: Fixup MSECCFG minimum priv check
target/riscv: Ibex: Support priv version 1.11
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 2 +-
2 files changed, 2
On 6/29/22 13:45, Vladimir Sementsov-Ogievskiy wrote:
The following changes since commit ad4c7f529a279685da84297773b4ec8080153c2d:
Merge tag 'pull-semi-20220628' of https://gitlab.com/rth7680/qemu into
staging (2022-06-28 10:24:31 +0530)
are available in the Git repository at:
https://g
On Wed, 15 Jun 2022 07:52:17 -0700
Steve Sistare wrote:
> If vfio_cpr_save fails to unmap all vaddr's, then recover by walking all
> flat sections to restore the vaddr for each. Do so by invoking the
> vfio listener callback, and passing a new "replay" flag that tells it
> to replay a mapping wi
On 6/29/22 02:56, Markus Armbruster wrote:
jianchunfu writes:
Add error reporting before return when opening file fails.
Signed-off-by: jianchunfu
---
target/ppc/kvm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index dc93b99189..ef9a871411
On 6/29/22 19:13, Alex Bennée wrote:
"Matheus K. Ferst" writes:
On 29/06/2022 12:36, Frederic Barrat wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que
você possa confirmar o remetente e saber que o conteúdo é seguro. Em
caso de e-mail suspeito entre imediatamente em con
On Wed, 15 Jun 2022 07:52:16 -0700
Steve Sistare wrote:
> Preserve vfio INTX state across cpr restart. Preserve VFIOINTx fields as
> follows:
> pin : Recover this from the vfio config in kernel space
> interrupt : Preserve its eventfd descriptor across exec.
> unmask : Ditto
> route.irq
On Wed, 15 Jun 2022 07:52:15 -0700
Steve Sistare wrote:
> Finish cpr for vfio-pci MSI/MSI-X devices by preserving eventfd's and
> vector state.
>
> Signed-off-by: Steve Sistare
> ---
> hw/vfio/pci.c | 122
> +-
> 1 file changed, 121 inse
On Jun 27 18:48, Jinhao Fan wrote:
> Add property "ioeventfd" which is enabled by default. When this is
> enabled, updates on the doorbell registers will cause KVM to signal
> an event to the QEMU main loop to handle the doorbell updates.
> Therefore, instead of letting the vcpu thread run both gue
For SEV-SNP, an OS is "SEV-SNP capable" without supporting this UEFI
v2.9 memory type. In order for OVMF to be able to avoid pre-validating
potentially hundreds of gibibytes of data before booting, it needs to
know if the guest OS can support its use of the new type of memory in
the memory map.
For SEV-SNP, an OS is "SEV-SNP capable" without supporting this UEFI
v2.9 memory type. In order for OVMF to be able to avoid pre-validating
potentially hundreds of gibibytes of data before booting, it needs to
know if the guest OS can support its use of the new type of memory in
the memory map.
Cc
On Wed, 15 Jun 2022 07:52:14 -0700
Steve Sistare wrote:
> Enable vfio-pci devices to be saved and restored across an exec restart
> of qemu.
>
> At vfio creation time, save the value of vfio container, group, and device
> descriptors in cpr state.
>
> In the container pre_save handler, suspend
> On Jun 29, 2022, at 11:04 AM, Titus Rwantare wrote:
>
> On Tue, 28 Jun 2022 at 20:36, Peter Delevoryas
> wrote:
>>
>> Signed-off-by: Peter Delevoryas
>> ---
>
>> --- a/hw/i2c/pmbus_device.c
>> +++ b/hw/i2c/pmbus_device.c
>> @@ -984,6 +984,11 @@ static uint8_t pmbus_receive_byte(SMBusDevic
> On Jun 29, 2022, at 11:05 AM, Titus Rwantare wrote:
>
> On Tue, 28 Jun 2022 at 20:36, Peter Delevoryas
> wrote:
>>
>> When a pmbus device switches pages, it should clears its output buffer so
>> that the next transaction doesn't emit data from the previous page.
>>
>> Fixes: 3746d5c15e7057
Cédric Le Goater writes:
> On 6/29/22 16:14, Alex Bennée wrote:
>> Cédric Le Goater writes:
>>
>>> On 6/24/22 18:50, Cédric Le Goater wrote:
On 6/23/22 20:43, Peter Delevoryas wrote:
>
>
>> On Jun 23, 2022, at 8:09 AM, Cédric Le Goater wrote:
>>
>> On 6/23/22 12:26,
On Tue, 28 Jun 2022 at 20:36, Peter Delevoryas
wrote:
>
> When a pmbus device switches pages, it should clears its output buffer so
> that the next transaction doesn't emit data from the previous page.
>
> Fixes: 3746d5c15e70570b ("hw/i2c: add support for PMBus”)
> Signed-off-by: Peter Delevoryas
On Tue, 28 Jun 2022 at 20:36, Peter Delevoryas
wrote:
>
> Signed-off-by: Peter Delevoryas
> ---
> --- a/hw/i2c/pmbus_device.c
> +++ b/hw/i2c/pmbus_device.c
> @@ -984,6 +984,11 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
> }
> break;
>
> +case PMBUS_IC_DEVICE_ID:
"Matheus K. Ferst" writes:
> On 29/06/2022 12:36, Frederic Barrat wrote:
>> [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que
>> você possa confirmar o remetente e saber que o conteúdo é seguro. Em
>> caso de e-mail suspeito entre imediatamente em contato com o DTI.
>> On 29/06/2
To preserve contributor CI credits we don't want jobs to run by default
unless the QEMU_CI variable is set. For most jobs we can achieve this
using the base template, but the edk2/opensbi jobs are a little special
as they have some complex conditions we can't easily model in the base
template.
We
In xen_pt_config_reg_init(), there is an error in the merging of the
emulated data with the host value. With the current Qemu, instead of
merging the emulated bits with the host bits as defined by emu_mask,
the emulated bits are merged with the host bits as defined by the
inverse of emu_mask. In so
Get rid of comments stating the obvious and re-arrange remaining
comments. The opensbi split of rules for file matches is also
merged into one rule.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/edk2.yml| 14 --
.gitlab-ci.d/opensbi.yml | 15 ---
2 files changed,
The edk2/opensbi gitlab CI config was using single space indents
which is not consistent with the rest of the gitlab CI config
files.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/edk2.yml| 108 +++---
.gitlab-ci.d/opensbi.yml | 110 +++---
When we introducd the QEMU_CI variable to control running of pipelines
in gitlab forks, we didn't include the ekd2/opensbi jobs in the rules.
This caused pipelines to be unexpectedly created in some cases. This
addresses that oversight.
Daniel P. Berrangé (3):
gitlab: normalize indentation in ed
On 6/29/22 18:07, Peter Delevoryas wrote:
On Jun 29, 2022, at 2:20 AM, Cédric Le Goater wrote:
On 6/29/22 05:36, Peter Delevoryas wrote:
This introduces a really basic PECI controller that responses to
commands by always setting the response code to success and then raising
an interrupt to
CHS-based disk utilities and operating systems may adjust the logical
geometry of a hard drive to cope with the expectations or limitations
of software using the ATA INITIALIZE_DEVICE_PARAMETERS command.
Prior to this patch, INITIALIZE_DEVICE_PARAMETERS was a nop that
always returned success, rais
From: Matheus Ferst
Implements the following Power ISA v2.06 instruction:
addg6s: Add and Generate Sixes
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
Reviewed-by: Víctor Colombo
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fixedpoint-impl.c.inc
Devices like the PIIX3/4 IDE controller do not support certain modes
of operation, such as memory space accesses, and indicate this lack of
support by hardwiring the applicable bits to zero. The QEMU PCI device
testing framework is hereby extended to accommodate such devices.
* tests/qtest/libqos/
From: Matheus Ferst
Implements the Convert Declets To Binary Coded Decimal instruction.
Since libdecnumber doesn't expose the methods for direct conversion
(decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero
exponent is used as an intermediate value to convert the declets.
Reviewed-
Add mffsce test to check both the return value and the new fpscr
stored in the cpu.
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
tests/tcg/ppc64/Makefile.target | 1 +
tests/tcg/ppc64le/Makefile.target | 1 +
tests/tcg/ppc64le/mffsce.c| 37 +++
From: Matheus Ferst
Adds an insns_flags2 for the BCD assist instructions introduced in
Power ISA 2.06. These instructions are not listed in the manuals for
e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10
models.
[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fp-impl.c.inc | 38 +-
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/ppc/
From: Matheus Ferst
Implements the Convert Binary Coded Decimal To Declets instruction.
Since libdecnumber doesn't expose the methods for direct conversion
(decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to
decimal32 format, from which the declets are extracted.
Where the behavior
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 5
target/ppc/translate/fp-impl.c.inc | 41 ++
2 files changed, 46 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 736a7c6f3f.
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 8 +++
target/ppc/internal.h | 3 --
target/ppc/translate/fp-impl.c.inc | 83 +++---
target/ppc/translate/fp-ops.c.inc | 4 --
4 files changed, 50 insertions
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 4
target/ppc/translate/fp-impl.c.inc | 35 +++---
target/ppc/translate/fp-ops.c.inc | 1 -
3 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/pp
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fp-impl.c.inc | 46 +++---
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/target/pp
Some lines in insn32.decode have inconsistent alignment when compared
to others.
Fix this by changing the alignment of some lines, making it more
consistent throughout the file.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode | 24 --
Hello everyone,
Set of patches containing implementations for some instructions that
were missing before. Also, moves some related instructions to
decodetree. Add mffsce test.
v3:
- Rebase on master
- Add r-b
v2:
- Added R-b on patches 1, 8, 10, and 11. Dropped the R-b on some
of the patches a
On 29/06/2022 12:36, Frederic Barrat wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 29/06/2022 00:17, Alex Bennée wrote:
If you ru
> On Jun 29, 2022, at 1:40 AM, Cédric Le Goater wrote:
>
> On 6/29/22 05:36, Peter Delevoryas wrote:
>> Signed-off-by: Peter Delevoryas
>
> This is also adding a "Renesas ISL69259 Digital Multiphase Voltage
> Regulator" device. There should be 2 patches.
H yes definitely, I’ll fix this.
Currently we check status of each submodule, before actually checking
if we're in a git repo. These status commands will all fail, but we
are hiding their output so we don't see it currently.
Signed-off-by: Daniel P. Berrangé
---
scripts/git-submodule.sh | 12 ++--
1 file changed, 6 inse
> On Jun 29, 2022, at 2:20 AM, Cédric Le Goater wrote:
>
> On 6/29/22 05:36, Peter Delevoryas wrote:
>> This introduces a really basic PECI controller that responses to
>> commands by always setting the response code to success and then raising
>> an interrupt to indicate the command is done. T
Frederic Barrat writes:
> On 29/06/2022 00:17, Alex Bennée wrote:
>> If you run the sync-profiler (via the HMP "sync-profile on") you can
>> then get a breakdown of which mutex's are being held and for how long
>> ("info sync-profile").
>
>
> Alex, a huge thank you!
>
> For the record, the "inf
On Wed, Jun 29, 2022 at 05:04:25PM +0800, Jinhao Fan wrote:
> Ping~
>
> > @@ -4271,6 +4343,11 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl
> > *n, uint64_t dma_addr,
> > if (n->dbbuf_enabled) {
> > sq->db_addr = n->dbbuf_dbs + (sqid << 3);
> > sq->ei_addr = n->dbbuf_ei
Hi Alex,
On Wed, Jun 29, 2022 at 04:24:20PM +0100, Alex Bennée wrote:
> > The code is exactly the same for kaslr-seed and rng-seed. Everytime
> > there's some kaslr-seed thing, there is now the same rng-seed thing.
>
> The duplication is annoying but specs are specs - where is this written
> by t
On 6/29/22 16:14, Alex Bennée wrote:
Cédric Le Goater writes:
On 6/24/22 18:50, Cédric Le Goater wrote:
On 6/23/22 20:43, Peter Delevoryas wrote:
On Jun 23, 2022, at 8:09 AM, Cédric Le Goater wrote:
On 6/23/22 12:26, Peter Delevoryas wrote:
Signed-off-by: Peter Delevoryas
Let's sta
On 29/06/2022 00:17, Alex Bennée wrote:
If you run the sync-profiler (via the HMP "sync-profile on") you can
then get a breakdown of which mutex's are being held and for how long
("info sync-profile").
Alex, a huge thank you!
For the record, the "info sync-profile" showed:
Type
"Jason A. Donenfeld" writes:
> On Wed, Jun 29, 2022 at 11:18:23AM +0100, Alex Bennée wrote:
>>
>> Peter Maydell writes:
>>
>> > On Tue, 28 Jun 2022 at 19:45, Jason A. Donenfeld wrote:
>> >>
>> >> On 6/27/22, Jason A. Donenfeld wrote:
>> >> > On 6/27/22, Peter Maydell wrote:
>> >> >> On Mo
Sven Schnelle writes:
> Sven Schnelle writes:
>
>> Alex Bennée writes:
>>
>>> Sven Schnelle writes:
>>>
Hi,
David Hildenbrand writes:
> On 04.05.22 09:37, Janosch Frank wrote:
>> I had a short look yesterday and the boot usually hangs in the raid6
>> code. D
On 6/27/22 15:31, Janosch Frank wrote:
On 6/20/22 16:03, Pierre Morel wrote:
We use new objects to have a dynamic administration of the CPU topology.
The highest level object in this implementation is the s390 book and
in this first implementation of CPU topology for S390 we have a single
boo
Change the job_{lock/unlock} and macros to use job_mutex.
Now that they are not nop anymore, remove the aiocontext
to avoid deadlocks.
Therefore:
- when possible, remove completely the aiocontext lock/unlock pair
- if it is used by some other function too, reduce the locking
section as much as po
From: Paolo Bonzini
We want to make sure access of job->aio_context is always done
under either BQL or job_mutex. The problem is that using
aio_co_enter(job->aiocontext, job->co) in job_start and job_enter_cond
makes the coroutine immediately resume, so we can't hold the job lock.
And caching it
Once job lock is used and aiocontext is removed, mirror has
to perform job operations under the same critical section,
using the helpers prepared in previous commit.
Note: at this stage, job_{lock/unlock} and job lock guard macros
are *nop*.
Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by:
Now that the API offers also _locked() functions, take advantage
of it and give also the caller control to take the lock and call
_locked functions.
This makes sense especially when we have for loops, because it
makes no sense to have:
for(job = job_next(); ...)
where each job_next() takes the l
job_event_* functions can all be static, as they are not used
outside job.c.
Same applies for job_txn_add_job().
Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
include/qemu/job.h | 18 --
job.c
In this series, we want to remove the AioContext lock and instead
use the already existent job_mutex to protect the job structures
and list. This is part of the work to get rid of AioContext lock
usage in favour of smaller granularity locks.
In order to simplify reviewer's job, job lock/unlock fun
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