Re: [PATCH] target/riscv: fix right shifts shamt value for rv128c

Le 09/07/2022 à 10:52, Weiwei Li a écrit : 在 2022/7/8 下午11:00, Frédéric Pétrot 写道: For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 --- disas/riscv.c | 27 +--

Re: [PATCH v6 03/10] i386/pc: pass pci_hole64_size to pc_memory_init()

Am 1. Juli 2022 16:10:07 UTC schrieb Joao Martins : >Use the pre-initialized pci-host qdev and fetch the >pci-hole64-size into pc_memory_init() newly added argument. >piix needs a bit of care given all the !pci_enabled() >and that the pci_hole64_size is private to i440fx. It exposes this value

Re: [PATCH v8 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels'

Second attempt of trying to resurrect this thread :-) May anybody please let us know what else is missing in this series of patches? I'm trying to add a 'query-nvmm' qmp command but got redirected to this thread. On 4/7/22 21:27, Antonio Huete Jimenez wrote: Are all these changes OK or is

Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default

在 2022/7/9 下午4:11, Weiwei Li 写道: 在 2022/7/8 下午3:39, Kito Cheng 写道: Default ELEN is setting to 64 for now, which is incorrect setting for Zve32*, and spec has mention minimum VLEN and supported EEW in chapter "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. ELEN actaully

Re: [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN

在 2022/7/8 下午3:39, Kito Cheng 写道: According RVV spec 1.0, the minmal requirement of VLEN is great than or equal to ELEN, and minmal possible ELEN is 32, and also spec has mention `Minimum VLEN` for zve32* is 32, so the lower bound of VLEN is 32 I think. [1]

Re: [PATCH 2/2] target/riscv: Implement dump content of vector register

在 2022/7/8 下午4:57, Kito Cheng 写道: Implement -d cpu,vu to dump content of vector register. Signed-off-by: Kito Cheng --- target/riscv/cpu.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

Re: [PATCH] target/riscv: fix right shifts shamt value for rv128c

在 2022/7/8 下午11:00, Frédéric Pétrot 写道: For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 --- disas/riscv.c | 27 +-- target/riscv/translate.c | 12

Re: [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN

在 2022/7/8 下午3:39, Kito Cheng 写道: According RVV spec 1.0, the minmal requirement of VLEN is great than or equal to ELEN, and minmal possible ELEN is 32, and also spec has mention `Minimum VLEN` for zve32* is 32, so the lower bound of VLEN is 32 I think. Sorry. I have a question about how to

Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default

在 2022/7/8 下午3:39, Kito Cheng 写道: Default ELEN is setting to 64 for now, which is incorrect setting for Zve32*, and spec has mention minimum VLEN and supported EEW in chapter "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. ELEN actaully could be derived from which extensions