On Fri, Jul 15, 2022 at 6:10 AM Jason Wang wrote:
>
> On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
> >
> > Since CVQ will be able to modify elements, the number of descriptors in
> > the guest may not match with the number of descriptors exposed. Track
> > separately.
> >
> >
On Fri, Jul 15, 2022 at 6:03 AM Jason Wang wrote:
>
> On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
> >
> > Since the vhost-vdpa device is exposing _F_LOG,
>
> I may miss something but I think it doesn't?
>
It's at vhost_vdpa_get_features. As long as SVQ is enabled, it's
exposing
On Fri, Jul 15, 2022 at 5:59 AM Jason Wang wrote:
>
> On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
> >
> > It allows the Shadow Control VirtQueue to wait for the device to use the
> > available buffers.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> >
On Fri, Jul 15, 2022 at 6:08 AM Jason Wang wrote:
>
> On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
> >
> > Do a simple forwarding of CVQ buffers, the same work SVQ could do but
> > through callbacks. No functional change intended.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> >
On Thu, 14 Jul 2022, Michael S. Tsirkin wrote:
> On Sun, Jul 10, 2022 at 10:30:10PM +0530, Ani Sinha wrote:
> > This change adds python based test environment that can be used to run
> > pytest
> > from within a virtual environment. A bash script sets up a virtual
> > environment
> > and
On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
>
> Finally offering the possibility to enable SVQ from the command line.
>
> Signed-off-by: Eugenio Pérez
> Acked-by: Markus Armbruster
> ---
> qapi/net.json| 9 +-
> net/vhost-vdpa.c | 72
On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
>
> Since CVQ will be able to modify elements, the number of descriptors in
> the guest may not match with the number of descriptors exposed. Track
> separately.
>
> Signed-off-by: Eugenio Pérez
> ---
> hw/virtio/vhost-shadow-virtqueue.h |
On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
>
> Do a simple forwarding of CVQ buffers, the same work SVQ could do but
> through callbacks. No functional change intended.
>
> Signed-off-by: Eugenio Pérez
> ---
> include/hw/virtio/vhost-vdpa.h | 3 ++
> hw/virtio/vhost-vdpa.c |
On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
>
> Since the vhost-vdpa device is exposing _F_LOG,
I may miss something but I think it doesn't?
Note that the features were fetched from the vDPA parent.
Thanks
> adding a migration blocker if
> it uses CVQ.
>
> Signed-off-by: Eugenio
On Fri, Jul 15, 2022 at 12:32 AM Eugenio Pérez wrote:
>
> It allows the Shadow Control VirtQueue to wait for the device to use the
> available buffers.
>
> Signed-off-by: Eugenio Pérez
> ---
> hw/virtio/vhost-shadow-virtqueue.h | 1 +
> hw/virtio/vhost-shadow-virtqueue.c | 22
Hello,
On 7/11/2022 6:44 PM, Hesham Almatary via wrote:
From: Brice Goglin
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting
Hey Cedric, Klaus, and Corey,
So I realized something about the current state of multi-master i2c:
We can't do transfers between two Aspeed I2C controllers, e.g. AST1030 <->
AST2600. I'm looking into this case in the new fby35 machine (which isn't even
merged yet, just in Cedric's pull request)
On 7/14/2022 3:59 PM, Paolo Bonzini wrote:
On 7/14/22 07:36, Zhenzhong Duan wrote:
On ICX-2S2 host, when run L2 guest with both L1/L2 using
Icelake-Server-v3
or above, we got below warning:
"warning: host doesn't support requested feature: MSR(10AH).taa-no
[bit 8]"
This is because L1 KVM
> -Original Message-
> From: Jean-Philippe Brucker
> Sent: Thursday, July 14, 2022 5:54 PM
> To: eric.au...@redhat.com
> Cc: m...@redhat.com; qemu-devel@nongnu.org; Jean-Philippe Brucker
> ; Zhang, Tina
> Subject: [PATCH] hw/virtio/virtio-iommu: Enforce power-of-two notify for
> both
On 7/14/22 18:53, Peter Maydell wrote:
In regime_tcr() we return the appropriate TCR register for the
translation regime. For Secure EL2, we return the VSTCR_EL2 value,
but in this translation regime some fields that control behaviour are
in VTCR_EL2. When this code was originally written (as
On 7/14/22 18:53, Peter Maydell wrote:
Change the representation of the TCR_EL* registers in the CPU state
struct from struct TCR to uint64_t. This allows us to drop the
custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0"
checks to their more usual location in the writefn
On 7/14/22 18:53, Peter Maydell wrote:
Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in
the CPU state struct from struct TCR to uint64_t.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 4 ++--
target/arm/helper.c| 4 +---
On 7/14/22 18:53, Peter Maydell wrote:
We have a bug in our handling of accesses to the AArch32 VTCR
register on big-endian hosts: we were not adjusting the part of the
uint64_t field within TCR that the generated code would access. That
can be done with offsetoflow32(), by using an
On 7/14/22 18:52, Peter Maydell wrote:
The only caller of regime_tcr() is now regime_tcr_value(); fold the
two together, and use the shorter and more natural 'regime_tcr'
name for the new function.
Signed-off-by: Peter Maydell
---
target/arm/internals.h | 16 +---
On 7/14/22 18:52, Peter Maydell wrote:
In get_level1_table_address(), instead of using precalculated values
of mask and base_mask from the TCR struct, calculate them directly
(in the same way we currently do in vmsa_ttbcr_raw_write() to
populate the TCR struct fields).
Signed-off-by: Peter
On 7/14/22 18:52, Peter Maydell wrote:
The regime_tcr() function returns a pointer to a struct TCR
corresponding to the TCR controlling a translation regime. The
struct TCR has the raw value of the register, plus two fields mask
and base_mask which are used as a small optimization in the case
On Wed, Jul 13, 2022 at 04:32:49PM +0300, Konstantin Kostiuk wrote:
> Signed-off-by: Konstantin Kostiuk
Acked-by: Michael Roth
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 450abd0252..22a4ffe0a2 100644
> --- a/MAINTAINERS
>
Author: John Snow - https://gitlab.com/jsnow
Merge Request:
https://gitlab.com/qemu-project/python-qemu-qmp/-/merge_requests/8
... from: jsnow/python-qemu-qmp:packaging
... into: qemu-project/python-qemu-qmp:main
This is all about streamlining the process of tagging, building, and
publishing.
Hello Peter,
Thank you for the review. Please see my comments inline.
Thank you,
Mahesh
On 7/14/22 8:10 AM, Peter Maydell wrote:
On Thu, 14 Jul 2022 at 14:04, Maheswara Kurapati
wrote:
This fix adds object properties for the FAN_COMMAND_1 (3Bh), STATUS_FANS_1_2
(81h),
READ_FAN_SPEED_1
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/1/22 10:34, Lucas Coutinho wrote:
Resent after rebasing and fixing conflicts with master.
Add Leandro Lupori as reviewer.
Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br>
Implement the following PowerISA
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/12/22 16:37, Leandro Lupori wrote:
Changes from v2:
- Moved TLBIE defines from helper.h to mmu-book3s-v3.h
Leandro Lupori (2):
target/ppc: Move tlbie[l] to decode tree
target/ppc: Implement ISA 3.00 tlbie[l]
On 7/14/22 14:23, Matheus Ferst wrote:
When using "-machine none", env->tb_env is not allocated, causing the
segmentation fault reported in issue #85 (launchpad bug #811683). To
avoid this problem, check if the pointer != NULL before calling the
methods to print TBU/TBL/DECR.
Resolves:
On Thu, Jul 14, 2022 at 07:49:36PM +0530, Ani Sinha wrote:
> > so you skip downlaod if it already exists locally. IIUC it is looking
> > in the CWD, which is presumably the directory the QEMU build is
> > performed in ?
>
> Yes, build/test/pytest/bits-test
>
> > So if dev cleans their build
On Sun, Jul 10, 2022 at 10:30:10PM +0530, Ani Sinha wrote:
> This change adds python based test environment that can be used to run pytest
> from within a virtual environment. A bash script sets up a virtual environment
> and then runs the python based tests from within that environment.
> All
On 7/14/22 16:57, Janis Schoetterl-Glausch wrote:
On 6/20/22 16:03, Pierre Morel wrote:
S390x CPU Topology allows a non uniform repartition of the CPU
inside the topology containers, sockets, books and drawers.
We use numa to place the CPU inside the right topology container
and report the
On 7/14/22 20:43, Janis Schoetterl-Glausch wrote:
On 6/20/22 16:03, Pierre Morel wrote:
Hi,
This new spin is essentially for coherence with the last Linux CPU
Topology patch, function testing and coding style modifications.
Forword
===
The goal of this series is to implement CPU
This observation came up during the review of "Move tlbie[l] to decode
tree" patch [1] and it seems useful enough to be added in the docs.
[1] https://lists.gnu.org/archive/html/qemu-devel/2022-07/msg02195.html
Signed-off-by: Daniel Henrique Barboza
---
docs/devel/decodetree.rst | 4 +++-
1
On 7/14/22 16:31, Leandro Lupori wrote:
On 7/14/22 15:45, Daniel Henrique Barboza wrote:
On 7/12/22 16:37, Leandro Lupori wrote:
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c | 4 +-
target/ppc/insn32.decode
On 7/14/22 15:45, Daniel Henrique Barboza wrote:
On 7/12/22 16:37, Leandro Lupori wrote:
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c | 4 +-
target/ppc/insn32.decode | 8 ++
On 7/14/22 14:50, Janis Schoetterl-Glausch wrote:
On 7/14/22 13:25, Pierre Morel wrote:
[...]
That is sure.
I thought about put a fatal error report during the initialization in the
s390_topology_setup()
And you can set thread > 1 today, so we'd need to handle that. (increase the
The added enforcing is only relevant in the case of AMD where the
range right before the 1TB is restricted and cannot be DMA mapped
by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
or possibly other kinds of IOMMU events in the AMD IOMMU.
Although, there's a case where it may
Factor out the calculation of the base address of the memory region.
It will be used later on for the cxl range end counterpart calculation
and as well in pc_memory_init() CXL memory region initialization, thus
avoiding duplication.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
On 7/12/22 16:37, Leandro Lupori wrote:
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are
On 6/20/22 16:03, Pierre Morel wrote:
> Hi,
>
> This new spin is essentially for coherence with the last Linux CPU
> Topology patch, function testing and coding style modifications.
>
> Forword
> ===
>
> The goal of this series is to implement CPU topology for S390, it
> improves the
Move calculation of CXL memory region end to separate helper.
This is in preparation to a future change that removes CXL range
dependency on the CXL memory region, with the goal of allowing
pc_pci_hole64_start() to be called before any memory region are
initialized.
Cc: Jonathan Cameron
v6[7] -> v7:
* Rebased to latest staging
* Build on top of apply CXL cleanups (Igor Mammedov)
* Use qdev property rather introducing new acessors to the i440fx pci-host
(Bernhard Beschow)
* Add Igor's Rb to patch 4 (Igor Mammedov)
* Replace pci_hole64_start() related helper functions rather than
On 7/12/22 16:37, Leandro Lupori wrote:
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 8 ++
target/ppc/translate.c | 64 +-
There's a couple of places that seem to duplicate this calculation
of RAM size above the 4G boundary. Move all those to a helper function.
Signed-off-by: Joao Martins
Reviewed-by: Igor Mammedov
---
hw/i386/pc.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
At the start of pc_memory_init() we usually pass a range of
0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
32G (q35). To get the real user value, we need to get pci-host
passed property for default pci_hole64_size. Thus to get that,
create the qdev prior to memory init to better make
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, except for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or
This patch allows the user to attach an external drive as a property
for an onboard at24c eeprom device. It uses an unit number to
distinguish different devices.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git
We allow at24c_eeprom_init to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git
Use the pre-initialized pci-host qdev and fetch the
pci-hole64-size into pc_memory_init() newly added argument.
Use PCI_HOST_PROP_PCI_HOLE64_SIZE pci-host property for
fetching pci-hole64-size.
This is in preparation to determine that host-phys-bits are
enough and for pci-hole64-size to be
Move obtaining hole64_start from device_memory memory region base/size
into an helper alongside correspondent getters in pc_memory_init() when
the hotplug range is unitialized. While doing that remove the memory
region based logic from this newly added helper.
This is the final step that allows
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed,
Rather than hardcoding the 4G boundary everywhere, introduce a
X86MachineState field @above_4g_mem_start and use it
accordingly.
This is in preparation for relocating ram-above-4g to be
dynamically start at 1T on AMD platforms.
Signed-off-by: Joao Martins
Reviewed-by: Igor Mammedov
---
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by:
Remove pc_get_cxl_range_end() dependency on the CXL memory region,
and replace with one that does not require the CXL host_mr to determine
the start of CXL start.
This in preparation to allow pc_pci_hole64_start() to be called early
in pc_memory_init(), handle CXL memory region end when its
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
[NOTE: I'm reviving a bunch of patches that was in the process of
upstreaming a while ago but paused.]
This patch set contains a few bug fixes and I2C devices for some
NPCM7XX boards.
Patch 1~2 fix a problem that causes the SMBus module to behave
incorrectly when it's in FIFO mode and trying to
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed,
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by:
[NOTE: I'm reviving a bunch of patches that was in the process of
upstreaming a while ago but paused.]
This patch set contains a few bug fixes and I2C devices for some
NPCM7XX boards.
Patch 1~2 fix a problem that causes the SMBus module to behave
incorrectly when it's in FIFO mode and trying to
DO NOT MERGE THIS RFC
... so we can evaluate if it is worth to move.
Answering [1].
It basically makes SVQ work in two different modes:
* data virtqueues works with the SVQ loop, intercepting guest's kicks
and device's call.
* CVQ does not move to that. Instead
- It "forbid" to vhost-dev to
We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
This patch allows the user to attach an external drive as a property
for an onboard at24c eeprom device. It uses an unit number to
distinguish different devices.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed,
We allow at24c_eeprom_init to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by:
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
[NOTE: I'm reviving a bunch of patches that was in the process of
upstreaming a while ago but paused.]
This patch set contains a few bug fixes and I2C devices for some
NPCM7XX boards.
Patch 1~2 fix a problem that causes the SMBus module to behave
incorrectly when it's in FIFO mode and trying to
On Thu, Jul 14, 2022 at 19:49 Ani Sinha wrote:
>
>
> On Thu, 14 Jul 2022, Daniel P. Berrangé wrote:
>
> > On Sun, Jul 10, 2022 at 10:30:10PM +0530, Ani Sinha wrote:
> > > This change adds python based test environment that can be used to run
> pytest
> > > from within a virtual environment. A
On Thu, Jul 14, 2022 at 9:04 AM Jason Wang wrote:
>
> On Thu, Jul 14, 2022 at 2:54 PM Eugenio Perez Martin
> wrote:
> >
> > > > > +static void vhost_vdpa_net_handle_ctrl_used(VhostShadowVirtqueue
> > > > > *svq,
> > > > > +void *vq_elem_opaque,
> > >
When using "-machine none", env->tb_env is not allocated, causing the
segmentation fault reported in issue #85 (launchpad bug #811683). To
avoid this problem, check if the pointer != NULL before calling the
methods to print TBU/TBL/DECR.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/85
Hi, Alex and Richard,
I implemented the changes you suggested in this conversation:
https://lists.nongnu.org/archive/html/qemu-devel/2022-05/threads.html#04679
The 9:th patch which updated libvirt-ci and added flex/bison to the
CI containers, has now been split into 5 separate patches that:
On Wed, 13 Jul 2022 at 11:19, Konstantin Kostiuk wrote:
>
> The following changes since commit 08c8a31214e8ca29e05b9f6c3ee942b28ec58457:
>
> Merge tag 'pull-tcg-20220712' of https://gitlab.com/rth7680/qemu into
> staging (2022-07-12 11:52:11 +0530)
>
> are available in the Git repository at:
>
Future code needs to call it from vhost_svq_add.
No functional change intended.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/virtio/vhost-shadow-virtqueue.c
From: Tobias Röhmel
The Cortex-R52 can access SPSR_hyp from hypervisor mode
as discussed here: https://github.com/zephyrproject-rtos/zephyr/issues/47330
Signed-off-by: Tobias Röhmel
---
target/arm/op_helper.c | 8
target/arm/translate.c | 5 +++--
2 files changed, 11 insertions(+), 2
On Thu, 14 Jul 2022 at 16:46, Peter Maydell wrote:
>
> On Thu, 14 Jul 2022 at 15:54, Tobias Roehmel wrote:
> >
> > From: Tobias Röhmel
> >
> > The Cortex-R52 can access SPSR_hyp from hypervisor mode
> > as discussed here: https://github.com/zephyrproject-rtos/zephyr/issues/47330
>
> The v8R
From: Tobias Röhmel
The Cortex-R52 has a 2 stage MPU translation process but doesn't have the
FEAT_S2FWB feature. This makes it neccessary to allow for the old cache
attribut combination.
This is facilitated by changing the control path of combine_cacheattrs instead
of failing if the second
On 12.07.22 23:19, Emanuele Giuseppe Esposito wrote:
-
RFC because I am not sure about the AioContext locks.
- Do we need to take the new AioContext lock? what does it protect?
- Taking the old AioContext lock is required now, because of
bdrv_drained_begin calling AIO_WAIT_WHILE that
From: Tobias Röhmel
Enable TTBCR_EAE during reset since it's always set to 1 for Cortex-R52.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c | 3 +++
1 file
These patches add the ARM Cortex-R52. The biggest addition is
an implementation of the armv8-r MPU.
The last patch adds a machine that combines the new core with
an UART and a GIC. This machine can run many samples of
the Zephyr OS.
All information is taken from:
- ARM Cortex-R52 TRM revision
From: Tobias Röhmel
This register is used by the ARM Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/helper.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6457e6301c..bdf1df37d5 100644
---
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
configs/devices/arm-softmmu/default.mak | 1 +
hw/arm/Kconfig | 5 +
hw/arm/meson.build | 1 +
hw/arm/r52_machine.c| 133 +++
hw/arm/r52_virt.c
Since the vhost-vdpa device is exposing _F_LOG, adding a migration blocker if
it uses CVQ.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost-vdpa.h | 1 +
hw/virtio/vhost-vdpa.c | 14 ++
2 files changed, 15 insertions(+)
diff --git a/include/hw/virtio/vhost-vdpa.h
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
---
target/arm/cpu_tcg.c | 54
1 file changed, 54 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
This allows external handlers to be aware of new buffers that the guest
places in the virtqueue.
When this callback is defined the ownership of the guest's virtqueue
element is transferred to the callback. This means that if the user
wants to forward the descriptor it needs to manually inject it.
Finally offering the possibility to enable SVQ from the command line.
Signed-off-by: Eugenio Pérez
Acked-by: Markus Armbruster
---
qapi/net.json| 9 +-
net/vhost-vdpa.c | 72 ++--
2 files changed, 77 insertions(+), 4 deletions(-)
diff --git
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h| 10 +++
target/arm/helper.c | 171
2 files changed, 181 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 86e06116a9..632d0d13c6 100644
---
Do a simple forwarding of CVQ buffers, the same work SVQ could do but
through callbacks. No functional change intended.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost-vdpa.h | 3 ++
hw/virtio/vhost-vdpa.c | 3 +-
net/vhost-vdpa.c | 58
It allows the Shadow Control VirtQueue to wait for the device to use the
available buffers.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 1 +
hw/virtio/vhost-shadow-virtqueue.c | 22 ++
2 files changed, 23 insertions(+)
diff --git
Introduce the control virtqueue support for vDPA shadow virtqueue. This
is needed for advanced networking features like rx filtering.
Virtio-net control VQ copies the descriptors to qemu's VA, so we avoid
TOCTOU with the guest's or device's memory every time there is a device
model change.
To know the device features is needed for CVQ SVQ, so SVQ knows if it
can handle all commands or not. Extract from
vhost_vdpa_get_max_queue_pairs so we can reuse it.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 30 --
1 file changed, 20
Since CVQ will be able to modify elements, the number of descriptors in
the guest may not match with the number of descriptors exposed. Track
separately.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 6 ++
hw/virtio/vhost-shadow-virtqueue.c | 10 +-
2 files
Shadow CVQ will copy buffers on qemu VA, so we avoid TOCTOU attacks from
the guest that could set a different state in qemu device model and vdpa
device.
To do so, it needs to be able to map these new buffers to the device.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
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