Hello!
I'd like to implement support for emulating the teensy 4.1 board (
https://www.pjrc.com/store/teensy41.html) to QEMU.
I'm honestly quite lost as to where to start at the moment, since I can't
really find any emulated Cortex-M7 that would be close to that board
already implemented.
I asked
Hi all,
Just a small addition to make boston board easier to use :-)
Thanks
- Jiaxun
Jiaxun Yang (2):
mips/boston: Support initrd for ELF kernel
hw/mips/boston: Pack fdt in fdt filter
hw/mips/boston.c | 40
1 file changed, 40 insertions(+)
--
2.32
When loading ELF kernel we can just load out initrd after DTB
and append initrd information to DeviceTree's chosen node.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.
FDT can be awfully fat after series of modifications in fdt
filter. Just pack it up before add to ram.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 5145179951..a40f193f78 100644
--- a/hw/mips/boston.
[add migration maintainers]
On 8/11/22 19:49, Andrey Ryabinin wrote:
pxb/pxb-pcie/pxb-cxl devices currently doesn't have vmstate description
So the state of device is not preserved during migration and
guest can notice that as change of PCI_COMMAND_* registers state.
The diff of lspci output be
Leonardo Brás wrote:
> Hello Juan,
>
> On Tue, 2022-08-02 at 08:38 +0200, Juan Quintela wrote:
>> We were calling qemu_target_page_size() left and right.
>>
>> Signed-off-by: Juan Quintela
>
> IMHO looks a good idea to bring that info inside the multifd parameters.
Thanks.
[...]
> IIUC this i
Remove default case labels that do nothing or only there to set a
default value that could easily be done at the variable definition
instead.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405_boards.c | 7 +--
hw/ppc/ppc405_uc.c | 29 +
hw/ppc/ppc440_uc.c |
Now that shared PPC4xx devices are separated from PPC405 ones we can
drop this depencency.
Signed-off-by: BALATON Zoltan
---
hw/ppc/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 400511c6b7..205f9f98d7 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kco
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f5806f06e7..3311b30a81 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/
Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
link and make it uniform with the other PPC4xx devices.
Signed-off-by: BALATON Zoltan
---
hw/intc/ppc-uic.c | 26 ++
hw/ppc/ppc405_uc.c| 6 ++
hw/ppc/ppc440_bamboo.c| 7 ++
From: Cédric Le Goater
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 1 +
hw/ppc/pp
These are only used by tha board code so move out from the shared SoC
model and put it in the boards file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 38 -
hw/ppc/ppc405_boards.c | 375 +++--
hw/ppc/ppc405_uc.c | 92 --
3 file
Le 11/08/2022 à 17:18, Alex Bennée a écrit :
Laurent Vivier writes:
Le 11/08/2022 à 13:54, Peter Maydell a écrit :
On Thu, 11 Aug 2022 at 09:29, Laurent Vivier wrote:
Le 10/08/2022 à 22:47, Richard Henderson a écrit :
On 8/10/22 13:32, Vitaly Buka wrote:
Sorry, I only noticed today that
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405_boards.c | 56 +-
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 3677793adc..7af
The PLB is shared between 405 and 440 so move it to the shared file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 11 -
hw/ppc/ppc405_uc.c | 93
hw/ppc/ppc4xx_devs.c| 94 +
include/hw/ppc
Leonardo Brás wrote:
> On Tue, 2022-08-02 at 08:38 +0200, Juan Quintela wrote:
>> Signed-off-by: Juan Quintela
>> Reviewed-by: Dr. David Alan Gilbert
>> Reviewed-by: David Edmondson
>> Signed-off-by: Juan Quintela
>
> Is this doubled Signed-off-by intentional?
It is .git/hooks/prepare-commit-
From: Cédric Le Goater
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 14 --
hw/ppc/ppc405_uc.c | 64
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 28 ++--
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c0251f0894..5bcbc
From: Cédric Le Goater
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 12 +++
hw/ppc/ppc405_uc.c | 49 +++--
h
The EBC is shared between 405 and 440 so move it to shared file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 15
hw/ppc/ppc405_uc.c | 191
hw/ppc/ppc4xx_devs.c| 191
include/hw/ppc/pp
From: Cédric Le Goater
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus from the machine init routine.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 2 ++
hw/ppc/ppc405_uc.c | 10 --
2 files change
From: Cédric Le Goater
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 21 +++
hw/ppc/ppc405_uc.c | 50 ++---
In pegasos2 section move imply before select to match other sections.
Signed-off-by: BALATON Zoltan
---
hw/ppc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 205f9f98d7..3a4418a69e 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
From: Cédric Le Goater
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 22 ++
hw/ppc/ppc405_uc.c | 99
From: Cédric Le Goater
POB is currently modeled as a simple DCR device.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 12 ++
hw/ppc/ppc405_uc.c | 56 ++
2 files changed, 44 insertions(+), 24 deletions
From: Cédric Le Goater
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 17 -
hw/ppc/ppc405_uc.c | 62
From: Cédric Le Goater
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 16 ++
hw/ppc/ppc405_uc.c | 77 +++---
From: Cédric Le Goater
The DMA controller is currently modeled as a DCR device with a couple
of IRQs.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 19 ++
hw/ppc/ppc405_uc.c | 141 -
2 files changed, 81
From: Cédric Le Goater
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
From: Cédric Le Goater
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model th
Hello,
This is mased on gitlab.com/danielhb/qemu/tree/ppc-7.2
This series contains the rest of Cédric's patches modified according
my review comments and some other small clean ups I've noticed along
the way. I've kept the From line of Cédric for patches that were
originally his even though they
On Sat, 13 Aug 2022 at 12:27, Anton Kochkov wrote:
>
> Cortex-M NVIC can be configured with different amount of
> the maximum available priority bits. FreeRTOS has asserts
> that checks if the all unavailable priority bits are unset
> after writing into this register in real hardware.
This assert
From: Conor Dooley
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot
entirely is probably not advisable, but it does at least show signs of
life. Recent Linux kernel versions make use of peripherals that are
missing definitions in QEMU and lead to kernel panics. These issues
On Sat, 13 Aug 2022 12:11:37 +0100,
Vitaly Chikunov wrote:
>
> Marc,
>
> On Fri, Aug 12, 2022 at 04:02:37PM +0100, Marc Zyngier wrote:
> > On Fri, 12 Aug 2022 10:25:55 +0100,
> > Peter Maydell wrote:
> > >
> > > I've added some more relevant mailing lists to the cc.
> > >
> > > On Fri, 12 Aug
While Meson buildsystem accepts the 'false' as a value
for boolean options, it's not covered by the specification
and in general invalid. Some alternative Meson implementations,
like Muon, do not accept 'false' or 'true' as a valid value
for the boolean options.
See https://mesonbuild.com/Build-op
* Implement Octal SPI commands based on Micron MT35X series
* Fix Micron 0x2C-based ID handling (incompatible with Numonyx)
* Fix Micron configuration registers handling
Signed-off-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1148
Resolves: https://gitlab.com/qemu-pro
On 8/12/22 02:19, Xiaojuan Yang wrote:
1. Add some information about how to boot the LoongArch virt
machine by uefi bios and linux kernel and how to access the
source code or binary file.
2. Move the explanation of LoongArch system emulation in the
target/loongarch/README to docs/system/loongarch
Cortex-M NVIC can be configured with different amount of
the maximum available priority bits. FreeRTOS has asserts
that checks if the all unavailable priority bits are unset
after writing into this register in real hardware.
To allow setting this number depending on the machine or
configuration exp
Marc,
On Fri, Aug 12, 2022 at 04:02:37PM +0100, Marc Zyngier wrote:
> On Fri, 12 Aug 2022 10:25:55 +0100,
> Peter Maydell wrote:
> >
> > I've added some more relevant mailing lists to the cc.
> >
> > On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > > On Fri, Aug 12, 2022 at 05:14:27AM
On Sat, 13 Aug 2022 at 00:23, Furquan Shaikh wrote:
>
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels - M, S, U,
On Sat, 13 Aug 2022 at 01:53, Furquan Shaikh wrote:
> I ran into a problem when I was testing a project (with a microkernel
> in M-mode and tasks in U-mode) that uses semihosting for debugging.
> The semihosting worked fine for M-mode but not in U-mode. As I started
> digging into this, I realized
Hi,
On Fri, Aug 12, 2022 at 10:57:08PM -0700, Joelle van Dyne wrote:
> On Fri, Aug 12, 2022 at 10:50 PM Victor Toso wrote:
> >
> > Hi,
> >
> > On Fri, Aug 12, 2022 at 10:33:54PM -0700, Joelle van Dyne wrote:
> > > On Fri, Aug 12, 2022 at 10:30 PM Victor Toso
> > > wrote:
> > > >
> > > > Hi,
> >
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