Re: [PATCH 7/7] vdpa: Use ring hwaddr at vhost_vdpa_svq_unmap_ring

在 2022/8/20 00:53, Eugenio Pérez 写道: Reduce code duplication. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang (In the future, we need to look for other cases where a function may use only a partial of DMAMap.) Thanks --- hw/virtio/vhost-vdpa.c | 17 - 1 file ch

Re: [PATCH v9 11/12] vdpa: Add virtio-net mac address via CVQ at start

在 2022/8/20 01:00, Eugenio Pérez 写道: This is needed so the destination vdpa device see the same state a the guest set in the source. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang --- v9: * Use guest acked features instead of device's. * Constify vhost_vdpa and VirtIONet variables.

Re: [PATCH 4/7] vdpa: Remove SVQ vring from iova_tree at shutdown

在 2022/8/20 00:53, Eugenio Pérez 写道: Although the device will be reset before usage, the right thing to do is to clean it. Reported-by: Lei Yang Fixes: 34e3c94eda ("vdpa: Add custom IOTLB translations to SVQ") Signed-off-by: Eugenio Pérez --- hw/virtio/vhost-vdpa.c | 7 ++- 1 file cha

Re: [PATCH 6/7] vhost: Always store new kick fd on vhost_svq_set_svq_kick_fd

在 2022/8/20 00:53, Eugenio Pérez 写道: We can unbind twice a file descriptor if we call twice vhost_svq_set_svq_kick_fd because of this. Since it comes from vhost and not from SVQ, that file descriptor could be a different thing that guest's vhost notifier. Likewise, it can happens the same if a

Re: [PATCH 5/7] vdpa: Make SVQ vring unmapping return void

在 2022/8/20 00:53, Eugenio Pérez 写道: Nothing actually reads the return value, but an error in cleaning some entries could cause device stop to abort, making a restart impossible. Better ignore explicitely the return value. Reported-by: Lei Yang Fixes: 34e3c94eda ("vdpa: Add custom IOTLB trans

Re: [PATCH 3/7] util: make a copy of iova_tree_remove_parameter

在 2022/8/20 00:53, Eugenio Pérez 写道: It's convenient to call iova_tree_remove from a map returned from iova_tree_find or iova_tree_find_iova. The looks like a hint of the defect of current API. With the current code this is not possible, since we will free it, and then we will try to se

[PATCH v4 4/4] hw/ssi: ibex_spi: update reg addr

From: Wilfred Mallawa Updates the `EVENT_ENABLE` register to offset `0x34` as per OpenTitan spec [1]. [1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 2 +- 1 file changed, 1 insertio

[PATCH v4 3/4] hw/ssi: ibex_spi: fixup/add rw1c functionality

From: Wilfred Mallawa This patch adds the `rw1c` functionality to the respective registers. The status fields are cleared when the respective field is set. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 34 --

[PATCH v4 1/4] hw/ssi: ibex_spi: fixup typos in ibex_spi_host

From: Wilfred Mallawa This patch fixes up minor typos in ibex_spi_host Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- hw/ssi/ibex_spi_host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/i

[PATCH v4 2/4] hw/ssi: ibex_spi: fixup coverity issue

From: Wilfred Mallawa This patch addresses the coverity issues specified in [1], as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been implemented to clean up the code. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html Fixes: Coverity CID 1488107 Signed-off-by: Wilfr

[PATCH v4 0/4] hw/ssi: ibex_spi: cleanup and fixup bugs

From: Wilfred Mallawa Patch V4 fixes up: - Fixup missing register field clearing on tx/rx_fifo_reset() in [2/4] Testing: - Tested with Opentitan unit tests for TockOS...[OK] Wilfred Mallawa (4): hw/ssi: ibex_spi: fixup typos in ibex_spi_host hw/ssi: ibex_spi: fixup coverity issue

[PATCH] vhost: reduce the set_mem_table call frenquency

If the vhost memory layout doesn't change, don't need to call the vhost backend. The set_mem_table is time consuming when sending to vhost-user backend. On aarch64, the edk2 uefi firmware will write the pflash which will trigger the vhost_commit hundreds of times. Signed-off-by: Li Feng --- hw/

[PATCH] target/avr: Support probe argument to tlb_fill

While there are no target-specific nonfaulting probes, generic code may grow some uses at some point. Note that the attrs argument was incorrect -- it should have been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface. Signed-off-by: Richard Henderson --- target/avr/helper.c | 46 +

Re: [PATCH v7 2/8] file-posix: introduce get_sysfs_str_val for device zoned model

Stefan Hajnoczi 于2022年8月23日周二 07:05写道： > > On Tue, Aug 16, 2022 at 02:25:16PM +0800, Sam Li wrote: > > +static int hdev_get_max_segments(int fd, struct stat *st) { > > +int ret; > > +if (S_ISCHR(st->st_mode)) { > > +if (ioctl(fd, SG_GET_SG_TABLESIZE, &ret) == 0) { > > The ioctl mus

Re: [PATCH v7 6/8] config: add check to block layer

Stefan Hajnoczi 于2022年8月23日周二 08:54写道： > > On Tue, Aug 16, 2022 at 02:25:20PM +0800, Sam Li wrote: > > Putting zoned/non-zoned BlockDrivers on top of each other is not > > allowed. > > > > Signed-off-by: Sam Li > > Reviewed-by: Stefan Hajnoczi > > --- > > block.c | 14 +

Re: [PATCH v7 4/8] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

Stefan Hajnoczi 于2022年8月23日周二 08:49写道： > > On Tue, Aug 16, 2022 at 02:25:18PM +0800, Sam Li wrote: > > By adding zone management operations in BlockDriver, storage controller > > emulation can use the new block layer APIs including Report Zone and > > four zone management operations (open, close,

Re: [RFC 5/8] vdpa: Add vdpa memory listener

On Fri, Aug 19, 2022 at 6:35 PM Eugenio Perez Martin wrote: > > On Fri, Aug 19, 2022 at 11:01 AM Jason Wang wrote: > > > > On Fri, Aug 19, 2022 at 4:30 PM Eugenio Perez Martin > > wrote: > > > > > > On Fri, Aug 19, 2022 at 8:29 AM Jason Wang wrote: > > > > > > > > On Thu, Aug 11, 2022 at 2:42 A

RE: [PATCH V5] net/colo.c: Fix the pointer issue reported by Coverity.

> -Original Message- > From: Jason Wang > Sent: Tuesday, August 23, 2022 10:03 AM > To: Zhang, Chen > Cc: Peter Maydell ; Li Zhijian > ; qemu-dev > Subject: Re: [PATCH V5] net/colo.c: Fix the pointer issue reported by > Coverity. > > On Mon, Aug 22, 2022 at 4:29 PM Zhang Chen wrote:

Re: [PATCH 00/14] target/i386: Use atomic operations for pte updates

On 8/22/22 16:57, Richard Henderson wrote: This patch set does two things: (1) Remove assert(!probe) from the x86 tlb_fill It turns out that this is a prerequisite for [PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping to non-readable pages because of a new us

Re: [PATCH V5] net/colo.c: Fix the pointer issue reported by Coverity.

On Mon, Aug 22, 2022 at 4:29 PM Zhang Chen wrote: > > When enabled the virtio-net-pci, guest network packet will > load the vnet_hdr. In COLO status, the primary VM's network > packet maybe redirect to another VM, it needs filter-redirect > enable the vnet_hdr flag at the same time, COLO-proxy wil

Re: [PATCH 00/24] Support VIRTIO_F_RING_RESET for virtio-net, vhost-user, vhost-kernel in virtio pci-modern

Forgot to append changelog for v2 in the cover letter, so I add it in this email. changelog: 1. Add support for vhost-net scenario 2. Add a new vhost-user message VHOST_USER_RESET_VRING 3. Add migration compatibility for virtqueue reset Looking forward to your review and comments to this p

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On Wed, Aug 17, 2022 at 10:27:19AM -0500, Michael Roth wrote: > > I think the best approach is to turn KVM_TDX_INIT_MEM_REGION into a generic > > vCPU-scoped ioctl() that allows userspace to pre-map guest memory. > > Supporting > > initializing guest private memory with a source page can be imp

Re: [PATCH v7 6/8] config: add check to block layer

On Tue, Aug 16, 2022 at 02:25:20PM +0800, Sam Li wrote: > Putting zoned/non-zoned BlockDrivers on top of each other is not > allowed. > > Signed-off-by: Sam Li > Reviewed-by: Stefan Hajnoczi > --- > block.c | 14 ++ > block/raw-format.c | 1 +

Re: [PATCH v7 4/8] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

On Tue, Aug 16, 2022 at 02:25:18PM +0800, Sam Li wrote: > By adding zone management operations in BlockDriver, storage controller > emulation can use the new block layer APIs including Report Zone and > four zone management operations (open, close, finish, reset). > > Add zoned storage commands of

Re: [PATCH 7/9] hw/isa/vt82c686: QOM'ify ac97 and mc97 creation

On Tue, 23 Aug 2022, Bernhard Beschow wrote: Resolves duplicate code in the boards. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 16 hw/mips/fuloong2e.c | 4 hw/ppc/pegasos2.c | 4 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/isa/vt

Re: [PATCH v13 3/6] target/riscv: Add few cache related PMU events

On Wed, Aug 17, 2022 at 9:24 AM Atish Patra wrote: > > From: Atish Patra > > Qemu can monitor the following cache related PMU events through > tlb_fill functions. > > 1. DTLB load/store miss > 3. ITLB prefetch miss > > Increment the PMU counter in tlb_fill function. > > Reviewed-by: Alistair Fran

Re: [PATCH 1/9] hw/isa/vt82c686: QOM'ify Super I/O creation

On Tue, 23 Aug 2022, Bernhard Beschow wrote: The object creation now happens in chip-specific init methods which allows the realize methods to be consolidated into one method. Shifting the logic into the init methods has the addidional advantage that the parent object's init methods are called im

[PATCH 12/14] target/i386: Use MMU_NESTED_IDX for vmload/vmsave

Use MMU_NESTED_IDX for each memory access, rather than just a single translation to physical. Adjust svm_save_seg and svm_load_seg to pass in mmu_idx. This removes the last use of get_hphys so remove it. Signed-off-by: Richard Henderson --- target/i386/cpu.h| 2 - target/

Re: [PATCH 8/9] hw/isa/vt82c686: QOM'ify RTC creation

On Tue, 23 Aug 2022, Bernhard Beschow wrote: Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 47f2fd2669..ee745d5d49 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c6

[PATCH 07/14] target/i386: Use MMUAccessType across excp_helper.c

Replace int is_write1 and magic numbers with the proper MMUAccessType access_type and enumerators. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/e

[PATCH 08/14] target/i386: Direct call get_hphys from mmu_translate

Use a boolean to control the call to get_hphys instead of passing a null function pointer. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i38

[PATCH 06/14] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA

Allow the target to cache items from the guest page tables. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5e12cc1854..67239b4e5e 100644 --- a/include/exec/cpu-defs.

[PATCH 13/14] target/i386: Combine 5 sets of variables in mmu_translate

We don't need one variable set per translation level, which requires copying into pte/pte_addr for huge pages. Standardize on pte/pte_addr for all levels. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 178 ++- 1 file changed, 91 insertions(+)

[PATCH 05/14] accel/tcg: Introduce tlb_set_page_full

Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Signed-off-by: Richard Henderson --- incl

[PATCH 00/14] target/i386: Use atomic operations for pte updates

This patch set does two things: (1) Remove assert(!probe) from the x86 tlb_fill It turns out that this is a prerequisite for [PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping to non-readable pages because of a new use of probe_access(..., nonfault) when compari

[PATCH 04/14] accel/tcg: Introduce probe_access_full

Add an interface to return the CPUTLBEntryFull struct that goes with the lookup. The result is not intended to be valid across multiple lookups, so the user must use the results immediately. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 11 +++ accel/tcg/cputlb.c |

[PATCH 11/14] target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX

These new mmu indexes will be helpful for improving paging and code throughout the target. Signed-off-by: Richard Henderson --- target/i386/cpu-param.h | 2 +- target/i386/cpu.h| 3 + target/i386/tcg/sysemu/excp_helper.c | 82 ++-- targe

[PATCH 11/22] target/i386: Remove cur_eip, next_eip arguments to gen_repz*

All callers pass s->base.pc_next and s->pc, which we can just as well compute within the functions. Pull out common helpers and reduce the amount of code under macros. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 116 ++-- 1 file changed, 57

[PATCH 03/14] accel/tcg: Suppress auto-invalidate in probe_access_internal

When PAGE_WRITE_INV is set when calling tlb_set_page, we immediately set TLB_INVALID_MASK in order to force tlb_fill to be called on the next lookup. Here in probe_access_internal, we have just called tlb_fill and eliminated true misses, thus the lookup must be valid. This allows us to remove a w

[PATCH 14/14] target/i386: Use atomic operations for pte updates

Use probe_access_full in order to resolve to a host address, which then lets us use a host cmpxchg to update the pte. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/279 Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 242 +++ 1 file ch

[PATCH 09/14] target/i386: Introduce structures for mmu_translate

Create TranslateParams for inputs, TranslateResults for successful outputs, and TranslateFault for error outputs; return true on success. Move stage1 error paths from handle_mmu_fault to x86_cpu_tlb_fill; reorg the rest of handle_mmu_fault into get_physical_address. Signed-off-by: Richard Henders

[PATCH 17/22] target/i386: Use gen_jmp_rel for loop and jecxz insns

With gen_jmp_rel, we may chain to the next tb instead of merely writing to eip and exiting. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 21 ++--- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/tr

[PATCH 12/22] target/i386: Introduce DISAS_JUMP

Drop the unused dest argument to gen_jr(). Remove most of the calls to gen_jr, and use DISAS_JUMP. Remove some unused loads of eip for lcall and ljmp. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-)

[PATCH 01/14] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull

This structure will shortly contain more than just data for accessing MMIO. Rename the 'addr' member to 'xlat_section' to more clearly indicate its purpose. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h| 22 accel/tcg/cputlb.c | 102 +++--

[PATCH 19/22] target/i386: Use gen_jmp_rel for gen_repz*

Subtract cur_insn_len to restart the current insn. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 6d6c751c10..67c803263b 100644 --- a/t

[PATCH 10/14] target/i386: Reorg GET_HPHYS

Replace with PTE_HPHYS for the page table walk, and a direct call to mmu_translate for the final stage2 translation. Hoist the check for HF2_NPT_MASK out to get_physical_address, which avoids the recursive call when stage2 is disabled. We can now return all the way out to x86_cpu_tlb_fill before

[PATCH 16/22] target/i386: Create gen_jmp_rel

Create a common helper for pc-relative branches. The jmp jb insn was missing a mask for CODE32. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 57 ++--- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/target/i386/tcg/translate.c

[PATCH 15/22] target/i386: Use DISAS_TOO_MANY to exit after gen_io_start

We can set is_jmp early, using only one if, and let that be overwritten by gen_repz_* etc. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 42 + 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/target/i386/tcg/translate.c b/ta

[PATCH 02/14] accel/tcg: Drop addr member from SavedIOTLB

This field is only written, not read; remove it. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - accel/tcg/cputlb.c| 7 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..9e47184513 100644 -

[PATCH 20/22] target/i386: Use gen_jmp_rel for DISAS_TOO_MANY

With gen_jmp_rel, we may chain between two translation blocks which may only be separated because of TB size limits. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c i

[PATCH 09/22] target/i386: USe DISAS_EOB_ONLY

Replace lone calls to gen_eob() with the new enumerator. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 73e4330fc0..1dc3ff67ae 100644

[PATCH 22/22] target/i386: Enable TARGET_TB_PCREL

Signed-off-by: Richard Henderson --- target/i386/cpu-param.h | 1 + target/i386/tcg/tcg-cpu.c | 8 ++-- target/i386/tcg/translate.c | 86 ++--- 3 files changed, 77 insertions(+), 18 deletions(-) diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.

[PATCH 14/22] target/i386: Create eip_next_*

Create helpers for loading the address of the next insn. Use tcg_constant_* in adjacent code where convenient. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 44 +++-- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/target/i386/

[PATCH 10/22] target/i386: Create cur_insn_len, cur_insn_len_i32

Create common routines for computing the length of the insn. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1dc3

[PATCH 01/22] target/i386: Return bool from disas_insn

Instead of returning the new pc, which is present in DisasContext, return true if an insn was translated. This is false when we detect a page crossing and must undo the insn under translation. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 42 +++--

[PATCH 21/22] target/i386: Create gen_eip_cur

Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 846040c1ab..6192a3e30e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translat

[PATCH 13/22] target/i386: Truncate values for lcall_real to i32

Use i32 not int or tl for eip and cs arguments. Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 +- target/i386/tcg/seg_helper.c | 6 ++ target/i386/tcg/translate.c | 3 ++- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/i386/helper.h b/target/i3

[PATCH 05/22] target/i386: Create gen_update_eip_next

Sync EIP before exiting a translation block. Replace all gen_jmp_im that use s->pc. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 45 - 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i3

[PATCH v3 17/17] target/arm: Enable TARGET_TB_PCREL

Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 ++ target/arm/translate.h | 6 target/arm/cpu.c | 23 +++--- target/arm/translate-a64.c | 37 ++- target/arm/translate.c | 62 ++ 5 files c

[PATCH 18/22] target/i386: Use gen_jmp_rel for gen_jcc

Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 57 - 1 file changed, 18 insertions(+), 39 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 59e7596629..6d6c751c10 100644 --- a/target/i386/tcg/translat

[PATCH 08/22] target/i386: Use DISAS_EOB_NEXT

Replace sequences of gen_update_cc_op, gen_update_eip_next, and gen_eob with the new is_jmp enumerator. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 40 - 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/target/i386/tcg/tra

[PATCH 04/22] target/i386: Create gen_update_eip_cur

Like gen_update_cc_op, sync EIP before doing something that could raise an exception. Replace all gen_jmp_im that use s->base.pc_next. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 52 - 1 file changed, 28 insertions(+), 24 deletions(-)

[PATCH 03/22] target/i386: Remove cur_eip, next_eip arguments to gen_interrupt

All callers pass s->base.pc_next and s->pc, which we can just as well compute within the function. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/tran

[PATCH 07/22] target/i386: Use DISAS_EOB* in gen_movl_seg_T0

Set is_jmp properly in gen_movl_seg_T0, so that the callers need to nothing special. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 36 +--- 1 file changed, 5 insertions(+), 31 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i38

[PATCH v3 16/17] target/arm: Introduce gen_pc_plus_diff for aarch32

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d13e365e2

[PATCH 02/22] target/i386: Remove cur_eip argument to gen_exception

All callers pass s->base.pc_next - s->cs_base, which we can just as well compute within the function. Note the special case of EXCP_VSYSCALL in which s->cs_base didn't have the subtraction, but cs_base is always zero in 64-bit mode, when vsyscall is used. Signed-off-by: Richard Henderson --- ta

[PATCH 06/22] target/i386: Introduce DISAS_EOB*

Add a few DISAS_TARGET_* aliases to reduce the number of calls to gen_eob() and gen_eob_inhibit_irq(). So far, only update i386_tr_translate_insn for exiting the block because of single-step or previous inhibit irq. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 23 +

[PATCH 00/22] target/i386: pc-relative translation

Based-on: <20220822232338.1727934-1-richard.hender...@linaro.org> ("[PATCH v3 00/17] accel/tcg + target/arm: pc-relative translation") Improve translation with address space randomization. Before: gen code size 232687283/1073577984 TB count434021 TB flush count 1 TB invali

[PATCH v3 12/17] target/arm: Change gen_exception_insn* to work on displacements

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.h| 4 ++-- target/arm/translate-a64.c| 28 +++-- target/arm/translate-m-nocp.c | 6 +++--- target/arm/translate-mve.c| 2 +- ta

[PATCH v3 14/17] target/arm: Change gen_jmp* to work on displacements

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.c | 35 --- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 63a4

[PATCH v3 05/17] include/hw/core: Create struct CPUJumpCache

Wrap the bare TranslationBlock pointer into a structure. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 ++-- accel/tcg/cpu-exec.c | 9 ++--- accel/tcg/cputlb.c| 2 +- accel/tcg/translate-all.c | 4 ++-- 4 files changed, 15 insertions(+), 8 deletions(-)

[PATCH v3 15/17] target/arm: Introduce gen_pc_plus_diff for aarch64

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 41 +++--- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a

[PATCH v3 13/17] target/arm: Change gen_exception_internal to work on displacements

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/

[PATCH v3 03/17] accel/tcg: Use DisasContextBase in plugin_gen_tb_start

Use the pc coming from db->pc_first rather than the TB. Use the cached host_addr rather than re-computing for the first page. We still need a separate lookup for the second page because it won't be computed for DisasContextBase until the translator actually performs a read from the page. Signed-

[PATCH v3 09/17] target/arm: Introduce curr_insn_len

A simple helper to retrieve the length of the current insn. Signed-off-by: Richard Henderson --- target/arm/translate.h | 5 + target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 5 ++--- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.h b/

[PATCH v3 10/17] target/arm: Change gen_goto_tb to work on displacements

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 40 -- target/arm/translate.c | 10 ++ 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target

[PATCH v3 01/17] accel/tcg: Remove PageDesc code_bitmap

This bitmap is created and discarded immediately. We gain nothing by its existence. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 78 ++- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/tr

[PATCH v3 11/17] target/arm: Change gen_*set_pc_im to gen_*update_pc

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values by passing in pc difference. Signed-off-by: Richard Henderson --- target/arm/translate-a32.h | 2 +- target/arm/translate.h | 6 ++-- target/arm/translate-a64.c | 32 +- target/arm/translate-vfp.c | 2 +

[PATCH v3 07/17] accel/tcg: Introduce TARGET_TB_PCREL

Prepare for targets to be able to produce TBs that can run in more than one virtual context. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ include/exec/exec-all.h | 41 ++--- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 55 +++

[PATCH v3 04/17] accel/tcg: Do not align tb->page_addr[0]

Let tb->page_addr[0] contain the offset within the page of the start of the translation block. We need to recover this value anyway at various points, and it is easier to discard the page offset when it's not needed, which happens naturally via the existing find_page shift. Signed-off-by: Richard

[PATCH v3 00/17] accel/tcg + target/arm: pc-relative translation

Based-on: 20220819032615.884847-1-richard.hender...@linaro.org ("[PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping to non-readable pages") v1: https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.hender...@linaro.org/ Just a simple refresh from v2 for the dependenci

[PATCH v3 06/17] accel/tcg: Introduce tb_pc and tb_pc_log

The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++ accel/tcg/cpu-exec.c| 20 - accel/tcg/translate-all.c

[PATCH v3 08/17] accel/tcg: Split log_cpu_exec into inline and slow path

Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3fb7ce05f8..4dc0a9ec41 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -283,12 +283,1

[PATCH v3 02/17] accel/tcg: Use bool for page_find_alloc

Bool is more appropriate type for the alloc parameter. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 34bf296250..a8f1c34c4e 100644 --- a

Re: [PATCH v6 17/21] accel/tcg: Add fast path for translator_ld*

On Thu, 2022-08-18 at 20:26 -0700, Richard Henderson wrote: > Cache the translation from guest to host address, so we may > use direct loads when we hit on the primary translation page. > > Look up the second translation page only once, during translation. > This obviates another lookup of the sec

Re: [PATCH v7 2/8] file-posix: introduce get_sysfs_str_val for device zoned model

On Tue, Aug 16, 2022 at 02:25:16PM +0800, Sam Li wrote: > +static int hdev_get_max_segments(int fd, struct stat *st) { > +int ret; > +if (S_ISCHR(st->st_mode)) { > +if (ioctl(fd, SG_GET_SG_TABLESIZE, &ret) == 0) { The ioctl must be within #ifdef CONFIG_LINUX since SG_GET_SG_TABLESI

[PATCH 6/9] hw/isa/vt82c686: QOM'ify pm creation

Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 9 + hw/mips/fuloong2e.c | 2 +- hw/ppc/pegasos2.c | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index c2f2e0039a..b964d1a760 100644 --- a/hw/isa/vt82c686.c +++ b/hw

[PATCH 2/9] hw/isa/vt82c686: Resolve unneeded attribute

Now that also the super io device is realized in the common realize method, the isa_bus attribute can be turned into a temporary. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/

[PATCH 1/9] hw/isa/vt82c686: QOM'ify Super I/O creation

The object creation now happens in chip-specific init methods which allows the realize methods to be consolidated into one method. Shifting the logic into the init methods has the addidional advantage that the parent object's init methods are called implicitly. Signed-off-by: Bernhard Beschow ---

[PATCH 9/9] hw/isa/vt82c686: Reuse errp

Rather than terminating abruptly, make use of the already present errp and propagate the error to the caller. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index ee745d5d49..15

[PATCH 8/9] hw/isa/vt82c686: QOM'ify RTC creation

Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 47f2fd2669..ee745d5d49 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -546,6 +546,7 @@ struct ViaISAState {

[PATCH 5/6] target/i386: Use tcg gvec for pand, pandn, por, pxor

Signed-off-by: Richard Henderson --- target/i386/ops_sse.h| 5 target/i386/ops_sse_header.h | 5 target/i386/tcg/translate.c | 45 +--- 3 files changed, 37 insertions(+), 18 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse

[PATCH 5/9] hw/isa/vt82c686: QOM'ify vt82c686b-usb-uhci creation

Resolves duplicate code in the boards. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 12 hw/mips/fuloong2e.c | 3 --- hw/ppc/pegasos2.c | 4 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 37d9ed635d..c

[PATCH 7/9] hw/isa/vt82c686: QOM'ify ac97 and mc97 creation

Resolves duplicate code in the boards. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 16 hw/mips/fuloong2e.c | 4 hw/ppc/pegasos2.c | 4 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index b964d1a7

[PATCH 4/9] hw/isa/vt82c686: QOM'ify via-ide creation

The IDE function is closely tied to the ISA function (e.g. the IDE interrupt routing happens there), so it makes sense that the IDE function is instantiated within the southbridge itself. As a side effect, duplicated code in the boards is resolved. Signed-off-by: Bernhard Beschow --- configs/dev

[PATCH 3/9] hw/isa/vt82c686: Prefer pci_address_space() over get_system_memory()

Unlike get_system_memory(), pci_address_space() respects the memory tree available to the parent device. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 9d12e1cae4..5582c0b179 10

[PATCH 3/6] target/i386: Use tcg gvec for pcmp{eq,gt}*

As pcmpeqb is used by strlen et al, this is the highest overhead sse operation, at 2.5%. It's simple to include the other compares at the same time. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h| 8 target/i386/ops_sse_header.h | 8 target/i386/tcg/trans

[PATCH 0/9] QOM'ify VT82xx devices

This series instantiates all PCI functions of the VT82xx southbridges in the southbridges themselves. For the IDE function this is especially important since its interrupt routing is configured in the ISA function, hence doesn't make sense to instantiate it as a "Frankenstein" device. The interr

[PATCH 4/6] target/i386: Use tcg gvec for p{add,sub}*

Since psubb is the second highest overhead sse operation, at 0.9%. It's simple to include add and the other sizes at the same time. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h| 10 - target/i386/ops_sse_header.h | 10 - target/i386/tcg/translate.c | 39 +++

[PATCH 2/6] target/i386: Use tcg gvec for gen_op_movo

Low hanging fruit, using gvec to move 16 bytes. Signed-off-by: Richard Henderson --- target/i386/cpu.h | 4 ++-- target/i386/tcg/translate.c | 7 +++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 81e5abed86..dbc9a99a3b 10

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