On Mon, Sep 12, 2022 at 1:22 AM Kangjie Xu wrote:
>
> A a new command line parameter "queue_reset" is added.
>
> Meanwhile, the vq reset feature is disabled for pre-7.2 machines.
>
> Signed-off-by: Kangjie Xu
> Signed-off-by: Xuan Zhuo
Acked-by: Jason Wang
> ---
> hw/core/machine.c
[AMD Official Use Only - General]
Hi Paul,
Could you help to review this patch?
Thanks
From: Ji, Ruili
Sent: 2022年9月7日 9:04
To: 'Paul Durrant' ; 'qemu-devel@nongnu.org'
Cc: Liu, Aaron ; 'xen-de...@lists.xenproject.org'
Subject: RE: [PATCH] hw/xen: set pci Atomic Ops requests for passthrough
On 9/10/2022 12:25 AM, Peter Xu wrote:
On Wed, Aug 17, 2022 at 10:08:45AM +0800, Chenyi Qiang wrote:
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window
On Mon, Sep 12, 2022 at 02:38:52PM +0200, Cornelia Huck wrote:
> External email: Use caution opening links or attachments
>
>
> On Fri, Sep 09 2022, Nicolin Chen wrote:
>
> > Its caller vfio_connect_container() assigns a default value
> > to info->iova_pgsizes, even if vfio_get_iommu_info()
Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow :
>v5:
>
>* Add patch "Inline vt82c686b_southbridge_init() and remove it" (Zoltan)
>
>* Use machine parameter when creating rtc-time alias (Zoltan)
>
>
>
>Testing done: Same as in v3.
>
>
>
>v4:
>
>* Fix in comment: AC97 Modem -> MC97
Am 12.09.22 um 19:45 schrieb Arwed Meyer:
Am 11.09.22 um 20:27 schrieb Peter Maydell:
On Sun, 11 Sept 2022 at 18:14, Arwed Meyer wrote:
Am 08.09.22 um 23:11 schrieb Peter Maydell:
On Thu, 8 Sept 2022 at 18:43, Arwed Meyer wrote:
Detect mouse reset via RTS or DTR line:
Don't send or
Swtpm may release the lock once the last one of its state blobs has been
migrated out. In case of VM migration failure QEMU now needs to notify
swtpm that it should again take the lock, which it can otherwise only do
once it has received the first TPM command from the VM.
Only try to send the
Ping? This is from April this year, half a year ago.
Can this be applied or?
Marcel said it should wait a week or two, I think that's been done already.. ;)
Thanks,
/mjt
03.04.2022 12:52, Yuval Shaia wrote:
Guest driver might execute HW commands when shared buffers are not yet
allocated.
Swtpm has been extended to release the lock on the storage where its state
is written to upon migration of the last one of its state blobs. Signal
swtpm to again lock the storage upon migration fallback. An explicit signal
helps swtpm to lock the storage earlier because otherwise it would have
to
Use the latest tpm_ioctl.h from upstream swtpm project.
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
---
backends/tpm/tpm_ioctl.h | 96 +++-
1 file changed, 76 insertions(+), 20 deletions(-)
diff --git a/backends/tpm/tpm_ioctl.h
Am 11.09.22 um 20:27 schrieb Peter Maydell:
On Sun, 11 Sept 2022 at 18:14, Arwed Meyer wrote:
Am 08.09.22 um 23:11 schrieb Peter Maydell:
On Thu, 8 Sept 2022 at 18:43, Arwed Meyer wrote:
Detect mouse reset via RTS or DTR line:
Don't send or process anything while in reset.
When coming out
> Thanks for reviewing! Could you send a Pull request? Or do we need an
> ack from someone else?
mst typically includes the vhost-user-blk patches in his PRs. Usually a few
other people review but I'm not sure it's required.
A lot of folks have been busy prepping for KVM Forum the last few
On Mon, Sep 12, 2022 at 07:30:50PM +0300, Nikolay Borisov wrote:
>
>
> On 12.09.22 г. 18:41 ч., Daniel P. Berrangé wrote:
> > On Thu, Sep 08, 2022 at 01:26:32PM +0300, Nikolay Borisov wrote:
> > > This is a prototype of supporting a 'file:' based uri protocol for
> > > writing out the migration
On 12.09.22 г. 18:41 ч., Daniel P. Berrangé wrote:
On Thu, Sep 08, 2022 at 01:26:32PM +0300, Nikolay Borisov wrote:
This is a prototype of supporting a 'file:' based uri protocol for
writing out the migration stream of qemu. Currently the code always
opens the file in DIO mode and adheres to
On Thu, Sep 08, 2022 at 01:26:32PM +0300, Nikolay Borisov wrote:
> This is a prototype of supporting a 'file:' based uri protocol for
> writing out the migration stream of qemu. Currently the code always
> opens the file in DIO mode and adheres to an alignment of 64k to be
> generic enough.
On 9/6/22 07:58, Nico Boehr wrote:
Quoting Pierre Morel (2022-09-02 09:55:23)
[...]
diff --git a/hw/s390x/cpu-topology.c b/hw/s390x/cpu-topology.c
new file mode 100644
index 00..a6ca006ec5
--- /dev/null
+++ b/hw/s390x/cpu-topology.c
[...]
+void s390_topology_new_cpu(int core_id)
+{
On 9/5/22 20:11, Janis Schoetterl-Glausch wrote:
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
In the S390x CPU topology the core_id specifies the CPU address
and the position of the core withing the topology.
Let's build the topology based on the core_id.
Signed-off-by: Pierre
On 9/12/22 00:04, Paolo Bonzini wrote:
@@ -839,6 +910,10 @@ static bool decode_insn(DisasContext *s, CPUX86State *env,
X86DecodeFunc decode_
}
}
if (e->op3 != X86_TYPE_None) {
+/*
+ * A couple instructions actually use the extra immediate byte for an
Lx
+
On 9/12/22 00:04, Paolo Bonzini wrote:
+[0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256
p_00_66), /* MOVNTQ/MOVNTDQ */
Cut and paste comment?
+BINARY_INT_MMX(PMULLW, pmullw)
tcg_gen_gvec_mul
+static void gen_VCVTpd_dq(DisasContext *s, CPUX86State *env,
Thanks for reviewing! Could you send a Pull request? Or do we need an
ack from someone else?
On 9/7/22 7:02 AM, Raphael Norwitz wrote:
Thanks for the changes. For the whole series:
Reviewed-by: Raphael Norwitz
On Tue, Sep 06, 2022 at 10:31:06AM +0300, Daniil Tatianin wrote:
This patch set
I found this version much easier to understand than the previous one.
You could consider splitting up the series into two.
One that introduces support for STSI, PTF, migration, etc.
And a second one that adds support for the maximum-MNist facility and
drawers and books.
This would also make
On 9/12/22 00:04, Paolo Bonzini wrote:
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were
On 9/12/22 00:04, Paolo Bonzini wrote:
+static void gen_MOVD_from(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+MemOp ot = decode->op[2].ot;
+int lo_ofs = decode->op[2].offset
+- xmm_offset(decode->op[2].ot)
++ xmm_offset(ot);
+
+switch (ot) {
+
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
> Add some basic examples for the definition of cpu topology
> in s390x.
>
> Signed-off-by: Pierre Morel
> ---
> docs/system/s390x/cpu_topology.rst | 88 ++
> 1 file changed, 88 insertions(+)
> create mode
On 9/12/22 00:04, Paolo Bonzini wrote:
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX. must be b), and 3 operands
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
> Add some basic examples for the definition of cpu topology
> in s390x.
>
> Signed-off-by: Pierre Morel
> ---
> docs/system/s390x/cpu_topology.rst | 88 ++
> 1 file changed, 88 insertions(+)
> create mode
Now that everything has been converted to C code the nanomips.cpp file
has been renamed. Therefore, meson.build file is also changed.
Signed-off-by: Milica Lazarevic
---
disas/meson.build | 2 +-
disas/{nanomips.cpp => nanomips.c} | 0
2 files changed, 1 insertion(+), 1
On 9/12/22 00:04, Paolo Bonzini wrote:
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -290,6 +290,20 @@ BINARY_INT_MMX(PUNPCKHWD, punpckhwd)
BINARY_INT_MMX(PUNPCKHDQ, punpckhdq)
BINARY_INT_MMX(PACKSSDW, packssdw)
+BINARY_INT_MMX(PSUBUSB, psubusb)
Disassemble function that calls the other variant of it is deleted.
Where it is called, now we're directly calling the other implementation.
Signed-off-by: Milica Lazarevic
---
disas/nanomips.cpp | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/disas/nanomips.cpp
On 9/12/22 00:04, Paolo Bonzini wrote:
+static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
+{
+if (s->prefix & PREFIX_REPNZ) {
+entry->gen = NULL;
Are these lines really required with the p_00_66_f3 spec on the group entry?
+} else if
On Fri, Sep 09 2022, Nicolin Chen wrote:
> Its caller vfio_connect_container() assigns a default value
> to info->iova_pgsizes, even if vfio_get_iommu_info() fails.
> This would result in a "Segmentation fault" error, when the
> VFIO_IOMMU_GET_INFO ioctl errors out.
>
> Since the caller has
is a C++ library and it's not used by disassembler.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
disas/nanomips.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
index 7fed1abff0..e3c5c51db1 100644
Replaced argument passing by reference with passing by address.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
disas/nanomips.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
Header file nanomips.h has been deleted for the nanomips disassembler to
stay consistent with the rest of the disassemblers which don't include
extra header files.
Signed-off-by: Milica Lazarevic
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
disas/nanomips.h | 26
Change enums to typedef enums to keep naming clear.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
disas/nanomips.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
index
Hi,
This patchset converts the nanomips disassembler to plain C. C++ features
like class, std::string type, exception handling, and function overloading
have been removed and replaced with the equivalent C code.
===
Changes since previous version:
(3) disas/nanomips: Delete NMD class
Since there's no support for exception handling in C, the try-catch
blocks have been deleted, and throw clauses are replaced. When a runtime
error happens, we're printing out the error message. Disassembling of
the current instruction interrupts. This behavior is achieved by adding
sigsetjmp() to
NMD class has been deleted. The following methods are now declared as
static functions:
- public NMD::Disassemble method
- private NMD::Disassemble method
- private NMD::extract_op_code_value helper method
Also, the implementation of the print_insn_nanomips function and
nanomips_dis function is
CPR functions has been removed.
Before this patch, we'd been calling img_format twice, the first time
through the CPR function to get an appropriate string and the second
time to print that formatted string. There's no more need for that.
Therefore, calls to CPR are removed, and now we're
g_autofree attribute is added for every dynamically allocated string to
prevent memory leaking.
The implementation of the several functions that work with dynamically
allocated strings is slightly changed so we can add those attributes.
Signed-off-by: Milica Lazarevic
---
disas/nanomips.cpp |
Both versions of IMMEDIATE functions have been removed.
Before this patch, we'd been calling img_format twice, the first time
through the IMMEDIATE to get an appropriate string and the second time
to print that string. There's no more need for that. Therefore, calls to
IMMEDIATE are removed, and
Pool tables are no longer declared as static fields of the NMD
class but as global static const variables. Pool struct is defined
outside of the class.
The NMD::Disassemble method is using the MAJOR Pool table variable, so
its implementation is moved to the end of the nanomips.cpp file,
right
The m_requested_instruction_categories field always has the same value,
ALL_ATTRIBUTES. The only use of that field is within the if statement.
When replaced with a specific value, the if statement is always false,
so it has been removed.
Now, when the only use of the
NMD class methods with the conditional_function type like
NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD
class. They're now declared global static functions. Therefore, typedef
of the function pointer, conditional_function is defined outside of the
class.
Now that
Helper methods from NMD class like NMD::renumber_registers,
NMD::decode_gpr_gpr4... etc. are removed from the class. They're now
declared global static functions.
Following helper methods have been deleted because they're not used by
the nanomips disassembler:
-
Following functions just wrap the decode_gpr_gpr3() function:
- encode_rs3_and_check_rs3_ge_rt3()
- encode_rs3_and_check_rs3_lt_rt3()
Therefore those have been deleted. Calls to these two functions have
been replaced with calls to decode_gpr_gpr3.
Signed-off-by: Milica Lazarevic
---
The following is moved from the nanomips.h to nanomips.cpp file:
- #include line
- typedefs
- enums
- definition of the Pool struct.
Header file nanomips.h will be deleted to be consistent with the rest of
the disas/ code.
Signed-off-by: Milica Lazarevic
Reviewed-by: Philippe Mathieu-Daudé
Definitions of enums TABLE_ENTRY_TYPE and TABLE_ATTRIBUTE_TYPE are moved
out of the NMD class. The main goal is to remove NMD class completely.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
disas/nanomips.cpp | 8 +++
disas/nanomips.h | 59
On 06/09/2022 16:52, Daniel Henrique Barboza wrote:
Lucas,
If you're still interested, patches 1-4 are worth re-sending in separate.
You'll need to address Daniel's comments on patch 1. The other 3 patches
LGTM.
Patches 5-8 can wait. We're not certain about Unicamp's Minicloud
availability
On 9/12/22 00:04, Paolo Bonzini wrote:
+/*
+ * 00 = p* Pq, Qq (if mmx not NULL; no VEX)
+ * 66 = vp* Vx, Hx, Wx
+ *
+ * These are really the same encoding, because 1) V is the same as P when VEX.V
+ * is not present 2) P and Q are the same as H and W apart from MM/XMM
+ */
+static inline void
From: Philippe Mathieu-Daudé
The '1' magic value means 'Port B'. Introduce and use the
gpio_port_index() helper to explicit the port name.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210313165445.2113938-10-f4...@amsat.org>
Reviewed-by: Michael Rolnik
Signed-off-by: Heecheol Yang
Add some of these features for AVR GPIO:
- GPIO I/O : PORTx registers
- Data Direction : DDRx registers
- DDRx toggling : PINx registers
Following things are not supported yet:
- MCUR registers
Signed-off-by: Heecheol Yang
Reviewed-by: Michael Rolnik
Message-Id:
[PMD: Use
From: G S Niteesh Babu
Added tracing for gpio read, write, and update output irq.
1) trace_avr_gpio_update_ouput_irq
2) trace_avr_gpio_read
3) trace_avr_gpio_write
Signed-off-by: G S Niteesh Babu
Reviewed-by: Michael Rolnik
Message-Id: <20210311135539.10206-3-niteesh...@gmail.com>
[PMD:
From: G S Niteesh Babu
Signed-off-by: G S Niteesh Babu
Reviewed-by: Michael Rolnik
Message-Id: <20210311135539.10206-4-niteesh...@gmail.com>
[PMD: Added ArduinoMachineClass::d13_led_portb_bit]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210313165445.2113938-9-f4...@amsat.org>
On 9/12/22 00:03, Paolo Bonzini wrote:
The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done. We just need to
build them.
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 ++
target/i386/ops_sse.h
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210313165445.2113938-7-f4...@amsat.org>
Reviewed-by: Michael Rolnik
Signed-off-by: Heecheol Yang
---
hw/gpio/avr_gpio.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git
Signed-off-by: Heecheol Yang
---
hw/gpio/avr_gpio.c | 16
include/hw/gpio/avr_gpio.h | 15 +++
2 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
index 29252d6ccf..7613ca6493 100644
--- a/hw/gpio/avr_gpio.c
On 9/12/22 00:03, Paolo Bonzini wrote:
The new implementation of SSE will cover AVX from the get go, so include
the 24 extra comparison operators that are only available with the VEX
prefix.
Based on a patch by Paul Brook.
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 38
On 9/12/22 00:03, Paolo Bonzini wrote:
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
helpers to provide this functionality.
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h |
From: Philippe Mathieu-Daudé
AVR MCU have various GPIO ports. Add an 'id' property to distinct
all instances.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210313165445.2113938-6-f4...@amsat.org>
Reviewed-by: Michael Rolnik
Signed-off-by: Heecheol Yang
---
hw/avr/atmega.c
On 9/12/22 00:03, Paolo Bonzini wrote:
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
old SSE decoder to be compatible with new-style helpers.
The affected instructions are CVTSx2Sx,
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210313165445.2113938-5-f4...@amsat.org>
Reviewed-by: Michael Rolnik
Signed-off-by: Heecheol Yang
---
hw/gpio/avr_gpio.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/gpio/avr_gpio.c
On 9/12/22 00:03, Paolo Bonzini wrote:
Add to the helpers all the operands that are needed to implement AVX.
Extracted from a patch by Paul Brook.
Message-Id:<20220424220204.2493824-26-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 173
On 9/12/22 00:03, Paolo Bonzini wrote:
This is all dead code, since the VEX prefix goes straight to the new decoder.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 243
1 file changed, 243 deletions(-)
Could be squashed with previous,
On 9/12/22 00:03, Paolo Bonzini wrote:
From: Paul Brook
Adjust all #ifdefs to match the ones in ops_sse.h.
Signed-off-by: Paul Brook
Message-Id:<20220424220204.2493824-23-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse_header.h | 114 +++
On 9/12/22 00:03, Paolo Bonzini wrote:
Because these are the only VEX instructions that QEMU supports, the
new decoder is entered on the first byte of a valid VEX prefix, and VEX
decoding only needs to be done in decode-new.c.inc.
Signed-off-by: Paolo Bonzini
---
On 9/12/22 00:03, Paolo Bonzini wrote:
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc
On 9/12/22 00:03, Paolo Bonzini wrote:
+/* five rows for no prefix, 66, F3, F2, 66+F2 */
+static X86OpEntry opcodes_0F38_F0toFF[16][5] = {
const.
r~
On 9/12/22 00:03, Paolo Bonzini wrote:
@@ -180,6 +210,8 @@ struct X86OpEntry {
X86InsnSpecial special : 8;
X86CPUIDFeature cpuid : 8;
+uint8_t vex_class : 8;
Since uint8_t expands to 'unsigned char', it's friendlier to use 'unsigned' with
bitfields, so that gdb
From: Marc-André Lureau
In order to reset the guest agent, we send CLOSED & OPENED events.
They are correctly received by the guest kernel. However, they might not
be noticed by the guest agent process, as the IO task (poll() for
example) might be wake up after both CLOSED & OPENED have been
On 9/12/22 00:03, Paolo Bonzini wrote:
@@ -102,6 +107,25 @@ static void gen_load_sse(DisasContext *s, TCGv temp, MemOp
ot, int dest_ofs)
+static inline bool sse_needs_alignment(DisasContext *s, X86DecodedInsn
*decode, X86DecodedOp *op)
+{
Drop inline. You may require adding G_GNUC_UNUSED
From: Marc-André Lureau
The guest agent doesn't know what is the current serial state. Reset the
serial value whenever a new agent connection is established.
Fixes:
https://bugzilla.redhat.com/show_bug.cgi?id=2124446
Signed-off-by: Marc-André Lureau
---
ui/vdagent.c | 4 +++-
1 file changed,
From: Marc-André Lureau
Not only we have to reset the vdagent clipboards serial state, but also
the current QEMU clipboards info serial (the value is currently used by
qemu_clipboard_check_serial, only used by -display dbus).
Signed-off-by: Marc-André Lureau
---
ui/clipboard.c | 7 +++
1
From: Marc-André Lureau
This helps debugging clipboard serial sync issues.
Signed-off-by: Marc-André Lureau
---
ui/clipboard.c | 11 +--
ui/vdagent.c| 3 +++
ui/trace-events | 5 +
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/ui/clipboard.c
From: Marc-André Lureau
Hi,
The Spice vdagent serial handling has a few flaws when the guest agent is
restarted, or when the dbus client is restarted. The clipboard serials are not
in sync between agent, qemu and client. This series fixes various reset issues.
Fixes:
From: Marc-André Lureau
The incoming grab event should have a higher serial.
See also "vdagent: introduce VD_AGENT_CAP_CLIPBOARD_GRAB_SERIAL":
https://gitlab.freedesktop.org/spice/spice-protocol/-/commit/045a6978d6dbbf7046affc5c321fa8177c8cce56
This is only a relevant fix for the -display dbus,
On 9/12/22 00:03, Paolo Bonzini wrote:
From: Paul Brook
Add a new hflag bit to determine whether AVX instructions are allowed
Signed-off-by: Paul Brook
Message-Id:<20220424220204.2493824-4-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 3 +++
On 9/12/22 00:03, Paolo Bonzini wrote:
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/12/22 00:03, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 51
target/i386/tcg/decode-new.h | 20 +
2 files changed, 71 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc
On 9/12/22 00:03, Paolo Bonzini wrote:
Add generic code generation that takes care of preparing operands
around calls to decode.e.gen in a table-driven manner, so that ALU
operations need not take care of that.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 20 +++-
On 9/12/22 00:03, Paolo Bonzini wrote:
+case X86_TYPE_B: /* VEX. selects a GPR */
+op->unit = X86_OP_INT;
+op->n = s->vex_v;
+break;
Could use a comment for where missing vex prefix is diagnosed.
I guess it's one of the "vexN" group markers in the insn table?
Hi
On Mon, Sep 12, 2022 at 12:58 PM Antonio Caggiano <
antonio.caggi...@collabora.com> wrote:
> Hi Marc-André,
>
> On 30/08/2022 13:07, Marc-André Lureau wrote:
> > Hi
> >
> > On Mon, Aug 29, 2022 at 7:46 PM Antonio Caggiano
> > mailto:antonio.caggi...@collabora.com>>
>
> > wrote:
> >
> >
Hi Marc-André,
On 30/08/2022 13:07, Marc-André Lureau wrote:
Hi
On Mon, Aug 29, 2022 at 7:46 PM Antonio Caggiano
mailto:antonio.caggi...@collabora.com>>
wrote:
Add shared memory and support blob resource creation, mapping and
unmapping through virglrenderer new stable APIs[0] when
Copying in the two migration maintainers.
On Wed, Aug 10, 2022 at 01:39:42PM +0300, Nikolay Borisov wrote:
> All pages which are going to be migrated are first added to
> MultiFDSendParams::MultiFDPages_t::offset array by the main migration
> thread and are subsequently copied to
On Fri, 09 Sep 2022 22:02:34 +0800
Robert Hoo wrote:
> On Fri, 2022-09-09 at 15:39 +0200, Igor Mammedov wrote:
> > On Thu, 1 Sep 2022 11:27:20 +0800
> > Robert Hoo wrote:
> >
> > > Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W},
> > > which
> > > deprecates corresponding
On 9/12/22 00:03, Paolo Bonzini wrote:
The "O" operand type in the Intel SDM needs to load an 8- to 64-bit
unsigned value, while insn_get is limited to 32 bits. Extract the code
out of disas_insn and into a separate function.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 36
On 9/12/22 00:03, Paolo Bonzini wrote:
The later prefix wins if both are present, make it show in s->prefix too.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/12/22 00:03, Paolo Bonzini wrote:
ldq takes a pointer to the first byte to load the 64-bit word in;
ldo takes a pointer to the first byte of the ZMMReg. Make them
consistent, which will be useful in the new SSE decoder's
load/writeback routines.
Signed-off-by: Paolo Bonzini
---
On 9/11/22 23:26, Paolo Bonzini wrote:
Do not set all the flags, they are untouched other than ZF.
Um, no, second sentence:
# The ZF flag is set if the values in the destination operand and register
# AL, AX, or EAX are equal; otherwise it is
cleared. The CF, PF, AF, SF,
# and OF flags are
On 9/11/22 23:26, Paolo Bonzini wrote:
+/* Compute the result of writing t0 to the OT-sized register REG.
+ *
+ * If DEST is NULL, store the result into the register and return the
+ * register's TCGv.
+ *
+ * If DEST is not NULL, store the result into DEST and return the
+ * register's TCGv.
+
Gentle ping -- is there anything blocking this patch from going in?
It's been about a month now since I sent it, and it's not very big, so I
was hoping it would merge without much difficulty.
If it's breaking a test or something then I'd be happy to take a look
and send a new revision.
On Mon,
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