Alberto Faria writes:
> The nvme-io_uring driver expects a character special file such as
> /dev/ng0n1. Follow the convention of having a "filename" option when a
> regular file is expected, and a "path" option otherwise.
I suspect this is by accident, not by design. Is it desirable?
> This ma
Hi Oleksandr,
On 10/28/22 1:26 PM, Oleksandr Tyshchenko wrote:
On Thu, Oct 27, 2022 at 12:24 PM Alex Bennée
wrote:
Hello all
Vikram Garhwal writes:
> xenstore_record_dm_state() will also be used in aarch64 xenpv
machine.
>
> Signed-off-by: Vikram Garhwal
> Sig
On Thu, Oct 27, 2022 at 12:24 PM Alex Bennée wrote:
Hello all
> Vikram Garhwal writes:
>
> > xenstore_record_dm_state() will also be used in aarch64 xenpv machine.
> >
> > Signed-off-by: Vikram Garhwal
> > Signed-off-by: Stefano Stabellini
> > ---
> > accel/xen/xen-all.c | 2 +-
> > inclu
On Fri, Oct 28, 2022 at 8:58 PM Julien Grall wrote:
> Hi,
>
Hello all.
[sorry for the possible format issues]
>
> On 27/10/2022 09:02, Alex Bennée wrote:
> >
> > Vikram Garhwal writes:
> >
> >
> >> Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device,
> adds a
> >> TPM em
Thanks, Alex, for reviewing this one. I built for all the archs and it was
fine. Can you please share more about what environment builds are breaking? So,
I can test the changes for v2.
Regards,
Vikram
From: Alex Bennée
Date: Thursday, October 27, 2022 at 2:24 AM
To: Garhwal, Vikram
Cc: qemu-
在 2022/10/21 下午5:28, yangxiaojuan 写道:
在 2022/10/21 下午5:11, Philippe Mathieu-Daudé 写道:
On 21/10/22 03:53, Xiaojuan Yang wrote:
1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' req
在 2022/10/28 上午9:40, Xiaojuan Yang 写道:
Add new items into LoongArch FDT, including rtc and uart info.
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/virt.c| 31 +++
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 32 insertions(+)
Reviewed-by: Song G
在 2022/10/28 上午9:40, Xiaojuan Yang 写道:
Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/virt.c | 18 +++---
i
在 2022/10/28 上午9:40, Xiaojuan Yang 写道:
Add TPM device for LoongArch virt machine, including
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
to dynamic_sysbus_devices list.
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/acpi-build.c | 50 +--
hw/loonga
Am 22.04.22 um 09:01 schrieb Stefan Weil:
At least the 1st two patches could also be applied via qemu-trivial.
One of them missed release 7.0, so hopefully the fixes will be
included in the next QEMU release.
Stefan W.
[PATCH 1/3] libvhost-user: Fix wrong type of argument to formatting
[PATCH 2
This is a ping to the patch below.
https://patchew.org/QEMU/ty0pr0101mb4285f637209075c9f65fcda6a4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
https://lore.kernel.org/qemu-devel/ty0pr0101mb4285f637209075c9f65fcda6a4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
Before this commit, ther
Hi all,
I was trying to build a MIPS VirtIO board[1] for QEMU that is able
to work with all processors we support.
When I was bring up varoius CPUs on that board I noticed some issues
with the system emulation code that I'm fixing in this series.
Thanks.
- Jiaxun
[1]: https://gitlab.com/FlyGoat
As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
should is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
---
target/mips/cpu.c | 6 ++
1 file changed, 6
I don't have access to Octeon68XX hardware but accroading to
my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 p
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/octeon_translate.c | 2 +-
1 file changed, 1 inse
在 2022-10-29星期六的 06:28 +1100，Richard Henderson写道：
> On 10/28/22 18:21, Icenowy Zheng wrote:
> > When registering helpers via FFI for TCI, the inner loop that
> > iterates
> > parameters of the helper reuses (and thus pollutes) the same
> > variable
> > used by the outer loop that iterates all helpe
On Fri, Oct 28, 2022 at 03:54:49PM +0800, Cindy Lu wrote:
> To support configure interrupt for vhost-vdpa
> Introduce VIRTIO_CONFIG_IRQ_IDX -1 as configure interrupt's queue index,
> Then we can reuse the functions guest_notifier_mask and
> guest_notifier_pending.
> Add the check of queue index in
The nvme-io_uring driver expects a character special file such as
/dev/ng0n1. Follow the convention of having a "filename" option when a
regular file is expected, and a "path" option otherwise.
This makes io_uring the only libblkio-based driver with a "filename"
option, as it accepts a regular fil
On 28/10/22 18:02, Eugenio Pérez wrote:
This causes errors on virtio modern devices on big endian hosts
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-shadow-virtqueue.c
b/hw/virtio/vh
On 28/10/22 18:02, Eugenio Pérez wrote:
This causes errors on virtio modern devices on big endian hosts
Fixes: 01f8beacea2a ("vhost: toggle device callbacks using used event idx")
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 de
On 28/10/22 18:02, Eugenio Pérez wrote:
The used event is already an uint16_t pointer
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 28/10/22 17:09, Daniel Henrique Barboza wrote:
Bernhard,
The 32 builds aren't fancying this patch. The issue is down there:
On 10/18/22 18:01, Bernhard Beschow wrote:
Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory regi
On 28/10/22 14:26, Akihiko Odaki wrote:
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the
On 10/28/22 16:22, Eric Farman wrote:
On Thu, 2022-10-27 at 23:23 +0200, Peter Jin wrote:
Revert the control and flag bits in the subchannel status word in
case
the SSCH operation fails with non-zero CC (ditto for CSCH and HSCH).
According to POPS, the control and flag bits are only changed if
' of https://gitlab.com/marcandre.lureau/qemu
into staging (2022-10-26 10:53:49 -0400)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20221028
for you to fetch changes up to 1a4ef9d45dbe6be588735a989e8ed3764a2fcf49:
hw/ppc/e500: Implement
On Thu, 2022-10-27 at 23:23 +0200, Peter Jin wrote:
> Revert the control and flag bits in the subchannel status word in
> case
> the SSCH operation fails with non-zero CC (ditto for CSCH and HSCH).
> According to POPS, the control and flag bits are only changed if
> SSCH,
> CSCH, and HSCH return CC
On 10/28/22 15:36, Leandro Lupori wrote:
Commit 47e83d9107 ended up unintentionally changing the control flow
of ppc_radix64_process_scoped_xlate(). When guest_visible is false,
it must not raise an exception, even if the radix configuration is
not valid.
This regression prevented Linux boot
The following series fixes an issue with guest RPCIT processing discovered
during development of [1] as well as proposes a few additional optimizations
to the current RPCIT codepath.
[1]
https://lore.kernel.org/linux-s390/20221019144435.369902-1-schne...@linux.ibm.com/
Matthew Rosato (3):
s390
Currently, each unmapped page is handled as an individual iommu
region notification. Attempt to group contiguous unmap operations
into fewer notifications to reduce overhead.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-inst.c | 51
1 file changed
If we encounter a new mapping while the number of available DMA entries
in vfio is 0, we are currently skipping that mapping which is a problem
if we manage to free up DMA space after that within the same RPCIT --
we will return to the guest with CC0 and have not mapped everything
within the specif
Currently, s390x-pci performs accounting against the vfio DMA
limit and triggers the guest to clean up mappings when the limit
is reached. Let's go a step further and also limit the size of
the supported DMA aperture reported to the guest based upon the
initial vfio DMA limit reported for the conta
On 10/29/22 00:40, Peter Maydell wrote:
Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
On 10/29/22 00:40, Peter Maydell wrote:
For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
their AArch32 equivalents). This is a subset of the registers
trapped by HCR_EL2.TID2, which includes all of these and also
On 10/29/22 00:40, Peter Maydell wrote:
For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
and IC IALLUIS cache maintenance instructions.
The HCR_EL2.TOCU bit traps all the other cache maintenance
instructions that operate to the point of unification:
AArch64 IC IVAU, IC IALL
On 10/29/22 00:39, Peter Maydell wrote:
For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
use of TLB maintenance instructions that operate on the
outer shareable domain:
TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
T
On 10/29/22 00:39, Peter Maydell wrote:
For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
TLB maintenance instructions that operate on the inner shareable
domain:
AArch64:
TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TL
On 10/29/22 00:39, Peter Maydell wrote:
+if (cpu_isar_feature(any_half_evt, cpu)) {
+valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
+}
+if (cpu_isar_feature(any_evt, cpu)) {
+valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU |
HCR_TID4;
+}
You don't n
On 10/29/22 00:39, Peter Maydell wrote:
The HCR_EL2.TTLB bit is supposed to trap all EL1 execution of TLB
maintenance instructions. However we have added new TLB insns for
FEAT_TLBIOS and FEAT_TLBIRANGE, and forgot to set their accessfn to
access_ttlb. Add the missing accessfns.
Signed-off-by:
On 10/28/22 18:21, Icenowy Zheng wrote:
When registering helpers via FFI for TCI, the inner loop that iterates
parameters of the helper reuses (and thus pollutes) the same variable
used by the outer loop that iterates all helpers, thus made some helpers
unregistered.
Fix this logic error by usin
On Sat, 29 Oct 2022 01:12:11 +0900
Akihiko Odaki wrote:
> On 2022/10/28 23:16, Alex Williamson wrote:
> > On Fri, 28 Oct 2022 21:26:13 +0900
> > Akihiko Odaki wrote:
> >
> >> vfio_add_std_cap() is designed to ensure that capabilities do not
> >> overlap, but it failed to do so for MSI and MSI
These patches aim to solve two types of DMA-reentrancy issues:
1.) mmio -> dma -> mmio case
To solve this, we track whether the device is engaged in io by
checking/setting a flag within APIs used for MMIO access.
2.) bh -> dma write -> mmio case
This case is trickier, since we dont have a generic
Add transitionary DMA APIs which associate accesses with the device
initiating them. The modified APIs maintain a "MemReentrancyGuard" in
the DeviceState, which is used to prevent DMA re-entrancy issues.
The MemReentrancyGuard is set/checked when entering IO handlers and when
initiating a DMA acces
Signed-off-by: Alexander Bulekov
---
hw/usb/hcd-xhci.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 8299f35e66..2621dde7ea 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -494,7 +494,7 @@ stati
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/541
Signed-off-by: Alexander Bulekov
---
hw/usb/libhw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/usb/libhw.c b/hw/usb/libhw.c
index f350eae443..a15e97f76d 100644
--- a/hw/usb/libhw.c
+++ b/hw/usb/libhw.c
@@ -36
Signed-off-by: Alexander Bulekov
---
hw/usb/hcd-ehci.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index d4da8dcb8d..b93f4d44c1 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -383,8 +383,8 @@ static inline int get_dw
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/62
Signed-off-by: Alexander Bulekov
---
hw/ide/ahci.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 7ce001cacd..ffa817eebe 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1282
Signed-off-by: Alexander Bulekov
---
hw/sd/sdhci.c | 43 +++
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 0e5e988927..0ebbc13862 100644
--- a/hw
Signed-off-by: Alexander Bulekov
---
softmmu/dma-helpers.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c
index 7820fec54c..ba2ad23324 100644
--- a/softmmu/dma-helpers.c
+++ b/softmmu/dma-helpers.c
@@ -90,9 +90,9 @
On 10/28/22 23:42, Ilya Leoshkevich wrote:
munmap() flushes jump cache on all CPUs if the unmapped range contains
a translation block. This currently includes new CPUs (i.e. qemu-user
threads), for which there is no jump cache yet, which leads to a null
pointer dereference.
Fix by skipping new C
On 28/10/2022 15:36, Leandro Lupori wrote:
Commit 47e83d9107 ended up unintentionally changing the control flow
of ppc_radix64_process_scoped_xlate(). When guest_visible is false,
it must not raise an exception, even if the radix configuration is
not valid.
This regression prevented Linux boot i
On 10/28/22 20:16, Claudio Fontana wrote:
On 10/27/22 12:02, Richard Henderson wrote:
Since we do not plan to exit, use cpu_unwind_state_data
and extract exactly the data requested.
Signed-off-by: Richard Henderson
---
target/openrisc/sys_helper.c | 11 +--
1 file changed, 9 inserti
Commit 47e83d9107 ended up unintentionally changing the control flow
of ppc_radix64_process_scoped_xlate(). When guest_visible is false,
it must not raise an exception, even if the radix configuration is
not valid.
This regression prevented Linux boot in a nested environment with
L1 using TCG and
On Thu, 27 Oct 2022 at 12:26, Timofey Kutergin wrote:
>
> - Use CPSR.PAN to check for PAN state in aarch32 mode
> - throw permission fault during address translation when PAN is
> enabled and kernel tries to access user acessible page
> - ignore SCTLR_XP bit for armv7 and armv8 (
On Wed, 26 Oct 2022 at 01:30, Gavin Shan wrote:
>
> Hi Peter and Marc,
>
> On 10/24/22 11:54 AM, Gavin Shan wrote:
> > There are three high memory regions, which are VIRT_HIGH_REDIST2,
> > VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
> > are floating on highest RAM address. Ho
Hi,
On 27/10/2022 09:02, Alex Bennée wrote:
Vikram Garhwal writes:
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functionalities for a guest domain.
Extra command
The following changes since commit 344744e148e6e865f5a57e745b02a87e5ea534ad:
Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2022-10-26 10:53:49 -0400)
are available in the Git repository at:
ssh://g...@github.com/qemu-bsd-user/qemu-bsd-user.git
tags
From: Muhammad Moinur Rahman
Some versions of FreeBSD now require sys/param.h for machine/pmap.h on
x86. Include them here to meet that requirement. It does no harm on
older versions, so there's no need to #ifdef it.
Signed-off-by: Muhammad Moinur Rahman
Reviewed-by:John Baldwin
Signed-of
Hi Jason,
This one is a one-line simple bug fix but seems to be missed from the
pull request. If there's a v2 for the PULL, would appreciate if you can
piggyback. Thanks in advance!
Regards,
-Siwei
On 10/7/2022 8:42 AM, Eugenio Perez Martin wrote:
On Tue, Oct 4, 2022 at 11:05 PM Si-Wei Liu
From: Hyman Huang(黄勇)
Abstract vhost acked features saving into
vhost_user_save_acked_features, export it as util function.
Signed-off-by: Hyman Huang(黄勇)
Signed-off-by: Guoyi Tu
---
include/net/vhost-user.h | 2 ++
net/vhost-user.c | 35 +++
2 files c
From: Hyman Huang(黄勇)
Save the acked_features once it be configured by guest
virtio driver so it can't miss any features.
Signed-off-by: Hyman Huang(黄勇)
Signed-off-by: Guoyi Tu
---
hw/net/vhost_net.c | 9 +
hw/net/virtio-net.c | 5 +
include/net/vhost_net.h | 2 ++
3 file
From: Hyman Huang(黄勇)
v2:
Fix the typo in subject of [PATCH v2 2/2]
v1:
This is the version 1 of the series and it is exactly the same as
RFC version, but fixing a typo in subject, which is reported by Michael.
As for test for the behavior suggested by Michael, IMHO, it could be
post in anoth
From: Hyman Huang(黄勇)
Save the acked_features once it be configured by guest
virtio driver so it can't miss any features.
Signed-off-by: Hyman Huang(黄勇)
Signed-off-by: Guoyi Tu
---
hw/net/vhost_net.c | 9 +
hw/net/virtio-net.c | 5 +
include/net/vhost_net.h | 2 ++
3 file
From: Hyman Huang(黄勇)
Abstract vhost acked features saving into
vhost_user_save_acked_features, export it as util function.
Signed-off-by: Hyman Huang(黄勇)
Signed-off-by: Guoyi Tu
---
include/net/vhost-user.h | 2 ++
net/vhost-user.c | 35 +++
2 files c
From: Hyman Huang(黄勇)
v1:
This is the version 1 of the series and it is exactly the same as
RFC version, but fixing a typo in subject, which is reported by Michael.
As for test for the behavior suggested by Michael, IMHO, it could be
post in another series, since i found that testing the negoti
From: Matheus Ferst
Move the interrupt masking logic out of cpu_has_work_POWER8 in a new
method, p8_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.16411
On Fri, Oct 28, 2022 at 9:45 PM B wrote:
>
>
>
> Am 28. Oktober 2022 10:58:07 UTC schrieb Ani Sinha :
> >On Fri, Oct 28, 2022 at 4:05 PM Bernhard Beschow wrote:
> >>
> >> The code currently assumes Q35 iff ICH9 and i440fx iff PIIX. Now that more
> >> AML generation has been moved into the south b
From: Matheus Ferst
Remove the following unused interrupts from the POWER7 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Hypervisor Doorbell and Event-Based Branch: introduced in
Power ISA
From: Matheus Ferst
Split ppc_hw_interrupt into an interrupt masking method,
ppc_next_unmasked_interrupt, and an interrupt processing method,
ppc_deliver_interrupt.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-4-matheus.fe...@eldorado.org.br>
Sign
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-10-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/tar
From: Matheus Ferst
This new method will check if any pending interrupt was unmasked and
then call cpu_interrupt/cpu_reset_interrupt accordingly. Code that
raises/lowers or masks/unmasks interrupts should call this method to
keep CPU_INTERRUPT_HARD coherent with env->pending_interrupts.
Signed-o
From: BALATON Zoltan
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<04bb3445439c2f37b99e74b3fdf4e62c2e6f7e04.1666194485.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique
From: Leandro Lupori
Add 2 new PMC related HFLAGS:
- HFLAGS_PMCJCE - value of MMCR0 PMCjCE bit
- HFLAGS_PMC_OTHER - set if a PMC other than PMC5-6 is enabled
These flags allow further optimization of PMC5 update code, by
allowing frequently tested conditions to be performed at
translation time.
From: Matheus Ferst
Move the methods to excp_helper.c and make them static.
Reviewed-by: Fabiano Rosas
Signed-off-by: Matheus Ferst
Message-Id: <20221021142156.4134411-4-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c| 102 -
From: BALATON Zoltan
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-Id:
<3ea98072dbeb757942e25dcfcdd6a7a47738d2ca.1666194485.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc4xx_devs.c | 352
hw
From: BALATON Zoltan
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Sign
From: Matheus Ferst
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-22-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel
From: BALATON Zoltan
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mat
From: Bernhard Beschow
Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory region.
Note that the flash memory area is only created when a -pflash argument is
given, and that the size is determined by the given file. The idea is
From: "Lucas Mateus Castro (alqotel)"
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
true to +1. It also implemented a .fni4 version of thos
From: Matheus Ferst
Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-12-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c| 2 +
From: Matheus Ferst
Export p7_interrupt_powersave and use it in p7_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-26-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c| 2 +
From: BALATON Zoltan
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
differ
On Fri, Oct 28, 2022 at 06:02:50PM +0200, Eugenio Pérez wrote:
> By qemu coding style.
>
> Signed-off-by: Eugenio Pérez
You wrote this code originally so I don't mind but just to note I don't
want a flurry of patches "fixing" lines over 80 chars.
> ---
> hw/virtio/vhost-shadow-virtqueue.c | 7
From: BALATON Zoltan
In order to move PPC4xx SDRAM controller models together move out the
DDR2 controller model from ppc440_uc.c into a new ppc4xx_sdram.c file.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-Id:
<2f2900f93e997480e54b7bf9c32bb482a0fb1022.1666194485
From: Matheus Ferst
Use ppc_set_irq to raise/clear interrupts to ensure CPU_INTERRUPT_HARD
will be set/reset accordingly.
Reviewed-by: Fabiano Rosas
Signed-off-by: Matheus Ferst
Message-Id: <20221011204829.1641124-3-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
ta
From: Matheus Ferst
Move the interrupt masking logic out of cpu_has_work_POWER9 in a new
method, p9_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.16411
From: Matheus Ferst
Remove the following unused interrupts from the POWER7 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Hypervisor Doorbell and Event-Based Branch: introduced in
Power
From: Matheus Ferst
Remove the following unused interrupts from the POWER8 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Wat
From: Bernhard Beschow
The documentation suggests that there is a qemu-system-ppc32 binary
while the 32 bit version is actually just named qemu-system-ppc. Settle
on qemu-system-ppc64 which also works for 32 bit machines and causes
less clutter in the documentation.
Found-by: BALATON Zoltan
Sug
From: Matheus Ferst
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-13-matheus.fe...@eldorado.org.br>
Signed-o
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-24-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/ppc/excp_helper.c
From: Matheus Ferst
Remove the following unused interrupts from the POWER8 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970, and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Watch
From: Leandro Lupori
Profiling QEMU during Fedora 35 for PPC64 boot revealed that
6.39% of total time was being spent in helper_insns_inc(), on a
POWER9 machine. To avoid calling this helper every time PMCs had
to be incremented, an inline implementation of PMC5 increment and
check for overflow w
From: Bernhard Beschow
These defines aren't used outside of sdhci.c, so can be defined there.
Signed-off-by: Bernhard Beschow
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221018210146.193159-4-shen...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/sd/sd
From: "Lucas Mateus Castro (alqotel)"
Moved XSTSTDCSP, XSTSTDCDP and XSTSTDCQP to decodetree and moved some of
its decoding away from the helper as previously the DCMX, XB and BF were
calculated in the helper with the help of cpu_env, now that part was
moved to the decodetree with the rest.
xvts
From: BALATON Zoltan
This function is only used by the ppc4xx memory controller models so
it can be made static.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc4xx_devs.c| 62 --
From: Matheus Ferst
Writes to LPCR are hypervisor privileged.
Signed-off-by: Matheus Ferst
Reviewed-by: Fabiano Rosas
Message-Id: <20221011204829.1641124-27-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.c | 2 ++
target/ppc/cpu.h | 2 +-
2 files cha
From: "Lucas Mateus Castro (alqotel)"
Moved VABSDUB, VABSDUH and VABSDUW to decodetree and use gvec to
translate them.
vabsdub:
reptloopmaster patch
8 12500 0,03601600 0,00688500 (-80.9%)
25 40000,03651000 0,00532100 (-85.4%)
100 10000
From: Bernhard Beschow
The device model's functions start with "usdhc_", so rename the defines
accordingly for consistency.
Signed-off-by: Bernhard Beschow
Reviewed-by: Bin Meng
Message-Id: <20221018210146.193159-5-shen...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/sd/sdhci.c |
From: Bernhard Beschow
According to the JEDEC standard the device length is communicated to an
OS as an exponent (power of two).
Signed-off-by: Bernhard Beschow
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221018210146.193159-3-shen...@gmail.com>
Signed-off-by: Dan
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