From: Xiang Chen
Currently the numbers of MSI vectors come from register PCI_MSI_FLAGS
which should be power-of-2, but in some scenaries it is not the same as
the number that driver requires in guest, for example, a PCI driver wants
to allocate 6 MSI vecotrs in guest, but as the limitation, it wi
From: Xiang Chen
Currently the numbers of MSI vectors come from register PCI_MSI_FLAGS
which should be power-of-2, but in some scenaries it is not the same as
the number that driver requires in guest, for example, a PCI driver wants
to allocate 6 MSI vecotrs in guest, but as the limitation, it wi
On 11/8/22 15:05, Taylor Simpson wrote:
static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
{
+DisasContext *ctx = container_of(db, DisasContext, base);
+ctx->branch_cond = TCG_COND_NEVER;
}
Typically this would go in hexagon_tr_init_disas_context as well, but I d
On 11/8/22 15:05, Taylor Simpson wrote:
+/* Shift left with saturation */
+static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
+{
+TCGv_i64 src64 = tcg_temp_local_new_i64();
+TCGv_i64 shift64 = tcg_temp_new_i64();
+TCGv_i64 dst64 = tcg_temp_new_i64();
+TCGv dst_sar = tcg_t
On 11/8/22 15:05, Taylor Simpson wrote:
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 55
2 files changed, 63 insertions(+)
Reviewed-by:
On Fri, Nov 04, 2022 at 10:29:48PM +, Sean Christopherson wrote:
> On Fri, Nov 04, 2022, Chao Peng wrote:
> > On Thu, Oct 27, 2022 at 11:29:14AM +0100, Fuad Tabba wrote:
> > > Hi,
> > >
> > > On Tue, Oct 25, 2022 at 4:19 PM Chao Peng
> > > wrote:
> > > >
> > > > Currently in mmu_notifier val
On Mon, Nov 07, 2022 at 05:47:16PM -0500, Michael S. Tsirkin wrote:
> Changes from v3:
> Applied and squashed fix by Ani for modular build breakage
> Reordered Julia's patches to avoid bisect breakage
> Checkpatch fixes for Jason's patches
> Added Alex's patch to partially address v
checkpatch is unhappy about this line:
WARNING: Block comments use a leading /* on a separate line
#50: FILE: hw/acpi/nvdimm.c:1074:
+ aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element?
*/));
but there's nothing wrong with it - the check is just too simplistic. I
From: Samker
This is patch replaces WITH_QEMU_LOCK_GUARD() call with the
QEMU_LOCK_GUARD()
Signed-off-by: Samker
---
softmmu/physmem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index fb00596777..907491ae17 100644
--- a/softmmu
The following changes since commit 524fc737431d240f9d9f10aaf381003092868bac:
util/log: Ignore per-thread flag if global file already there (2022-11-07
16:00:02 -0500)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you to fetch changes
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Acked-by: Michael S. Tsirkin
Signed-off-by: Jason Wang
---
tests/qtest/meson.build | 2 +
tests/qtest/netdev-socket.c | 435
2 files changed, 437 insertions(+)
create mode 100644 tests/qtest
From: Si-Wei Liu
The citing commit has incorrect code in vhost_vdpa_receive() that returns
zero instead of full packet size to the caller. This renders pending packets
unable to be freed so then get clogged in the tx queue forever. When device
is being reset later on, below assertion failure ensu
The imported files don't properly mark all CONDEXEC instructions, so
we add some logic to hex_common.py to add the attribute.
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 6 ++
target/hexagon
When a packet has more than one change-of-flow instruction, only the first
one to branch is considered. We use the branch_taken variable to keep
track of this.
However, when there is a single cof instruction, we don't need the same
amount of bookkeeping.
We add the pkt_has_multi_cof member to th
Here are example instructions with a predicated .tmp/.cur assignment
if (p1) v12.tmp = vmem(r7 + #0)
if (p0) v12.cur = vmem(r9 + #0)
The .tmp/.cur indicates that references to v12 in the same packet
take the result of the load. However, when the predicate is false,
the value at the start o
Add pc field to Packet structure
For helpers that need PC, pass an extra argument
Remove slot arg from conditional jump helpers
On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC]
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 7 +++
tar
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments
Not only does this simplify the code, it improves the translation time
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 55
2 files changed, 63 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tc
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Recall that Hexagon allows packets with multiple jumps where only the
first one with a true predicate will actually jump. We can use
tcg_gen_goto_tb/tcg_gen_exit_tb when the packet
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 177 +++
target/hexagon/genptr.c | 90
2 files changed, 267 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 1b
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 203 +++
target/hexagon/genptr.c | 43 +
2 files changed, 246 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 506b454e4e
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Hexagon inner loops end with the endloop0 instruction
To go back to the beginning of the loop, this instructions writes to PC
from register SA0 (start address 0). To use direct bloc
1)
Performance improvement
Add pkt and insn to DisasContext
Many functions need information from all 3 structures, so merge
them together.
2)
Bug fix
Fix predicated assignment to .tmp and .cur
3)
Performance improvement
Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
These functions will not be
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 +++-
target
在 2022/11/8 10:42, Jason Wang 写道:
On Tue, Nov 8, 2022 at 8:42 AM Longpeng(Mike) wrote:
From: Longpeng
Signed-off-by: Longpeng
---
docs/system/devices/vhost-vdpa-device.rst | 43 +++
1 file changed, 43 insertions(+)
create mode 100644 docs/system/devices/vhost-vdp
On Tue, Nov 8, 2022 at 8:42 AM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> Signed-off-by: Longpeng
> ---
> docs/system/devices/vhost-vdpa-device.rst | 43 +++
> 1 file changed, 43 insertions(+)
> create mode 100644 docs/system/devices/vhost-vdpa-device.rst
>
> diff --git a
On Tue, Nov 8, 2022 at 8:42 AM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> The generic vDPA device doesn't support migration currently, so
> mark it as unmigratable temporarily.
>
> Signed-off-by: Longpeng
Acked-by: Jason Wang
> ---
> hw/virtio/vdpa-dev.c | 1 +
> 1 file changed, 1 insertio
We use 32bit value for linux,initrd-[start/end], when we have
loader_start > 4GB, there will be a wrong initrd_start passed
to the kernel, and the kernel will report the following warning.
[0.00] [ cut here ]
[0.00] initrd not fully accessible via the linear
On 2022/11/7 23:58, Alex Bennée wrote:
LIU Zhiwei writes:
On 2022/11/7 9:37, Alistair Francis wrote:
On Thu, Oct 13, 2022 at 4:32 PM LIU Zhiwei wrote:
When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.
Translate the guest code in a way that each
On Tue, Oct 25, 2022 at 11:13:41PM +0800, Chao Peng wrote:
> Introduce generic private memory register/unregister by reusing existing
> SEV ioctls KVM_MEMORY_ENCRYPT_{UN,}REG_REGION. It differs from SEV case
> by treating address in the region as gpa instead of hva. Which cases
> should these ioctl
From: Longpeng
Add helpers to get the "Transitional PCI Device ID" and "class_id"
of the device specified by the "Virtio Device ID".
These helpers will be used to build the generic vDPA device later.
Acked-by: Jason Wang
Signed-off-by: Longpeng
---
hw/virtio/virtio-pci.c | 88 +++
From: Longpeng
The generic vDPA device doesn't support migration currently, so
mark it as unmigratable temporarily.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 2885d06cbe..62d83d3423 1006
From: Longpeng
Signed-off-by: Longpeng
---
docs/system/devices/vhost-vdpa-device.rst | 43 +++
1 file changed, 43 insertions(+)
create mode 100644 docs/system/devices/vhost-vdpa-device.rst
diff --git a/docs/system/devices/vhost-vdpa-device.rst
b/docs/system/devices/vhost-
From: Longpeng
Supports vdpa-dev-pci, we can use the device as follow:
-device vhost-vdpa-device-pci,vhostdev=/dev/vhost-vdpa-X
Reviewed-by: Stefano Garzarella
Acked-by: Jason Wang
Signed-off-by: Longpeng
---
hw/virtio/meson.build| 1 +
hw/virtio/vdpa-dev-pci.c | 102 +
From: Longpeng
Hi guys,
With the generic vDPA device, QEMU won't need to touch the device
types any more, such like vfio.
We can use the generic vDPA device as follow:
-device vhost-vdpa-device-pci,vhostdev=/dev/vhost-vdpa-X
Or
-M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \
On Thu, Nov 03, 2022 at 05:43:52PM +0530,
Vishal Annapurve wrote:
> On Tue, Oct 25, 2022 at 8:48 PM Chao Peng wrote:
> >
> > This patch series implements KVM guest private memory for confidential
> > computing scenarios like Intel TDX[1]. If a TDX host accesses
> > TDX-protected guest memory, ma
From: Longpeng
Supports vdpa-dev, we can use the deivce directly:
-M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \
vhost-vdpa-device,vhostdev=/dev/vhost-vdpa-x
Reviewed-by: Stefano Garzarella
Acked-by: Jason Wang
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5 +
h
From: Richard Henderson
Since Disassemble wants the data in this format, collect
it that way. This allows using a loop to print the bytes.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <20221106212852.152384-3-richard.hender...@linaro.org>
---
disas/nanomip
From: Jiaxun Yang
I don't have access to Octeon68XX hardware but according
to my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which
From: Richard Henderson
There is no point in looking for a 48-bit opcode if we've
not read the second word for a 32-bit opcode.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221106023735.5277-5-richard.hender...@linaro.org>
---
disas/nanomips.c | 12 +
From: Richard Henderson
Reduce the number of local variables within the scope of the
setjmp by moving it to the existing helper. The actual length
returned from Disassemble is not used, because we have already
determined the length while reading bytes. Fixes:
nanomips.c: In function ‘print_ins
From: Pavel Dovgalyuk
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <166728058455.229236.138
From: Richard Henderson
Split out a helper function for reading a uint16_t
with the correct endianness.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221106023735.5277-4-richard.hender...@linaro.org>
---
disas/nanomips.c | 48 +++--
6 months ago Stefan Pejic stepped in as nanoMIPS maintainer
(see commit a 8e0e23445a "target/mips: Undeprecate nanoMIPS
ISA support in QEMU"), however today his email is bouncing:
** Message blocked **
Your message to stefan.pe...@syrmia.com has been blocked. See technical
details below for
From: Jiaxun Yang
As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segment. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Hender
Suggested-by: Stefan Weil
Reviewed-by: Stefan Weil
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221101114458.25756-4-phi...@linaro.org>
---
disas/nanomips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/nanomips.c b/disas/nanomips.c
index e4b21e7c45..3f454472
From: Jiaxun Yang
Some implementations (i.e. Loongson-2F) may decide to implement
a 64 bit FPU without implementing COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined
by CP0St_FR, there is no need to check for COP1X again.
Signed-off-by: Jiaxun Yang
Reviewed
Fix:
disas/nanomips.c:12231:62: warning: format specifies type 'char *' but the
argument has type 'uint64' (aka 'unsigned long long') [-Wformat]
return img_format("RESTOREF 0x%" PRIx64 ", %s", u_value, count_value);
~~^~~
Fix warnings such:
disas/nanomips.c:3251:64: warning: format specifies type 'char *' but the
argument has type 'int64' (aka 'long long') [-Wformat]
return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
~~ ^~~
Reviewed-by: Stefan Weil
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221101114458.25756-5-phi...@linaro.org>
---
disas/nanomips.c | 4
1 file changed, 4 deletions(-)
diff --git a/disas/nanomips.c b/disas/nanomips.c
index 3f45447292..821d4f8832 100644
--- a/disas/nanomips.c
+++ b/d
From: Jiaxun Yang
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Acked-by: Pavel Dovga
The following changes since commit cd706454c6cd239a477cb227caf3e3dfbb742d1a:
Merge tag 'pull-request-2022-11-06' of https://gitlab.com/thuth/qemu into
staging (2022-11-07 05:44:44 -0500)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20221108
for you t
Merged, thanks!
Stefan
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
From: Jason Wang
We use to warn on wrong rid2pasid entry. But this error could be
triggered by the guest and could happens during initialization. So
let's don't warn in this case.
Reviewed-by: Peter Xu
Signed-off-by: Jason Wang
Message-Id: <20221028061436.30093-2-jasow...@redhat.com>
Reviewed-
From: Cindy Lu
- Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
change the name to memory_get_xlat_addr(). So we can use this
function on other devices, such as vDPA device.
- Add a new function vfio_get_xlat_addr in vfio/common.c, and it will check
whether the memory is bac
On 7/11/22 23:47, Philippe Mathieu-Daudé wrote:
On 2/11/22 17:57, Jiaxun Yang wrote:
Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit
FPU without implmenting COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined by
CP0St_FR, there is no n
From: Kangjie Xu
Introduce the interface queue_enable() in VirtioDeviceClass and the
fucntion virtio_queue_enable() in virtio, it can be called when
VIRTIO_PCI_COMMON_Q_ENABLE is written and related virtqueue can be
started. It only supports the devices of virtio 1 or later. The
not-supported dev
checkpatch is unhappy about this line:
WARNING: Block comments use a leading /* on a separate line
#50: FILE: hw/acpi/nvdimm.c:1074:
+ aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element?
*/));
but there's nothing wrong with it - the check is just too simplistic. I
From: Julia Suvorova
Introduce the 64-bit entry point. Since we no longer have a total
number of structures, stop checking for the new ones at the EOF
structure (type 127).
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Message-Id: <20220731162141.178443-3-jus...@redhat.com>
Message-
From: Miguel Luis
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
Message-Id: <20221011181730.10885-2-miguel.l...@oracle.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Acked-by: Ani Sinha
---
tests/qtest/bios-tables-test-allowed-diff.h
From: Igor Mammedov
It will be used in followup commits to figure out if
device has it's own, device specific AML block.
Signed-off-by: Igor Mammedov
Message-Id: <20221017102146.2254096-7-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Ani S
On 2/11/22 17:57, Jiaxun Yang wrote:
Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit
FPU without implmenting COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined by
CP0St_FR, there is no need to check for COP1X again.
Signed-off-by: Jia
From: Xuan Zhuo
Introduce a new interface function virtio_queue_reset() to implement
reset for vq.
Add a new callback to VirtioDeviceClass for queue reset operation for
each child device.
Signed-off-by: Xuan Zhuo
Acked-by: Jason Wang
Message-Id: <20221017092558.111082-3-xuanz...@linux.alibaba
On 31/10/22 14:25, Jiaxun Yang wrote:
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
---
v2:
Do casting in decodetr
From: Kangjie Xu
Introduce vhost_virtqueue_reset(), which can reset the specific
virtqueue in the device. Then it will unmap vrings and the desc
of the virtqueue.
Here we do not reuse the vhost_net_stop_one() or vhost_dev_stop(),
because they work at queue pair level. We do not use
vhost_virtque
From: Xuan Zhuo
Add virtqueue reset feature for virtio-net
Signed-off-by: Xuan Zhuo
Message-Id: <20221017092558.111082-16-xuanz...@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/net/virtio-net.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/
From: Kangjie Xu
Add virtqueue reset feature for vhost-kernel.
Signed-off-by: Kangjie Xu
Signed-off-by: Xuan Zhuo
Acked-by: Jason Wang
Message-Id: <20221017092558.111082-15-xuanz...@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/net/vhost_net.c
From: Julia Suvorova
The new test is run with a large number of cpus and checks if the
core_count field in smbios_cpu_test (structure type 4) is correct.
Choose q35 as it allows to run with -smp > 255.
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-5-jus...@redhat.com>
Messag
From: Julia Suvorova
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-4-jus...@redhat.com>
Message-Id: <2022101731.101412-4-jus...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Acked-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowe
On 1/11/22 06:29, Pavel Dovgalyuk wrote:
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk
---
target/mips/tcg/translate.c | 10 +++---
From: Hesham Almatary
* Expected ACPI Data Table [HMAT]
[000h 4]Signature : "HMAT"[Heterogeneous
Memory Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Ch
On 1/11/22 12:44, Philippe Mathieu-Daudé wrote:
Fix invalid string formats reported by Stefan:
https://lore.kernel.org/qemu-devel/78553699-00c1-ad69-1d58-02f75a1f4...@weilnetz.de/
Philippe Mathieu-Daudé (5):
disas/nanomips: Fix invalid PRId64 format calling img_format()
disas/nanomips: Fix
From: Jason Wang
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
existing support for scalable mode, we need to implement the following
missing parts:
1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation
with PASID
2) tag IOTLB with PASID
3) PASID cache and its
From: Kangjie Xu
Introduce vhost_net_virtqueue_restart(), which can restart the
specific virtqueue when the vhost net started running before.
If it fails to restart the virtqueue, the device will be stopped.
Here we do not reuse vhost_net_start_one() or vhost_dev_start()
because they work at que
From: Ani Sinha
This change adds initial biosbits config file that instructs biosbits to run
bios test suits in batch mode. Additionally acpi and smbios structures are also
dumped.
Cc: Daniel P. Berrangé
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
Cc: Alex Bennée
Cc:
From: Yajun Wu
This patch is part of adding vhost-user vhost_dev_start support. The
motivation is to improve backend configuration speed and reduce live
migration VM downtime.
Moving the device start routines after finishing all the necessary device
and VQ configuration, further aligning to the
From: Xuan Zhuo
Separate the logic of vq reset. This logic will be called directly
later.
Signed-off-by: Xuan Zhuo
Acked-by: Jason Wang
Message-Id: <20221017092558.111082-2-xuanz...@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio.c |
From: Gregory Price
Early-boot e820 records will be inserted by the bios/efi/early boot
software and be reported to the kernel via insert_resource. Later, when
CXL drivers iterate through the regions again, they will insert another
resource and make the RESERVED memory area a child.
This RESERV
On 31/10/22 14:25, Jiaxun Yang wrote:
Hi all,
I was trying to build a MIPS VirtIO board[1] for QEMU that is able
to work with all processors we support.
When I was bring up varoius CPUs on that board I noticed some issues
with the system emulation code that I'm fixing in this series.
Thanks.
From: Miguel Luis
Step 6 & 7 of the bios-tables-test.c documented procedure.
Differences between disassembled ASL files for MADT:
@@ -11,9 +11,9 @@
*/
[000h 4]Signature : "APIC"[Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Le
From: Ani Sinha
This introduces QEMU acpi/smbios biosbits avocado test which is run
from within the python virtual environment. When the bits tests are run, bits
binaries are downloaded from an external repo/location, bios bits iso is
regenerated containing the acpi/smbios bits tests that are mai
From: Kangjie Xu
Support queue_enable in vhost-kernel scenario. It can be called when
a vq reset operation has been performed and the vq is restared.
It should be noted that we can restart the vq when the vhost has
already started. When launching a new vhost device, the vhost is not
started and
From: Igor Mammedov
Move _GPE block declaration before it gets referenced by other
hotplug handlers. While at it move PCI hotplug (_E01) handler
after PCI tree description to avoid forward reference to
to not yet declared methods/devices.
PS:
Forward 'usage' usualy is fine as long as it's hidden
From: Brice Goglin
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6]
From: Brice Goglin
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 00
From: Yajun Wu
The motivation of adding vhost-user vhost_dev_start support is to
improve backend configuration speed and reduce live migration VM
downtime.
Today VQ configuration is issued one by one. For virtio net with
multi-queue support, backend needs to update RSS (Receive side
scaling) on
From: Markus Armbruster
Cc: Michael S. Tsirkin
Signed-off-by: Markus Armbruster
Message-Id: <20221020120458.80709-1-arm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
From: Xuan Zhuo
virtio-net and vhost-kernel implement queue reset.
Queued packets in the corresponding queue pair are flushed
or purged.
For virtio-net, userspace datapath will be disabled later in
__virtio_queue_reset(). It will set addr of vring to 0 and idx to 0.
Thus, virtio_net_receive() an
From: Bernhard Beschow
Ammends commit b23046abe78f48498a423b802d6d86ba0172d57f 'pc: acpi-build:
simplify PCI bus tree generation'.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221026133110.91828-2-shen...@gmail.com>
Message-Id: <20221028103419.93398-2-shen
On 1/11/22 06:29, Pavel Dovgalyuk wrote:
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk
---
target/mips/tcg/translate.c | 10 +++---
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen
Signed-off-by: Hesham Almatary
Reviewed-by: Igor Mammedov
Message-Id: <20221027100037.251-7-he
From: Kangjie Xu
Expose vhost_virtqueue_start(), we need to use it when restarting a
virtqueue.
Signed-off-by: Kangjie Xu
Signed-off-by: Xuan Zhuo
Acked-by: Jason Wang
Message-Id: <20221017092558.111082-8-xuanz...@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. T
From: Kangjie Xu
Introduce the fucntion flush_or_purge_queued_packets(), it will be
used in device reset and virtqueue reset. Therefore, we extract the
common logic as a new function.
Signed-off-by: Kangjie Xu
Signed-off-by: Xuan Zhuo
Acked-by: Jason Wang
Message-Id: <20221017092558.111082-12
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20221017102146.2254096-6-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 21 +
1 file changed, 21 insertions(+)
diff --gi
From: Akihiko Odaki
There were several different ways to deal with the situation where the
vector specified for a msix function is out of bound:
- early return a function and keep progresssing
- propagate the error to the caller
- mark msix unusable
- assert it is in bound
- just ignore
An out-o
From: Igor Mammedov
example of the change for PC machine with hotplug disabled on root buss (no
BSEL case):
-Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+Field (S08.P40C, ByteAcc, NoLock, Preserve)
===
-Scope (_SB.PCI0)
-{
-Device (ISA)
-{
-
From: David Daney
Most other virtio-pci devices allow MSI-X, let's have it for rng too.
Signed-off-by: David Daney
Reviewed-by: Marcin Nowakowski
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221014160947.66105-1-phi...@fungible.com>
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Michael S
From: Igor Mammedov
Expected changes are:
1) Moving _GPE scope declaration achec of all _E0x methods
+Scope (_GPE)
+{
+Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+}
+
Scope (_SB)
{
Device (\_SB.PCI0.PRES)
From: Jason Wang
We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drop
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