[PATCH v2 1/8] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Alistair Francis --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h | 6 ++ 2 files changed, 49 insertio

[PATCH v2 0/8] support subsets of code size reduction extension

This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v2 To test Zc* implementation, s

[PATCH v2 8/8] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/d

[PATCH v2 3/8] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvd.c.inc | 18

[PATCH v2 6/8] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 7 + target/riscv/csr.c

[PATCH v2 4/8] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode| 22 target/riscv/insn_trans/trans_rvzce.c.inc | 133 ++ target/riscv/translate.c | 2 +

[PATCH v2 2/8] target/riscv: add support for Zca and Zcf extensions

Add check for Zca and Zcf extensions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 16 ++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_tran

[PATCH v2 5/8] target/riscv: add support for Zcmp extension

Add encode, trans* functions and helper functions support for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/helper.h | 6 + target/riscv/insn16.decode| 16 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 107 ++

[PATCH v2 7/8] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ab04ab246..b9e41df96c 100644

[PATCH] hw/sd: Fix sun4i allwinner-sdhost for U-Boot

Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot access SD card. The problem is that FIFO register in current allwinner-sdhost implementation is at the address corresponding to Allwinner H3, but not A10. Linux kernel is not affected since Linux driver uses DMA access and

[PATCH v9 4/5] vdpa-dev: mark the device as unmigratable

From: Longpeng The generic vDPA device doesn't support migration currently, so mark it as unmigratable temporarily. Reviewed-by: Stefano Garzarella Acked-by: Jason Wang Signed-off-by: Longpeng --- hw/virtio/vdpa-dev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/virtio/vdpa-dev.c b

[PATCH v9 0/5] add generic vDPA device support

From: Longpeng Hi guys, With the generic vDPA device, QEMU won't need to touch the device types any more, such like vfio. We can use the generic vDPA device as follow: -device vhost-vdpa-device-pci,vhostdev=/dev/vhost-vdpa-X Or -M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \

[PATCH v9 1/5] virtio: get class_id and pci device id by the virtio id

From: Longpeng Add helpers to get the "Transitional PCI Device ID" and "class_id" of the device specified by the "Virtio Device ID". These helpers will be used to build the generic vDPA device later. Acked-by: Jason Wang Signed-off-by: Longpeng --- hw/virtio/virtio-pci.c | 88 +++

[PATCH v9 3/5] vdpa: add vdpa-dev-pci support

From: Longpeng Supports vdpa-dev-pci, we can use the device as follow: -device vhost-vdpa-device-pci,vhostdev=/dev/vhost-vdpa-X Reviewed-by: Stefano Garzarella Acked-by: Jason Wang Signed-off-by: Longpeng --- hw/virtio/meson.build| 1 + hw/virtio/vdpa-dev-pci.c | 102 +

[PATCH v9 5/5] docs: Add generic vhost-vdpa device documentation

From: Longpeng Signed-off-by: Longpeng --- .../devices/vhost-vdpa-generic-device.rst | 46 +++ 1 file changed, 46 insertions(+) create mode 100644 docs/system/devices/vhost-vdpa-generic-device.rst diff --git a/docs/system/devices/vhost-vdpa-generic-device.rst b/docs/syste

[PATCH v9 2/5] vdpa: add vdpa-dev support

From: Longpeng Supports vdpa-dev, we can use the deivce directly: -M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \ vhost-vdpa-device,vhostdev=/dev/vhost-vdpa-x Reviewed-by: Stefano Garzarella Acked-by: Jason Wang Signed-off-by: Longpeng --- hw/virtio/Kconfig| 5 + h

Re: [PULL 0/3] pc,virtio: regression fixes

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 0/8] Misc fixes

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 0/1] ppc queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

[PATCH v2 0/3] Add (more) missing PolarFire SoC io regions

From: Conor Dooley Hey all, But of a v2 of what I sent the other day [0].. Apart from DDR (see [1]), these should be the last bits needed to get recent Linux kernels booting again for Icicle/PolarFire SoC. Previously, I had been disabling the hwrng and PCI but I keep forgetting that is required a

[PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented

From: Conor Dooley The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for stori

[PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented

From: Conor Dooley The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to th

[PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb

From: Conor Dooley On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by "Clock Conditioning Circuitry" in the FPGA. The specific clock depends on the FPGA bitstream & can be locked to one particular {D,P}LL - in the Icicle Kit Reference Design v2022.09 or later this is/will be

Re: [PATCH] hw/misc/pfsoc: add fabric clocks to ioscb

On Sat, Nov 12, 2022 at 08:37:38AM +0800, Bin Meng wrote: > Hi Conor, > > On Sat, Nov 12, 2022 at 8:31 AM Conor Dooley wrote: > > > > On Thu, Nov 10, 2022 at 12:18:44AM +0100, Philippe Mathieu-Daudé wrote: > > > Hi Conor, > > > > > > On 9/11/22 20:08, Conor Dooley wrote: > > > > From: Conor Doole

[PATCH] qga: Add initial OpenBSD and NetBSD support

qga: Add initial OpenBSD and NetBSD support Signed-off-by: Brad Smith --- meson.build | 2 +- qga/commands-bsd.c | 5 + qga/commands-posix.c | 9 +++-- qga/main.c | 6 +++--- 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build in