Re: Instruction concurrent modification issue of direct jump in AArch64

On 11/19/22 00:19, hev wrote: Hello, I talked with Hu Qi about the risk of instruction concurrent modification in TCG direct jump for LoongArch, and the conclusion is that the implementation is correct. Similarly, the AArch64 implementation doesn't seem to be quite correct. IIUC, multiple

Re: [PATCH qemu.git v2 5/9] hw/timer/imx_epit: do not persist CR.SWR bit

From: Axel Heider Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 5315d9633e..6af460946f 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -191,8

Re: [PULL v4 46/83] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML

On Fri, Nov 18, 2022 at 03:55:17PM +0100, Igor Mammedov wrote: > On Fri, 18 Nov 2022 14:08:36 +0100 > Igor Mammedov wrote: > > > On Thu, 17 Nov 2022 22:51:46 +0100 > > Volker Rümelin wrote: > [...] > > > since this patch SeaBIOS no longer detects the PS/2 keyboard. This means > > > there's no

Re: [PULL v4 30/83] virtio: core: vq reset feature negotation support

On Fri, Nov 18, 2022 at 03:32:56PM +0100, Stefano Garzarella wrote: > Hi, > starting from this commit 69e1c14aa2 ("virtio: core: vq reset feature > negotation support"), vhost-user-vsock and vhost-vsock fails while > setting the device features, because VIRTIO_F_RING_RESET is not masked. > >

Re: [PATCH 3/4] target/avr: fix avr features processing

Reviewed-by: Michael Rolnik On Sat, Nov 19, 2022 at 7:56 AM Pavel Dovgalyuk wrote: > Bit vector for features has 64 bits. This patch fixes bit shifts in > avr_feature and set_avr_feature functions to be 64-bit too. > > Signed-off-by: Pavel Dovgalyuk > --- > target/avr/cpu.h |4 ++-- > 1

Re: [PATCH v2 05/19] hw/9pfs: Update 9pfs to use the new QemuFd_t type

Hi Greg, On Sat, Nov 19, 2022 at 6:20 PM Greg Kurz wrote: > > On Fri, 18 Nov 2022 14:38:00 +0100 > Christian Schoenebeck wrote: > > > On Friday, November 18, 2022 10:29:51 AM CET Greg Kurz wrote: > > > On Fri, 11 Nov 2022 12:22:11 +0800 > > > Bin Meng wrote: > > > > > > > With this new

Re: [PATCH] chardev/char-win-stdio: Pass Ctrl+C to guest with a multiplexed monitor

On Fri, Nov 11, 2022 at 8:11 AM Bin Meng wrote: > > On Wed, Oct 26, 2022 at 3:39 PM Marc-André Lureau > wrote: > > > > On Tue, Oct 25, 2022 at 6:15 PM Bin Meng wrote: > > > > > > At present when pressing Ctrl+C from a guest running on QEMU Windows > > > with a multiplexed monitor, e.g.: -serial

Re: [PATCH] gtk: disable GTK Clipboard with a new option 'gtk_clipboard'

On Fri, 18 Nov 2022 at 22:26, Jim Fehlig wrote: > > I should make myself useful around here on occasion when items are within my > skill set. But I already struggle to find time for that in the libvirt > community > :-). > > On 11/8/22 09:23, Claudio Fontana wrote: > > The GTK Clipboard

[PATCH 1/3] kvm: introduce a helper before creating the 1st vcpu

Some per-VM kvm caps (e.g., KVM_CAP_PMU_CAPABILITY) can only be enabled/disabled before creating the 1st vcpu, that is, when (!kvm->created_vcpus) at the KVM side. Unfortunately, some properties are still not set during kvm_arch_init(). The values of those properties are obtained during the init

[PATCH 0/3] kvm: fix two svm pmu virtualization bugs

This patchset is to fix two svm pmu virtualization bugs. 1. The 1st bug is that "-cpu,-pmu" cannot disable svm pmu virtualization. To use "-cpu EPYC" or "-cpu host,-pmu" cannot disable the pmu virtualization. There is still below at the VM linux side ... [0.510611] Performance Events:

[PATCH 2/3] i386: kvm: disable KVM_CAP_PMU_CAPABILITY if "pmu" is disabled

The "perf stat" at the VM side still works even we set "-cpu host,-pmu" in the QEMU command line. That is, neither "-cpu host,-pmu" nor "-cpu EPYC" could disable the pmu virtualization in an AMD environment. We still see below at VM kernel side ... [0.510611] Performance Events: Fam17h+ core

[PATCH 3/3] target/i386/kvm: get and put AMD pmu registers

The QEMU side calls kvm_get_msrs() to save the pmu registers from the KVM side to QEMU, and calls kvm_put_msrs() to store the pmu registers back to the KVM side. However, only the Intel gp/fixed/global pmu registers are involved. There is not any implementation for AMD pmu registers. The

Re: [PATCH v2 05/19] hw/9pfs: Update 9pfs to use the new QemuFd_t type

On Fri, 18 Nov 2022 14:38:00 +0100 Christian Schoenebeck wrote: > On Friday, November 18, 2022 10:29:51 AM CET Greg Kurz wrote: > > On Fri, 11 Nov 2022 12:22:11 +0800 > > Bin Meng wrote: > > > > > With this new QemuFd_t type, it significantly reduces the number of > > > > I cannot find the

Re: [PATCH 1/2] io: Add support for MSG_PEEK for socket channel

On 19/11/22 3:06 pm, manish.mishra wrote: MSG_PEEK reads from the peek of channel, The data is treated as unread and the next read shall still return this data. This support is currently added only for socket class. Extra parameter 'flags' is added to io_readv calls to pass extra read flags

check magic value for deciding the mapping of channels

Current logic assumes that channel connections on the destination side are always established in the same order as the source and the first one will always be the main channel followed by the multifid or post-copy preemption channel. This may not be always true, as even if a channel has a

[PATCH v3 2/2] migration: check magic value for deciding the mapping of channels

Current logic assumes that channel connections on the destination side are always established in the same order as the source and the first one will always be the main channel followed by the multifid or post-copy preemption channel. This may not be always true, as even if a channel has a

[PATCH 2/2] migration: check magic value for deciding the mapping of channels

Current logic assumes that channel connections on the destination side are always established in the same order as the source and the first one will always be the main channel followed by the multifid or post-copy preemption channel. This may not be always true, as even if a channel has a

[PATCH v3 1/2] io: Add support for MSG_PEEK for socket channel

MSG_PEEK reads from the peek of channel, The data is treated as unread and the next read shall still return this data. This support is currently added only for socket class. Extra parameter 'flags' is added to io_readv calls to pass extra read flags like MSG_PEEK. Suggested-by: Daniel P. Berrangé

[PATCH 1/2] io: Add support for MSG_PEEK for socket channel

MSG_PEEK reads from the peek of channel, The data is treated as unread and the next read shall still return this data. This support is currently added only for socket class. Extra parameter 'flags' is added to io_readv calls to pass extra read flags like MSG_PEEK. --- chardev/char-socket.c

Re: [PULL v4 46/83] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML

Am 18.11.22 um 15:55 schrieb Igor Mammedov: On Fri, 18 Nov 2022 14:08:36 +0100 Igor Mammedov wrote: On Thu, 17 Nov 2022 22:51:46 +0100 Volker Rümelin wrote: [...] since this patch SeaBIOS no longer detects the PS/2 keyboard. This means there's no keyboard in SeaBIOS, GRUB or FreeDOS. OVMF

Instruction concurrent modification issue of direct jump in AArch64

Hello, I talked with Hu Qi about the risk of instruction concurrent modification in TCG direct jump for LoongArch, and the conclusion is that the implementation is correct. Similarly, the AArch64 implementation doesn't seem to be quite correct. IIUC, multiple instructions paired with an atomic