Re: [PATCH 4/4] include/hw/ppc include/hw/pci-host: Drop extra typedefs

On 12/10/22 12:21, Markus Armbruster wrote: PnvChip is typedef'ed in five places, and PnvPhb4PecState in two. Keep one, drop the others. Signed-off-by: Markus Armbruster Reviewed-by: Cédric Le Goater Thanks, C. --- hw/pci-host/pnv_phb.h | 1 - include/hw/pci-host/pnv_phb3.h

Re: [PATCH 3/4] include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.h

On 12/10/22 12:21, Markus Armbruster wrote: The next commit needs to include hw/ppc/pnv.h from hw/pci-host/pnv_phb.h. Avoid an inclusion loop. Signed-off-by: Markus Armbruster Reviewed-by: Cédric Le Goater Thanks, C. (one comment below) --- hw/pci-host/pnv_phb.h | 1 + inc

[PATCH] hw/riscv: Add support to change default RISCV hart memory region

Add support to optionally specify a memory region container to be used to override the default system memory used by the the RISCV harts when they are realized. Additional memory regions can be added as sub-regions of this container to dynamically control the memory regions and mappings visible fro

[PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC

Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build") the IBEX PLIC model was replaced with the SiFive PLIC model in the 'opentitan' machine but we forgot the add the dependency there. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis ---

[PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb

Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which is VIRTIO_NDEV and also used as the value of "riscv,ndev" property in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES should i

[PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC

Per chapter 6.5.2 in [1], the number of interupt sources including interrupt source 0 should be 187. [1] PolarFire SoC MSS TRM: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf Fixes: 56f6e31

[PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value

At present the default value of "num-sources" property is zero, which does not make a lot of sense, as in sifive_plic_realize() we see s->bitfield_words is calculated by: s->bitfield_words = (s->num_sources + 31) >> 5; if the we don't configure "num-sources" property its default value zero make

[PATCH v3 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC

Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 supports 52 interrupt sources while G000 supports 51 interrupt sources. We use the value of G002 and G003, so it is 53 (including source 0). [1] G000 manual: https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa492

[PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order

SHAKTI_C machine Kconfig option was inserted in disorder. Fix it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Wilfred Mallawa --- (no changes since v1) hw/riscv/Kconfig | 16 +--- 1 file changed, 9 insertions(+), 7 delet

[PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in both riscv_aplic_realize() and riscv_imsic_realize(). Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC. Signed-off-by: Bin Meng Reviewed-

[PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"

At present magic number is used to create "riscv,ndev" property in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that is used to instantiate the PLIC model instead. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/

[PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser

At present the PLIC config parser can only handle legal config string like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is given the parser won't get the correct configuration. This commit improves the config parser to make it more robust. Signed-off-by: Bin Meng Acked-by: Alistair

[PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check

The pending register upper limit is currently set to plic->num_sources >> 3, which is wrong, e.g.: considering plic->num_sources is 7, the upper limit becomes 0 which fails the range check if reading the pending register at pending_base. Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block") Signed-off-

[PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0

At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note the irq number ca

[PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization

"hartid-base" and "priority-base" are zero by default. There is no need to initialize them to zero again. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa --- (no changes since v1) hw/riscv/opentitan.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/op

[PATCH v3 05/16] hw/riscv: spike: Remove misleading comments

PLIC is not included in the 'spike' machine. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/spike.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1e1d752c00..13946acf0d 10064

[PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in sifive_plic_realize(). Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from RISC-V machines. Signed-off-by: Bin Meng Reviewed-by

[PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()

The realize() callback has an errp for us to propagate the error up. While we are here, correct the wrong multi-line comment format. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- Changes in v3: - Fix the typo in the commit message Changes in v2

[PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H

H-mode has been removed since priv spec 1.10. Drop it. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/intc/sifive_plic.h | 1 - hw/intc/sifive_plic.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/

Re: [PATCH-for-8.0 1/7] hw/mips/bootloader: Handle buffers as opaque arrays

On Sat, 10 Dec 2022, Philippe Mathieu-Daudé wrote: It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 55 +--- hw/mi

[PATCH] tpm: add backend for mssim

The Microsoft Simulator (mssim) is the reference emulation platform for the TCG TPM 2.0 specification. https://github.com/Microsoft/ms-tpm-20-ref.git It exports a fairly simple network socket baset protocol on two sockets, one for command (default 2321) and one for control (default 2322). This p

Re: [PATCH v2] target/sh4: Fix TB_FLAG_UNALIGN

Hi, On Thu, Sep 01, 2022 at 11:15:09AM +0100, Richard Henderson wrote: > The value previously chosen overlaps GUSA_MASK. > > Rename all DELAY_SLOT_* and GUSA_* defines to emphasize > that they are included in TB_FLAGs. Add aliases for the > FPSCR and SR bits that are included in TB_FLAGS, so tha

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

On 10/12/22 16:55, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 997e74ee52..cc3df385df 100644 --- a/hw

Re: [PATCH-for-8.0 4/7] hw/mips/bootloader: Implement nanoMIPS LUI opcode

On 10/12/22 16:54, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 29 ++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 7f7d938f2e..997e74ee52 100644 --

Re: [PATCH 1/2] include/hw/virtio: Break inclusion loop

On 10/12/22 14:39, Markus Armbruster wrote: hw/virtio/virtio.h and hw/virtio/vhost.h include each other. The former doesn't actually need the latter, so drop that inclusion to break the loop. Signed-off-by: Markus Armbruster --- include/hw/virtio/virtio.h | 1 - hw/virtio/virtio.c |

[PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index cc3df385df..541b59bf84 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -17

[PATCH-for-8.0 4/7] hw/mips/bootloader: Implement nanoMIPS LUI opcode

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 29 ++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 7f7d938f2e..997e74ee52 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @

[PATCH-for-8.0 3/7] hw/mips/bootloader: Implement nanoMIPS NOP opcode

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 3a4573118c..7f7d938f2e 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -59,7 +59,11 @@ static v

[PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 997e74ee52..cc3df385df 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -150

[PATCH-for-8.0 0/7] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

Bernhard posted his "Consolidate PIIX south bridges" v3 series: https://lore.kernel.org/qemu-devel/20221204190553.3274-1-shen...@gmail.com/ However in order to simplify it, on the Malta board we need to set the PIIX IRQC[A:D] routing values via the embedded bootloader (used when no external BIOS i

[PATCH-for-8.0 2/7] hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode generator

While 32-bit wide instructions ISA restricts LUI to a 16-bit immediate value, some 16-bit ones allow up to 20-bit immediate (in particular nanoMIPS). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/

[PATCH-for-8.0 7/7] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs

Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader helper to set BAR registers") converted write_bootloader(), convert the equivalent write_bootloader_nanomips(), allowing us to modify the bootloader code more easily in the future. Signed-off-by: Philippe Mathieu-Daudé --- hw/mip

[PATCH-for-8.0 1/7] hw/mips/bootloader: Handle buffers as opaque arrays

It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 55 +--- hw/mips/malta.c | 19 +++-- include

Re: [PATCH-for-8.0 2/3] hw/intc: Move omap_lcdc.c out of target-specific source set

I suggest to change the subject since you move more than just the omap controller. On 09/12/2022 18.00, Philippe Mathieu-Daudé wrote: The Goldfish interrupt controller is not target specific. While the Exynos interrupt combiner is only used by the ARM targets, we can build this device once

Re: [PATCH v2 for-8.0] hw/rtc/mc146818rtc: Make this rtc device target independent

On 09/12/2022 11:15, Thomas Huth wrote: The only reason for this code being target dependent is the apic-related code in rtc_policy_slew_deliver_irq(). Since these apic functions are rather simple, we can easily move them into a new, separate file (apic_irqcount.c) which will always be compiled

[PATCH 0/2] Clean up includes

Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are need

[PATCH 2/2] include: Include headers where needed

A number of headers neglect to include everything they need. They compile only if the headers they need are already included from elsewhere. Fix that. Signed-off-by: Markus Armbruster --- include/exec/plugin-gen.h | 1 + include/hw/acpi/erst.h | 3 +++ in

[PATCH 1/2] include/hw/virtio: Break inclusion loop

hw/virtio/virtio.h and hw/virtio/vhost.h include each other. The former doesn't actually need the latter, so drop that inclusion to break the loop. Signed-off-by: Markus Armbruster --- include/hw/virtio/virtio.h | 1 - hw/virtio/virtio.c | 1 + 2 files changed, 1 insertion(+), 1 deletio

Re: [PATCH 4/4] include/hw/ppc include/hw/pci-host: Drop extra typedefs

On 10/12/22 12:21, Markus Armbruster wrote: PnvChip is typedef'ed in five places, and PnvPhb4PecState in two. Keep one, drop the others. Signed-off-by: Markus Armbruster --- hw/pci-host/pnv_phb.h | 1 - include/hw/pci-host/pnv_phb3.h | 1 - include/hw/pci-host/pnv_phb4.h | 2 -- i

Re: [PATCH 2/4] include/hw/ppc: Supply a few missing includes

On 12/10/22 12:21, Markus Armbruster wrote: A few headers neglect to include headers they need. They compile only if something else includes the required header(s) first. Fix that. Signed-off-by: Markus Armbruster Reviewed-by: Cédric Le Goater Thanks, C. --- include/hw/ppc/pnv_lpc.h

Re: [PATCH 1/4] include/hw/ppc: Split pnv_chip.h off pnv.h

On 12/10/22 12:21, Markus Armbruster wrote: PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined in pnv.h. Many users of the header don't actually need them. One instance is this inclusion loop: hw/ppc/pnv_homer.h includes hw/ppc/pnv.h for typedef PnvChip, and vice versa for str

[PATCH 0/4] hw/ppc: Clean up includes

Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are need

[PATCH 4/4] include/hw/ppc include/hw/pci-host: Drop extra typedefs

PnvChip is typedef'ed in five places, and PnvPhb4PecState in two. Keep one, drop the others. Signed-off-by: Markus Armbruster --- hw/pci-host/pnv_phb.h | 1 - include/hw/pci-host/pnv_phb3.h | 1 - include/hw/pci-host/pnv_phb4.h | 2 -- include/hw/ppc/pnv_core.h | 3 +-- include/hw/

[PATCH 1/4] include/hw/ppc: Split pnv_chip.h off pnv.h

PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined in pnv.h. Many users of the header don't actually need them. One instance is this inclusion loop: hw/ppc/pnv_homer.h includes hw/ppc/pnv.h for typedef PnvChip, and vice versa for struct PnvHomer. Similar structs live in their o

[PATCH 2/4] include/hw/ppc: Supply a few missing includes

A few headers neglect to include headers they need. They compile only if something else includes the required header(s) first. Fix that. Signed-off-by: Markus Armbruster --- include/hw/ppc/pnv_lpc.h| 3 ++- include/hw/ppc/pnv_occ.h| 3 ++- include/hw/ppc/pnv_pnor.h | 2 +- include/hw

[PATCH 3/4] include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.h

The next commit needs to include hw/ppc/pnv.h from hw/pci-host/pnv_phb.h. Avoid an inclusion loop. Signed-off-by: Markus Armbruster --- hw/pci-host/pnv_phb.h | 1 + include/hw/pci-host/pnv_phb4.h | 3 ++- include/hw/ppc/pnv.h | 3 ++- hw/ppc/pnv_psi.c | 1 + 4 f