Re: [PATCH 05/30] configure: remove backwards-compatibility and obsolete options

On Fri, Dec 9, 2022 at 3:43 PM Paolo Bonzini wrote: > > Signed-off-by: Paolo Bonzini Reviewed-by: Marc-André Lureau > --- > configure | 20 > 1 file changed, 20 deletions(-) > > diff --git a/configure b/configure > index 4d14ff9c319c..adfff30a6204 100755 > --- a/configur

[PATCH v3] hw/rtc/mc146818rtc: Make this rtc device target independent

The only reason for this code being target dependent is the apic-related code in rtc_policy_slew_deliver_irq(). Since these apic functions are rather simple, we can easily move them into a new, separate file (apic_irqcount.c) which will always be compiled and linked if either APIC or the mc146818 d

Re: [PATCH 04/30] configure: preserve qemu-ga variables

On Fri, Dec 9, 2022 at 3:28 PM Paolo Bonzini wrote: > > Ensure that qemu-ga variables set at configure time are kept > later when the script is rerun. For preserve_env to work, > the variables need to be empty so move the default values > to config-host.mak generation. > > Signed-off-by: Paolo Bo

Re: [PATCH v2 for-8.0] hw/rtc/mc146818rtc: Make this rtc device target independent

On 10/12/2022 14.48, Mark Cave-Ayland wrote: On 09/12/2022 11:15, Thomas Huth wrote: The only reason for this code being target dependent is the apic-related code in rtc_policy_slew_deliver_irq(). Since these apic functions are rather simple, we can easily move them into a new, separate file (a

Re: [PATCH] linux-user: Enhance strace output for various syscalls

On 9/12/22 11:55, Helge Deller wrote: Add appropriate strace printf formats for various Linux syscalls. Signed-off-by: Helge Deller --- linux-user/strace.list | 43 ++ 1 file changed, 23 insertions(+), 20 deletions(-) #ifdef TARGET_NR_poll -{ TAR

Re: [PATCH v1 04/24] vfio-user: add region cache

On 11/9/22 00:13, John Johnson wrote: cache VFIO_DEVICE_GET_REGION_INFO results to reduce memory alloc/free cycles and as prep work for vfio-user Signed-off-by: John G Johnson Signed-off-by: Elena Ufimtseva Signed-off-by: Jagannathan Raman LGTM, Reviewed-by: Cédric Le Goater Thanks, C.

Re: [PATCH] include: Don't include qemu/osdep.h

On 12/12/22 08:04, Markus Armbruster wrote: docs/devel/style.rst mandates: The "qemu/osdep.h" header contains preprocessor macros that affect the behavior of core system headers like . It must be the first include so that core system headers included by external libraries ge

Re: [PATCH-for-8.0 0/7] hw/mips: Make gt64xxx_pci.c endian-agnostic

On 12/12/22 01:55, Bernhard Beschow wrote: Am 9. Dezember 2022 15:15:26 UTC schrieb "Philippe Mathieu-Daudé" : Respining an old/unfinished series... Add the 'cpu-little-endian' qdev property to the GT64120 north bridge so [target-specific] machines can set its endianness, allowing it to be en

Re: [PATCH 3/4] include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.h

Cédric Le Goater writes: > On 12/10/22 12:21, Markus Armbruster wrote: >> The next commit needs to include hw/ppc/pnv.h from >> hw/pci-host/pnv_phb.h. Avoid an inclusion loop. >> Signed-off-by: Markus Armbruster > > > Reviewed-by: Cédric Le Goater > > Thanks, > > C. > > (one comment below) > >

Re: [PATCH v10 8/9] KVM: Handle page fault for private memory

On Fri, Dec 09, 2022 at 09:01:04AM +, Fuad Tabba wrote: > Hi, > > On Fri, Dec 2, 2022 at 6:19 AM Chao Peng wrote: > > > > A KVM_MEM_PRIVATE memslot can include both fd-based private memory and > > hva-based shared memory. Architecture code (like TDX code) can tell > > whether the on-going fau

Re: [PATCH v10 6/9] KVM: Unmap existing mappings when change the memory attributes

On Fri, Dec 09, 2022 at 08:57:31AM +, Fuad Tabba wrote: > Hi, > > On Thu, Dec 8, 2022 at 11:18 AM Chao Peng wrote: > > > > On Wed, Dec 07, 2022 at 05:16:34PM +, Fuad Tabba wrote: > > > Hi, > > > > > > On Fri, Dec 2, 2022 at 6:19 AM Chao Peng > > > wrote: > > > > > > > > Unmap the existi

[PATCH] include: Don't include qemu/osdep.h

docs/devel/style.rst mandates: The "qemu/osdep.h" header contains preprocessor macros that affect the behavior of core system headers like . It must be the first include so that core system headers included by external libraries get the preprocessor macros that QEMU depends on.

[PATCH] linux-user: Add emulation for MADV_WIPEONFORK and MADV_KEEPONFORK in madvise()

Both parameters have a different value on the parisc platform, so first translate the target value into a host value for usage in the native madvise() syscall. Those parameters are often used by security sensitive applications (e.g. tor browser, boringssl, ...) which expect the call to return a pr

Re: [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check

On Sun, Dec 11, 2022 at 1:21 PM Bin Meng wrote: > > The pending register upper limit is currently set to > plic->num_sources >> 3, which is wrong, e.g.: considering > plic->num_sources is 7, the upper limit becomes 0 which fails > the range check if reading the pending register at pending_base. >

Re: [PATCH v3 0/3] target/riscv: Apply KVM policy to ISA extensions

On Fri, Dec 9, 2022 at 12:57 AM Mayuresh Chitale wrote: > > Currently the single and multi letter ISA extensions exposed to the > guest vcpu don't confirm to the KVM policies. This patchset updates the kvm > headers > and applies policies set in KVM to the extensions exposed to the guest. > > The

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: > > On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote: > > > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote: > > > > > > The htimedelta[h] CSR has impact on the VS timer comparison so we > > > should call riscv_timer_write_timecmp() whenev

Re: [RFC PATCH] RISC-V: Save mmu_idx using FIELD_DP32 not OR

On Fri, Dec 9, 2022 at 1:12 AM Christoph Muellner wrote: > > From: Christoph Müllner > > Setting flags using OR might work, but is not optimal > for a couple of reasons: > * No way grep for stores to the field MEM_IDX. > * The return value of cpu_mmu_index() is not masked > (not a real problem

Re: [PATCH 2/2] include: Include headers where needed

On Sat, Dec 10, 2022 at 11:43 PM Markus Armbruster wrote: > > A number of headers neglect to include everything they need. They > compile only if the headers they need are already included from > elsewhere. Fix that. > > Signed-off-by: Markus Armbruster Reviewed-by: Alistair Francis Alistair

Re: [PATCH 1/2] include/hw/virtio: Break inclusion loop

On Sat, Dec 10, 2022 at 11:42 PM Markus Armbruster wrote: > > hw/virtio/virtio.h and hw/virtio/vhost.h include each other. The > former doesn't actually need the latter, so drop that inclusion to > break the loop. > > Signed-off-by: Markus Armbruster Reviewed-by: Alistair Francis Alistair >

Re: [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization

On Sun, Dec 11, 2022 at 1:22 PM Bin Meng wrote: > > "hartid-base" and "priority-base" are zero by default. There is no > need to initialize them to zero again. > > Signed-off-by: Bin Meng > Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Alistair > --- > > (no changes since v1) >

Re: [PATCH v2] target/sh4: Fix TB_FLAG_UNALIGN

On Sat, Dec 10, 2022 at 07:27:46AM -0800, Guenter Roeck wrote: > Hi, > > On Thu, Sep 01, 2022 at 11:15:09AM +0100, Richard Henderson wrote: > > The value previously chosen overlaps GUSA_MASK. > > > > Rename all DELAY_SLOT_* and GUSA_* defines to emphasize > > that they are included in TB_FLAGs.

Re: [PATCH-for-8.0 0/7] hw/mips: Make gt64xxx_pci.c endian-agnostic

Am 9. Dezember 2022 15:15:26 UTC schrieb "Philippe Mathieu-Daudé" : >Respining an old/unfinished series... Add the 'cpu-little-endian' >qdev property to the GT64120 north bridge so [target-specific] >machines can set its endianness, allowing it to be endian agnostic. Hi Phil, Did you intend t

Re: [PATCH v2 for-8.0] hw/rtc/mc146818rtc: Make this rtc device target independent

Am 10. Dezember 2022 13:48:00 UTC schrieb Mark Cave-Ayland : >On 09/12/2022 11:15, Thomas Huth wrote: > >> The only reason for this code being target dependent is the apic-related >> code in rtc_policy_slew_deliver_irq(). Since these apic functions are rather >> simple, we can easily move them

Re: [PATCH-for-8.0 1/7] hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.c

Am 9. Dezember 2022 15:15:27 UTC schrieb "Philippe Mathieu-Daudé" : >From: Philippe Mathieu-Daudé > >Signed-off-by: Philippe Mathieu-Daudé >--- > hw/mips/Kconfig | 6 ++ > hw/mips/meson.build | 3 ++- > 2 files changed, 8 insertions(+), 1 deletion(-) > >diff --git a/hw/mips/Kconfig b/hw

Re: [PATCH-for-8.0 7/7] hw/mips/gt64xxx_pci: Move it to hw/pci-host/

Am 9. Dezember 2022 15:15:33 UTC schrieb "Philippe Mathieu-Daudé" : >From: Philippe Mathieu-Daudé > >The GT-64120 is a north-bridge, and it is not MIPS specific. >Move it with the other north-bridge devices. > >Signed-off-by: Philippe Mathieu-Daudé >--- > MAINTAINERS

Single system binary & Dynamic machine model (KVM developers conference call 2022-12-13)

Hi, In the last years we had few discussions on "simplifying" QEMU (system emulation / virtualization), in particular for the "management layer". Some of us are interested in having QEMU able to dynamically create machine models. Mark Burton's current approach is via a Python script which gene

Re: [PATCH v2 2/2] target/ppc: Check DEXCR on hash{st, chk} instructions

On 12/12/22 00:06, Harsh Prateek Bora wrote: On 12/9/22 11:43, Nicholas Miehlbradt wrote: Adds checks to the hashst and hashchk instructions to only execute if enabled by the relevant aspect in the DEXCR and HDEXCR. This behaviour is guarded behind TARGET_PPC64 since Power10 is currently t

Re: [PATCH-for-8.0 v2 01/11] hw/mips/bootloader: Handle buffers as opaque arrays

On 11/12/22 21:45, Philippe Mathieu-Daudé wrote: It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 55 +--- hw/

[PATCH-for-8.0 v2 07/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)

Part 2/5: Convert PCI0 MEM0 BAR setup Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 35 ++- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 30ca4e..3e80a12221 100644 --- a/hw/mips/malta.c +++

[PATCH-for-8.0 v2 10/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)

Part 5/5: Convert jumping to kernel Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 68 - 1 file changed, 11 insertions(+), 57 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 451908b217..876bc26a7f 100644 --- a/hw/mip

[PATCH-for-8.0 v2 09/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)

Part 4/5: Convert GT64120 ISD base address setup Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 40 +++- 1 file changed, 7 insertions(+), 33 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 16161b1b03..451908b217 100644 --- a/hw/

[PATCH-for-8.0 v2 04/11] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 36 ++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 3e1e73360f..9fc926d83f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloa

[PATCH-for-8.0 v2 06/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)

Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader helper to set BAR registers") converted write_bootloader(), convert the equivalent write_bootloader_nanomips(), allowing us to modify the bootloader code more easily in the future. Part 1/5: Convert PCI0 MEM1 BAR setup Signed-off-

[PATCH-for-8.0 v2 11/11] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()

Merge common code shared between write_bootloader() and write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 155 +--- 1 file changed, 56 insertions(+), 99 deletions(-) diff --git

[PATCH-for-8.0 v2 08/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)

Part 3/5: Convert PCI0 I/O BAR setup Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 40 1 file changed, 8 insertions(+), 32 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 3e80a12221..16161b1b03 100644 --- a/hw/mips/malta.c

[PATCH-for-8.0 v2 01/11] hw/mips/bootloader: Handle buffers as opaque arrays

It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 55 +--- hw/mips/malta.c | 19 +++-- include

[PATCH-for-8.0 v2 05/11] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 9fc926d83f..1dd6ef2096 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -129,7 +129,17 @

[PATCH-for-8.0 v2 03/11] hw/mips/bootloader: Implement nanoMIPS SW opcode generator

Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 20 +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 0035f37335..3e1e73360f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -143,9 +

[PATCH-for-8.0 v2 00/11] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

Bernhard posted his "Consolidate PIIX south bridges" v3 series: https://lore.kernel.org/qemu-devel/20221204190553.3274-1-shen...@gmail.com/ However in order to simplify it, on the Malta board we need to set the PIIX IRQC[A:D] routing values via the embedded bootloader (used when no external BIOS i

[PATCH-for-8.0 v2 02/11] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 24 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 21ffd4d772..0035f37335 100644 --- a/hw/mips/bootloader.c +

Re: [PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

On 11/12/22 11:40, Jiaxun Yang wrote: 2022年12月10日 15:55，Philippe Mathieu-Daudé 写道： Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index cc

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

On 11/12/22 17:24, Richard Henderson wrote: On 12/10/22 10:02, Philippe Mathieu-Daudé wrote: On 10/12/22 16:55, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé ---   hw/mips/bootloader.c | 24 +++-   1 file changed, 23 insertions(+), 1 deletion(-) diff -

Re: [PATCH-for-8.0 1/7] hw/mips/bootloader: Handle buffers as opaque arrays

On 11/12/22 01:16, BALATON Zoltan wrote: On Sat, 10 Dec 2022, Philippe Mathieu-Daudé wrote: It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 55

Re: [PATCH v2 2/2] target/ppc: Check DEXCR on hash{st, chk} instructions

On 12/9/22 11:43, Nicholas Miehlbradt wrote: Adds checks to the hashst and hashchk instructions to only execute if enabled by the relevant aspect in the DEXCR and HDEXCR. This behaviour is guarded behind TARGET_PPC64 since Power10 is currently the only implementation which has the DEXCR. Rev

Re: [PATCH v2 1/2] target/ppc: Implement the DEXCR and HDEXCR

On 12/9/22 11:43, Nicholas Miehlbradt wrote: Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the

[PATCH v20 10/10] virtio-pci: add support for configure interrupt

Add process to handle the configure interrupt, The function's logic is the same with vq interrupt.Add extra process to check the configure interrupt Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 118 +++-- include/hw/virtio/virtio-pci.h | 4 +- 2 file

[PATCH v20 04/10] vhost: introduce new VhostOps vhost_set_config_call

This patch introduces new VhostOps vhost_set_config_call. This function allows the qemu to set the config event fd to kernel driver. Signed-off-by: Cindy Lu --- include/hw/virtio/vhost-backend.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/virtio/vhost-backend.h b/include/h

[PATCH v20 07/10] vhost: add support for configure interrupt

Add functions to support configure interrupt. The configure interrupt process will start in vhost_dev_start and stop in vhost_dev_stop. Also add the functions to support vhost_config_pending and vhost_config_mask. Signed-off-by: Cindy Lu --- hw/virtio/vhost.c | 78 ++

[PATCH v20 03/10] virtio-pci: decouple the single vector from the interrupt process

To reuse the interrupt process in configure interrupt Need to decouple the single vector from the interrupt process. We add new function kvm_virtio_pci_vector_use_one and _release_one. These functions are used for the single vector, the whole process will finish in the loop with vq number. Signed-

[PATCH v20 09/10] virtio-mmio: add support for configure interrupt

Add configure interrupt support in virtio-mmio bus. add function to set configure guest notifier. Signed-off-by: Cindy Lu --- hw/virtio/virtio-mmio.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index d240efef9

[PATCH v20 00/10] vhost-vdpa: add support for configure interrupt

These patches introduced the support for configure interrupt These codes are tested on x86_64 and aarch64 platforms. the tested on vp-vdpa/vdpa_sim_net /vhost/vhost_user/testpmd, with/without irqfd. Tested in virtio-pci bus and virtio-mmio bus Change in v2: Add support for virtio-mmio bus a

[PATCH v20 08/10] virtio-net: add support for configure interrupt

Add functions to support configure interrupt in virtio_net Add the functions to support vhost_net_config_pending and vhost_net_config_mask. Signed-off-by: Cindy Lu --- hw/net/vhost_net.c | 9 + hw/net/virtio-net.c | 4 ++-- include/net/vhost_net.h | 2 ++ 3 files changed, 13 ins

[PATCH v20 06/10] virtio: add support for configure interrupt

Add the functions to support the configure interrupt in virtio The function virtio_config_guest_notifier_read will notify the guest if there is an configure interrupt. The function virtio_config_set_guest_notifier_fd_handler is to set the fd hander for the notifier Signed-off-by: Cindy Lu --- hw

[PATCH v20 02/10] virtio-pci: decouple notifier from interrupt process

To reuse the notifier process. We add the virtio_pci_get_notifier to get the notifier and vector. The INPUT for this function is IDX, The OUTPUT is the notifier and the vector Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 88 +++--- 1 file changed, 57 i

[PATCH v20 01/10] virtio: introduce macro VIRTIO_CONFIG_IRQ_IDX

To support configure interrupt for vhost-vdpa Introduce VIRTIO_CONFIG_IRQ_IDX -1 as configure interrupt's queue index, Then we can reuse the functions guest_notifier_mask and guest_notifier_pending. Add the check of queue index in these drivers, if the driver does not support configure interrupt, t

[PATCH v20 05/10] vhost-vdpa: add support for config interrupt

Add new call back function in vhost-vdpa, The function vhost_set_config_call can set the event fd to kernel. This function will be called in the vhost_dev_start and vhost_dev_stop Signed-off-by: Cindy Lu --- hw/virtio/trace-events | 1 + hw/virtio/vhost-vdpa.c | 8 2 files changed, 9 in

Re: [PATCH 5/9] ui: Move QMP commands from monitor to new ui/ui-qmp-cmds.c

Markus Armbruster writes: > Markus Armbruster writes: > >> This moves these commands from MAINTAINERS section "Human >> Monitor (HMP)" to "Graphics". Make that 'section "QMP"', of course. >> Command add-client applies to socket character devices in addition to >> display devices. Move it anyw

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

On 12/10/22 10:02, Philippe Mathieu-Daudé wrote: On 10/12/22 16:55, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé ---   hw/mips/bootloader.c | 24 +++-   1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloa

Re: [PATCH-for-8.0 3/7] hw/mips/bootloader: Implement nanoMIPS NOP opcode

On 12/10/22 09:54, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 3a4573118c..7f7d93

Re: [PATCH v2 19/27] target/s390x: Introduce help_goto_indirect

On 11/12/22 16:27, Richard Henderson wrote: Add a small helper to handle unconditional indirect jumps. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH-for-8.0 2/7] hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode generator

On 12/10/22 09:54, Philippe Mathieu-Daudé wrote: -static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) +static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32) { /* R6: It's a alias of AUI with RS = 0 */ -bl_gen_i_type(p, 0x0f, 0, rt, imm); +assert(imm32 <= UINT16_MAX); +

Re: [PATCH v2 15/27] target/s390x: Add disp argument to update_psw_addr

On 11/12/22 16:27, Richard Henderson wrote: Rename to update_psw_addr_disp at the same time. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) Reviewed-by: Philipp

Re: [PATCH v2 13/27] target/s390x: Use ilen instead in branches

On 11/12/22 16:27, Richard Henderson wrote: Remove the remaining uses of pc_tmp, and remove the variable. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) Reviewed-by: Phili

Re: [PATCH v2 07/27] target/s390x: Change help_goto_direct to work on displacements

On 11/12/22 16:27, Richard Henderson wrote: In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) Reviewed-by

Re: [PATCH v2 04/27] target/s390x: Use tcg_constant_* in translate_vx.c.inc

On 11/12/22 16:27, Richard Henderson wrote: In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. In gen_acc, this fixes a leak. Reviewed-by: Ilya Leoshkevich

Re: [PATCH v2 03/27] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34

On 11/12/22 16:27, Richard Henderson wrote: Return a constant or NULL, which means the free may be removed from all callers of fpinst_extract_m34. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 26 +- 1 file changed,

Re: [PATCH v2 02/27] target/s390x: Use tcg_constant_* for DisasCompare

On 11/12/22 16:27, Richard Henderson wrote: The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg

[PATCH v2 20/27] target/s390x: Split per_branch

Split into per_branch_dest and per_branch_disp, which can be used for direct and indirect. In preperation for TARGET_TB_PCREL, call per_branch_* before indirect branches. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 30 +-

[PATCH v2 16/27] target/s390x: Don't set gbea for user-only

The rest of the per_* functions have this ifdef; this one seemed to be missing. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index

[PATCH v2 14/27] target/s390x: Assert masking of psw.addr in cpu_get_tb_cpu_state

When changing modes via SAM, we raise a specification exception if the new PC is out of range. The masking in s390x_tr_init_disas_context was too late to be correct, but may be removed. Add a debugging assert in cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson --- target/s390x/cpu.h

[PATCH v2 07/27] target/s390x: Change help_goto_direct to work on displacements

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg

[PATCH v2 10/27] target/s390x: Use gen_psw_addr_disp in pc_to_link_info

This is slightly more complicated than a straight displacement for 31 and 24-bit modes. Dont bother with a cant-happen assert. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 21 - 1 file changed, 12 insertions(+), 9 deletio

[PATCH v2 22/27] target/s390x: Split per_breaking_event from per_branch_*

This allows us to update gbea before other updates to psw_addr, which will be important for TARGET_TB_PCREL. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/s390x/tc

[PATCH v2 23/27] target/s390x: Remove PER check from use_goto_tb

While it is common for the PC update to happen in the shadow of a goto_tb, it is not required to be there. By moving it before the goto_tb, we can also place the call to helper_per_branch there, and then afterward chain to the next tb. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderso

[PATCH v2 04/27] target/s390x: Use tcg_constant_* in translate_vx.c.inc

In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. In gen_acc, this fixes a leak. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target

[PATCH v2 06/27] tests/tcg/s390x: Add sam.S

From: Ilya Leoshkevich Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221129015328.55439-1-...@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/sam.S | 67

[PATCH v2 01/27] target/s390x: Use tcg_constant_* in local contexts

Replace tcg_const_* with tcg_constant_* in contexts where the free to remove is nearby. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 416 +-- 1 file changed, 149 insertions(

[PATCH v2 27/27] target/s390x: Enable TARGET_TB_PCREL

Signed-off-by: Richard Henderson --- target/s390x/cpu-param.h | 1 + target/s390x/cpu.c | 12 + target/s390x/tcg/translate.c | 86 +++- 3 files changed, 68 insertions(+), 31 deletions(-) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-p

[PATCH v2 26/27] target/s390x: Pass original r2 register to BCR

We do not modify any general-purpose registers in BCR, which means that we may be able to avoid saving the value across a branch. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/translate.c | 10 ++ 2 file

[PATCH v2 09/27] target/s390x: Remove pc argument to pc_to_link_into

All callers pass s->pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/transla

[PATCH v2 03/27] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34

Return a constant or NULL, which means the free may be removed from all callers of fpinst_extract_m34. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 26 +- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/t

[PATCH v2 05/27] tests/tcg/s390x: Add bal.S

From: Ilya Leoshkevich Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221103130011.2670186-1-...@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/bal.S | 24 ++

[PATCH v2 17/27] target/s390x: Introduce per_enabled

Hoist the test of FLAG_MASK_PER to a helper. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c i

[PATCH v2 13/27] target/s390x: Use ilen instead in branches

Remove the remaining uses of pc_tmp, and remove the variable. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/transl

[PATCH v2 02/27] target/s390x: Use tcg_constant_* for DisasCompare

The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 44 ++---

[PATCH v2 08/27] target/s390x: Introduce gen_psw_addr_disp

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 69 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/target/s390x/tcg/tra

[PATCH v2 15/27] target/s390x: Add disp argument to update_psw_addr

Rename to update_psw_addr_disp at the same time. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate

[PATCH v2 12/27] target/s390x: Use gen_psw_addr_disp in op_sam

Complicated because we may now require a runtime jump. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 40 +--- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target

[PATCH v2 24/27] target/s390x: Fix successful-branch PER events

From: Ilya Leoshkevich The branching code sets per_perc_atmid, but afterwards it does goto_tb/exit_tb, so per_check_exception() added by translate_one() is not reached. Fix by raising PER exception in per_branch(). Signed-off-by: Ilya Leoshkevich Message-Id: <20221130174610.434590-1-...@linux.

[PATCH v2 19/27] target/s390x: Introduce help_goto_indirect

Add a small helper to handle unconditional indirect jumps. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 9e84f706d5..7506

[PATCH v2 25/27] tests/tcg/s390x: Add per.S

From: Ilya Leoshkevich Add a small test to avoid regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221130174610.434590-2-...@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/per.S | 55 +

[PATCH v2 21/27] target/s390x: Simplify help_branch

Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. This will be help

[PATCH v2 11/27] target/s390x: Use gen_psw_addr_disp in save_link_info

Trivial but non-mechanical conversion away from pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/t

[PATCH v2 00/27] target/s390x: pc-relative translation blocks

This is the S390 specific changes required to reduce the amount of translation for address space randomization. Begin with some generic cleanups, then prepare by using displacements instead of addresses when possible, then add some tcg infrastructure to avoid a code gen ugly, then finalize the con

[PATCH v2 18/27] target/s390x: Disable conditional branch-to-next for PER

For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/

Re: [PATCH v13 4/7] s390x/cpu_topology: CPU topology migration

Sorry, I made an error in this patch that break the migration. On 12/8/22 10:44, Pierre Morel wrote: + +const VMStateDescription vmstate_cpu_topology = { +.name = "cpu_topology", +.version_id = 1, +.post_load = cpu_topology_postload, +.minimum_version_id = 1, +.needed = cpu_

Re: [PATCH for-8.0] hw/rtc/mc146818rtc: Make this rtc device target independent

On 11/12/2022 10:27, Bernhard Beschow wrote: Am 7. Dezember 2022 17:47:48 UTC schrieb Mark Cave-Ayland : On 07/12/2022 16:20, Bernhard Beschow wrote: Am 7. Dezember 2022 15:29:00 UTC schrieb Mark Cave-Ayland : On 06/12/2022 20:06, Thomas Huth wrote: The only code that is really, really t

[PATCH] virtiofsd: support setting multiple request virtqueues

Add an option '-o num_request_queues' to configure the queue number, currently the total number of vqs should be (1 hiprio queue + num_request_queues). The code is based on Connor's previous version in the virtio-fs mailing-list [1], but change the semantic of the new option from total queue numbe

Re: [PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

> 2022年12月10日 15:55，Philippe Mathieu-Daudé 写道： > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/mips/bootloader.c | 25 - > 1 file changed, 24 insertions(+), 1 deletion(-) > > diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c > index cc3df385df..541b59bf84 1

Re: [PATCH-for-8.0 4/7] hw/mips/bootloader: Implement nanoMIPS LUI opcode

> 2022年12月10日 16:01，Philippe Mathieu-Daudé 写道： > > On 10/12/22 16:54, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/mips/bootloader.c | 29 ++--- >> 1 file changed, 26 insertions(+), 3 deletions(-) >> diff --git a/hw/mips/bootload

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