On Tue, Dec 13, 2022 at 11:51:25PM +, Huang, Kai wrote:
> On Fri, 2022-12-02 at 14:13 +0800, Chao Peng wrote:
> >
> > - /* flags is currently not used. */
> > + /* 'flags' is currently not used. */
> > if (attrs->flags)
> > return -EINVAL;
>
> Unintended code change.
Yea
On Tue, Dec 13, 2022 at 11:49:13PM +, Huang, Kai wrote:
> >
> > memfd_restricted() itself is implemented as a shim layer on top of real
> > memory file systems (currently tmpfs). Pages in restrictedmem are marked
> > as unmovable and unevictable, this is required for current confidential
> > u
On Sun, Dec 18, 2022 at 01:06:49AM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> docs/about/deprecated.rst | 13 -
> docs/about/removed-features.rst | 13 +
> hw/i386/sgx.c | 15 ++-
> qapi/misc-target.json
Putting zoned/non-zoned BlockDrivers on top of each other is not
allowed.
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Hannes Reinecke
Reviewed-by: Dmitry Fomichev
---
block.c | 19 +++
block/file-posix.c | 12 +
raw-format driver usually sits on top of file-posix driver. It needs to
pass through requests of zone commands.
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Damien Le Moal
Reviewed-by: Hannes Reinecke
Reviewed-by: Dmitry Fomichev
---
block/raw-format.c | 13 +
Add a new zoned_host_device BlockDriver. The zoned_host_device option
accepts only zoned host block devices. By adding zone management
operations in this new BlockDriver, users can use the new block
layer APIs including Report Zone and four zone management operations
(open, close, finish, reset, re
Use get_sysfs_str_val() to get the string value of device
zoned model. Then get_sysfs_zoned_model() can convert it to
BlockZoneModel type of QEMU.
Use get_sysfs_long_val() to get the long value of zoned device
information.
Signed-off-by: Sam Li
Reviewed-by: Hannes Reinecke
Reviewed-by: Stefan H
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Damien Le Moal
Reviewed-by: Hannes Reinecke
---
include/block/block-common.h | 43
1 file changed, 43 insertions(+)
diff --git a/include/block/block-common.h b/include/block/block-common.h
ind
Zoned Block Devices (ZBDs) devide the LBA space to block regions called zones
that are larger than the LBA size. It can only allow sequential writes, which
reduces write amplification in SSD, leading to higher throughput and increased
capacity. More details about ZBDs can be found at:
https://zone
Am 18.12.22 um 21:26 schrieb Christian Schoenebeck:
On Sunday, December 18, 2022 6:15:29 PM CET Volker Rümelin wrote:
Some emulated audio devices allow guests to select very low
sample rates that the audio subsystem doesn't support. The lowest
supported sample rate depends on the audio backend u
On 18/12/22 23:44, Richard Henderson wrote:
On 12/18/22 13:49, Philippe Mathieu-Daudé wrote:
+ found:
memset(op, 0, offsetof(TCGOp, link));
op->opc = opc;
- s->nb_ops++;
+ op->nargs = nargs;
We can move this assignation before the 'found' label.
No, affected by the memset.
On 18/12/22 23:39, Strahinja Jankovic wrote:
Hi,
On Sun, Dec 18, 2022 at 11:23 PM Philippe Mathieu-Daudé
wrote:
On 18/12/22 23:12, Strahinja Jankovic wrote:
Hi,
On Sun, Dec 18, 2022 at 11:07 PM Philippe Mathieu-Daudé
wrote:
On 18/12/22 22:19, Strahinja Jankovic wrote:
This patch adds mi
On 18/12/22 23:57, Strahinja Jankovic wrote:
Hi,
I just looked around a bit more. Would OpenWrt image be acceptable?
Sure.
It looks like there are releases for cubieboard that are kept for a
longer time, and I just checked that they work properly, so I could
add them to the acceptance test.
On Fri, Dec 16, 2022 at 09:39:19PM +, Peter Maydell wrote:
> On Fri, 16 Dec 2022 at 19:11, Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 12/13/22 10:51, Peter Maydell wrote:
> > > On Tue, 13 Dec 2022 at 12:52, Philippe Mathieu-Daudé
> > > wrote:
> > >>
> > >> The tswap64() calls introd
Kindly ping for any comments:)
BR,
Lei
On 11/2/2022 4:52 PM, Wang, Lei wrote:
> This series aims to add a new CPU model SapphireRapids, and tries to
> address the problem stated in
> https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b267be9afd2fb3
Paolo Bonzini writes:
> On 12/15/22 07:49, Markus Armbruster wrote:
>>> linux-user/ does not use coroutines, so I'd like to avoid that it
>>> includes qemu/coroutine.h.
>> They include it even before the patch, via lockable.h.
>
> They do but there's a difference between "including lockable.h and
Before this commit, when GDB attached an OS working on QEMU, order of FPU
stack registers printed by GDB command 'info float' was wrong. There was a
bug causing the problem in 'g' packets sent by QEMU to GDB. The packets have
values of registers of machine emulated by QEMU containing FPU stack
regi
Before this commit, when GDB attached an OS working on QEMU, order of FPU
stack registers printed by GDB command 'info float' was wrong. There was a
bug causing the problem in 'g' packets sent by QEMU to GDB. The packets have
values of registers of machine emulated by QEMU containing FPU stack
regi
From: Bin Meng
sstatus register dump is currently missing in riscv_cpu_dump_state().
As sstatus is a copy of mstatus, which is described in the priv spec,
it seems redundant to print the same information twice.
Add some comments for this to let people know this is intentional.
Signed-off-by: Bi
From: Bin Meng
Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM
From: Wilfred Mallawa
Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20221025043335.339815-3-wilfred.mall...@
From: Conor Dooley
The Fabric Interconnect Controllers provide interfaces between the FPGA
fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered
0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and
does not show up on the MSS memory map. FIC4 is dedicated to th
From: Conor Dooley
The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usually connected to a flash chip, that is used for
stori
From: Mayuresh Chitale
This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-I
From: Alistair Francis
The following changes since commit 562d4af32ec2213061f844b3838223fd7711b56a:
Merge tag 'pull-loongarch-20221215' of https://gitlab.com/gaosong/qemu into
staging (2022-12-18 13:53:29 +)
are available in the Git repository at:
https://github.com/alistair23/qemu.gi
From: Bin Meng
H-mode has been removed since priv spec 1.10. Drop it.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211030829.802437-6-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
include/hw/intc/sifive_plic.h | 1 -
hw/intc/s
From: Bin Meng
The realize() callback has an errp for us to propagate the error up.
While we are here, correct the wrong multi-line comment format.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221211030829.802437-8-bm...@tinylab.org>
From: Anup Patel
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id: <20221108125703.1463577-2-apa...@ventanamicro.com>
Signed-off-by:
From: Richard Henderson
When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.
Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the r
From: Bin Meng
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Bl
From: Bin Meng
At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:
s->bitfield_words = (s->num_sources + 31) >> 5;
if the we don't configure "num-sources" property its defaul
From: Wilfred Mallawa
use the `FIELD32_1CLEAR` macro to implement register
`rw1c` functionality to `ibex_spi`.
This change was tested by running the `SPI_HOST` from TockOS.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221017054950.317584-3-wilfred.mall...@openso
From: Jim Shu
let tlb_fill() function also increments PMU counter when it is from
two-stage translation, so QEMU could also monitor these PMU events when
CPU runs in VS/VU mode (like running guest OS).
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Message-Id: <20221123090635.6574-1-jim.
From: Bin Meng
Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.
[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pd
From: LIU Zhiwei
When QEMU is not in icount mode, execute instruction one by one. The
tdata1 can be read directly.
When QEMU is in icount mode, use a timer to simulate the itrigger. The
tdata1 may be not right because of lazy update of count in tdata1. Thus,
We should pack the adjusted count int
From: Bin Meng
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
the IBEX PLIC model was replaced with the SiFive PLIC model in the
'opentitan' machine but we forgot the add the dependency there.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alis
From: LIU Zhiwei
Avoid calling riscv_itrigger_enabled() when calculate the tbflags.
As the itrigger enable status can only be changed when write
tdata1, migration load or itrigger fire, update env->itrigger_enabled
at these places.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Messag
From: LIU Zhiwei
The max count in itrigger can be 0x3FFF, which will cause a no trivial
translation and execution overload.
When icount is enabled, QEMU provides API that can fetch guest
instruction number. Thus, we can set an timer for itrigger with
the count as deadline.
Only when timer expir
From: Bin Meng
At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.
Note
From: Jim Shu
If the number of interrupt is not multiple of 32, PLIC will have
out-of-bound access to source_priority array. Compute the number of
interrupt in the last word to avoid this out-of-bound access of array.
Signed-off-by: Jim Shu
Reviewed-by: Bin Meng
Message-Id: <20221127165753.305
From: Christoph Muellner
This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore, we
From: Wilfred Mallawa
This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.
Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note: OpenT
From: Bin Meng
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault ex
From: Bin Meng
At present the PLIC config parser can only handle legal config string
like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
given the parser won't get the correct configuration.
This commit improves the config parser to make it more robust.
Signed-off-by: Bin Meng
A
From: Bin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().
Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.
Signed-off-by: Bin
From: Richard Henderson
Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
From: Bin Meng
At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211
From: Bin Meng
Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
leaving M-mode.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20221207090037.281452-2-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
target/riscv/op_helper.c | 6 ++
1 file change
From: Bin Meng
"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211030829.802437-15-bm...@tinylab.org>
Signed-off-by: Alistair Francis
From: Bin Meng
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().
Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
Signed-off-by: Bi
From: Richard Henderson
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-Id: <2
From: Bin Meng
Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.
We use the value of G002 and G003, so it is 53 (including source 0).
[1] G000 manual:
https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c
From: Mayuresh Chitale
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <20
From: Frédéric Pétrot
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object memory-backend-ram,id=
From: Bin Meng
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Wilfred Mallawa
Message-Id: <20221211030829.802437-4-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
From: Atish Patra
The imsic DT binding[1] has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.
Get rid of the unused dt property which may lead to confusion.
[1]
https://lore.kernel.org/lkml/2022044207.1478350-5-apa..
From: Bin Meng
There are 2 paths in helper_sret() and the same mstatus update codes
are replicated. Extract the common parts to simplify it a little bit.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20221207090037.281452-1-bm...@tinylab.org>
Signed-off-by: Alistair Franci
From: Conor Dooley
On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
Icicle Kit Reference Design v2022.09 or later this is/will be
From: Bin Meng
PLIC is not included in the 'spike' machine.
Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20221211030829.802437-5-bm...@tinylab.org>
Signed-off-by: Alistair Francis
---
hw/riscv/spike.c | 1 -
1 file changed, 1 deletion(-)
d
From: Richard Henderson
There was a typo using opc_addi instead of opc_add with the
two registers. While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Hen
From: Mayuresh Chitale
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
Reviewed-by
From: Wilfred Mallawa
Adds a helper macro that implements the register `w1c`
functionality.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
If ANY bits of the specified `FIELD` is set
then the respective field is cleared and returned to `data`.
If the field is cleared (0), then no chang
From: LIU Zhiwei
When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.
Translate the guest code in a way that each TB only has one instruction.
After executing the instruction, decrease the count by 1 until it reaches 0
where the itrigger fires.
Note tha
From: LIU Zhiwei
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
is an pmp rule, valid r
On 12/16/2022 6:30 PM, David Hildenbrand wrote:
> On 16.12.22 09:52, David Hildenbrand wrote:
>> On 16.12.22 07:22, Chenyi Qiang wrote:
>>> vmem->bitmap indexes the memory region of the virtio-mem backend at a
>>> granularity of block_size. To calculate the index of target section
>>> offset,
>>
Hi,
I just looked around a bit more. Would OpenWrt image be acceptable?
It looks like there are releases for cubieboard that are kept for a
longer time, and I just checked that they work properly, so I could
add them to the acceptance test.
Best regards,
Strahinja
On Sun, Dec 18, 2022 at 11:34 P
On 12/18/22 13:49, Philippe Mathieu-Daudé wrote:
+ found:
memset(op, 0, offsetof(TCGOp, link));
op->opc = opc;
- s->nb_ops++;
+ op->nargs = nargs;
We can move this assignation before the 'found' label.
No, affected by the memset.
r~
Hi,
On Sun, Dec 18, 2022 at 11:23 PM Philippe Mathieu-Daudé
wrote:
>
> On 18/12/22 23:12, Strahinja Jankovic wrote:
> > Hi,
> >
> > On Sun, Dec 18, 2022 at 11:07 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 18/12/22 22:19, Strahinja Jankovic wrote:
> >>> This patch adds minimal support for
Hi,
On Sun, Dec 18, 2022 at 11:17 PM Philippe Mathieu-Daudé
wrote:
>
> On 18/12/22 22:19, Strahinja Jankovic wrote:
> > This patch series adds missing Allwinner A10 modules needed for
> > successful SPL boot:
> > - Clock controller module
> > - DRAM controller
> > - I2C0 controller (added also f
> On Dec 19, 2022, at 12:07 AM, Khem Raj wrote:
>
> 64bit off_t is already in use since build uses _FILE_OFFSET_BITS=64
> already. Using lseek/off_t also makes it work with latest musl without
> using _LARGEFILE64_SOURCE macro. This macro is implied with _GNU_SOURCE
> when using glibc but not
On 18/12/22 23:12, Strahinja Jankovic wrote:
Hi,
On Sun, Dec 18, 2022 at 11:07 PM Philippe Mathieu-Daudé
wrote:
On 18/12/22 22:19, Strahinja Jankovic wrote:
This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID re
On 18/12/22 22:19, Strahinja Jankovic wrote:
This patch series adds missing Allwinner A10 modules needed for
successful SPL boot:
- Clock controller module
- DRAM controller
- I2C0 controller (added also for Allwinner H3 since it is the same)
- AXP-209 connected to I2C0 bus
It also updates Allwi
Hi,
On Sun, Dec 18, 2022 at 10:59 PM Philippe Mathieu-Daudé
wrote:
>
> On 18/12/22 22:19, Strahinja Jankovic wrote:
> > This patch enables copying of SPL from MMC if `-kernel` parameter is not
> > passed when starting QEMU. SPL is copied to SRAM_A.
> >
> > The approach is reused from Allwinner H3
Hi,
On Sun, Dec 18, 2022 at 11:07 PM Philippe Mathieu-Daudé
wrote:
>
> On 18/12/22 22:19, Strahinja Jankovic wrote:
> > This patch adds minimal support for AXP-209 PMU.
> > Most important is chip ID since U-Boot SPL expects version 0x1. Besides
> > the chip ID register, reset values for two more
On 18/12/22 23:07, Khem Raj wrote:
64bit off_t is already in use since build uses _FILE_OFFSET_BITS=64
already. Using lseek/off_t also makes it work with latest musl without
using _LARGEFILE64_SOURCE macro. This macro is implied with _GNU_SOURCE
when using glibc but not with musl.
Signed-off-by:
Hi,
On Sun, Dec 18, 2022 at 11:02 PM Philippe Mathieu-Daudé
wrote:
>
> On 18/12/22 22:19, Strahinja Jankovic wrote:
> > TWI (I2C) is supported so docs are updated for Cubieboard and
> > Orangepi-PC board.
> >
> > Signed-off-by: Strahinja Jankovic
> > ---
> > docs/system/arm/cubieboard.rst | 1
64bit off_t is already in use since build uses _FILE_OFFSET_BITS=64
already. Using lseek/off_t also makes it work with latest musl without
using _LARGEFILE64_SOURCE macro. This macro is implied with _GNU_SOURCE
when using glibc but not with musl.
Signed-off-by: Khem Raj
Cc: Michael S. Tsirkin
CC
On 18/12/22 22:19, Strahinja Jankovic wrote:
This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID register, reset values for two more registers used by A10
U-Boot SPL are covered.
Signed-off-by: Strahinja Jankovic
-
On 18/12/22 22:19, Strahinja Jankovic wrote:
TWI (I2C) is supported so docs are updated for Cubieboard and
Orangepi-PC board.
Signed-off-by: Strahinja Jankovic
---
docs/system/arm/cubieboard.rst | 1 +
docs/system/arm/orangepi.rst | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs
On 18/12/22 22:19, Strahinja Jankovic wrote:
This patch enables copying of SPL from MMC if `-kernel` parameter is not
passed when starting QEMU. SPL is copied to SRAM_A.
The approach is reused from Allwinner H3 implementation.
Tested with Armbian and custom Yocto image.
Signed-off-by: Strahinj
On 18/12/22 22:19, Strahinja Jankovic wrote:
SPL Boot for Cubieboard expects AXP-209 connected to I2C0 bus.
Signed-off-by: Strahinja Jankovic
---
hw/arm/cubieboard.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 5e3372a3c7..afc79804
On 18/12/22 22:18, Philippe Mathieu-Daudé wrote:
From: Richard Henderson
We have been allocating a worst case number of arguments
to support calls. Instead, allow the size to vary.
By default leave space for 4 args, to maximize reuse,
but allow calls to increase the number of args to 32.
Sign
On 18/12/22 22:18, Philippe Mathieu-Daudé wrote:
In order to have variable size allocated TCGOp, pass the number
of arguments we use (and would allocate) up to tcg_op_alloc().
This alters tcg_emit_op(), tcg_op_insert_before() and
tcg_op_insert_after() prototypes.
In tcg_op_alloc() ensure the nu
On 13/12/22 22:25, Richard Henderson wrote:
The first thing that temp_sync does is check mem_coherent,
so there's no need for the caller to do so.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daud
On 13/12/22 22:25, Richard Henderson wrote:
Use the official extend/extract functions instead of routines
that will shortly be internal to tcg.
Cc: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 21 -
1 file changed, 4 insertions(+), 17
I forgot to add Philippe Mathieu-Daudé in CC for this patch, so I'm
fixing it now.
Best regards,
Strahinja Jankovic
On Sun, Dec 18, 2022 at 10:19 PM Strahinja Jankovic
wrote:
>
> This patch adds minimal support for AXP-209 PMU.
> Most important is chip ID since U-Boot SPL expects version 0x1. Be
On 13/12/22 22:25, Richard Henderson wrote:
The function pointer is immediately after the output and input
operands; no need to search.
Signed-off-by: Richard Henderson
---
Cc: Alex Bennée
---
accel/tcg/plugin-gen.c | 29 +++--
1 file changed, 11 insertions(+), 18 de
On 13/12/22 22:25, Richard Henderson wrote:
There is only one use, and BLR is perhaps even more
self-documentary than CALLR.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
This patch enables copying of SPL from MMC if `-kernel` parameter is not
passed when starting QEMU. SPL is copied to SRAM_A.
The approach is reused from Allwinner H3 implementation.
Tested with Armbian and custom Yocto image.
Signed-off-by: Strahinja Jankovic
Reviewed-by: Niek Linnenbank
---
SPL Boot for Cubieboard expects AXP-209 connected to I2C0 bus.
Signed-off-by: Strahinja Jankovic
---
hw/arm/cubieboard.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 5e3372a3c7..afc7980414 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/
From: Richard Henderson
We have been allocating a worst case number of arguments
to support calls. Instead, allow the size to vary.
By default leave space for 4 args, to maximize reuse,
but allow calls to increase the number of args to 32.
Signed-off-by: Richard Henderson
[PMD: Split patch in
During SPL boot several Clock Controller Module (CCM) registers are
read, most important are PLL and Tuning, as well as divisor registers.
This patch adds these registers and initializes reset values from user's
guide.
Signed-off-by: Strahinja Jankovic
Reviewed-by: Niek Linnenbank
---
hw/arm/
This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID register, reset values for two more registers used by A10
U-Boot SPL are covered.
Signed-off-by: Strahinja Jankovic
---
hw/arm/Kconfig | 1 +
hw/mis
TWI (I2C) is supported so docs are updated for Cubieboard and
Orangepi-PC board.
Signed-off-by: Strahinja Jankovic
---
docs/system/arm/cubieboard.rst | 1 +
docs/system/arm/orangepi.rst | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubie
During SPL boot several DRAM Controller registers are used. Most
important registers are those related to DRAM initialization and
calibration, where SPL initiates process and waits until certain bit is
set/cleared.
This patch adds these registers, initializes reset values from user's
guide and upd
This patch series adds missing Allwinner A10 modules needed for
successful SPL boot:
- Clock controller module
- DRAM controller
- I2C0 controller (added also for Allwinner H3 since it is the same)
- AXP-209 connected to I2C0 bus
It also updates Allwinner A10 emulation so SPL is copied from attach
In order to have variable size allocated TCGOp, pass the number
of arguments we use (and would allocate) up to tcg_op_alloc().
This alters tcg_emit_op(), tcg_op_insert_before() and
tcg_op_insert_after() prototypes.
In tcg_op_alloc() ensure the number of arguments is in range.
Signed-off-by: Rich
This patch implements Allwinner TWI/I2C controller emulation. Only
master-mode functionality is implemented.
The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
first part enabling the TWI/I2C bus operation.
Since both Allwinner A10 and H3 use the same module, it is added
Splitting this patch in 2 to ease review.
Philippe Mathieu-Daudé (1):
tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*()
Richard Henderson (1):
tcg: Vary the allocation size for TCGOp
accel/tcg/plugin-gen.c | 11 ---
include/exec/helper-head.h | 2 --
include/tcg/tc
On 12/18/22 09:15, Volker Rümelin wrote:
Replace audio_calloc() with the equivalent g_new0().
With a n_structs argument >= 1, g_new0() never returns NULL.
Also remove the unnecessary NULL checks.
Signed-off-by: Volker Rümelin
---
audio/audio_template.h | 23 ++-
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