On Thu, Dec 22, 2022 at 01:08:12PM +0100, Markus Armbruster wrote:
> docs/devel/style.rst mandates:
>
> The "qemu/osdep.h" header contains preprocessor macros that affect
> the behavior of core system headers like . It must be
> the first include so that core system headers included
On Thu, Dec 22, 2022 at 01:08:09PM +0100, Markus Armbruster wrote:
> Back in 2016, we discussed[1] rules for headers, and these were
> generally liked:
>
> 1. Have a carefully curated header that's included everywhere first. We
>got that already thanks to Peter: osdep.h.
>
> 2. Headers
On Thu, Jan 5, 2023 at 6:43 AM Philippe Mathieu-Daudé wrote:
>
> pflash_cfi01_register() hides an implicit sysbus mapping of
> MMIO region #0. This is not practical in a heterogeneous world
> where multiple cores use different address spaces. In order to
> remove to remove pflash_cfi01_register()
On Thu, Jan 5, 2023 at 6:16 AM Philippe Mathieu-Daudé wrote:
>
> Currently pflash_cfi01_register():
>
> 1/ creates a TYPE_PFLASH_CFI01 qdev instance
> 2/ maps the first MMIO region to the system bus
>
> The first minor issue is the implicit sysbus mapping is not
> obvious (the function name
On Thu, Jan 5, 2023 at 6:37 AM Philippe Mathieu-Daudé wrote:
>
> Nothing here requires access to PFlashCFI01 internal fields:
> use the inherited generic DeviceState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/xtensa/xtfpga.c | 8
> 1 file changed, 4 insertions(+), 4
On Thu, Jan 5, 2023 at 6:53 AM Philippe Mathieu-Daudé wrote:
>
> Nothing here requires access to PFlashCFI01 internal fields:
> use the inherited generic DeviceState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/pc_sysfw.c | 14 +++---
> include/hw/i386/pc.h | 3 +--
> 2
On Thu, Jan 5, 2023 at 6:47 AM Philippe Mathieu-Daudé wrote:
>
> Nothing here requires access to PFlashCFI01 internal fields:
> use the inherited generic DeviceState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/riscv/virt.c | 9 +
> include/hw/riscv/virt.h | 3 +--
> 2
On Thu, Jan 5, 2023 at 6:35 AM Philippe Mathieu-Daudé wrote:
>
> Nothing here requires access to PFlashCFI01 internal fields:
> use the inherited generic DeviceState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/sbsa-ref.c | 12 ++--
> hw/arm/vexpress.c | 12
On Thu, Jan 5, 2023 at 6:16 AM Philippe Mathieu-Daudé wrote:
>
> Nothing here requires access to PFlashCFI01 internal fields:
> use the inherited generic DeviceState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/loongarch/virt.c | 9 -
> include/hw/loongarch/virt.h | 3
On Thu, Jan 5, 2023 at 6:39 AM Philippe Mathieu-Daudé wrote:
>
> The point of a getter() function is to not expose the structure
> internal fields. Otherwise callers could simply access the
> PFlashCFI01::mem field.
>
> Have the callers pass a DeviceState* argument. The QOM
> type check is done
On Thu, Jan 5, 2023 at 6:10 AM Philippe Mathieu-Daudé wrote:
>
> By using pflash_cfi01_get_blk(), pflash_cfi01_legacy_drive()
> doesn't require any knowledge of the PFlashCFI01 structure.
> Thus we can pass a generic DeviceState pointer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On Thu, Jan 5, 2023 at 6:40 AM Philippe Mathieu-Daudé wrote:
>
> The point of a getter() function is to not expose the structure
> internal fields. Otherwise callers could simply access the
> PFlashCFI01::blk field.
>
> Have the callers pass a DeviceState* argument. The QOM
> type check is done
On Fri, Dec 30, 2022 at 2:20 AM Saleem Abdulrasool wrote:
>
> From: Saleem Abdulrasool
>
> Setting the rounding mode via the `gen_set_rm` call would alter the
> state of the disassembler, resetting the `TransOp` in the assembler
> context. When we subsequently set the rounding mode to the
On Mon, Jan 2, 2023 at 7:55 PM Daniel Henrique Barboza
wrote:
>
> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
> the same steps when '-kernel' is used:
>
> - execute load_kernel()
> - load init_rd()
> - write kernel_cmdline
>
> Let's fold everything inside
On Mon, Jan 2, 2023 at 7:54 PM Daniel Henrique Barboza
wrote:
>
> riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works
> under the assumption that a 'filename' parameter is always not NULL.
>
> This is currently the case since all callers of these functions are
> checking for
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-Id: <20221112042555.2622152-2-richard.hender...@linaro.org>
---
target/arm/helper-a64.h| 6 ---
target/arm/helper-a64.c| 104 -
target/arm/translate-a64.c | 60
From: Ilya Leoshkevich
Add a basic test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
Message-Id: <2022110300.2539919-1-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
tests/tcg/s390x/div.c | 40 +
We expect the backend to require register pairs in
host-endian ordering, thus for big-endian the first
register of a pair contains the high part.
We were forcing R0 to contain the low part for calls.
Signed-off-by: Richard Henderson
---
tcg/tci.c | 21 +++--
1 file changed, 11
Acked-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 2 +-
target/s390x/tcg/mem_helper.c | 7 +++
target/s390x/tcg/translate.c | 7 +--
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
v2: Fix SPEC_in1_x1.
---
target/s390x/helper.h| 32 ++--
target/s390x/tcg/insn-data.h.inc | 30 +--
target/s390x/tcg/fpu_helper.c| 88 ++--
target/s390x/tcg/translate.c | 76
Acked-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 2 +-
target/s390x/tcg/mem_helper.c | 7 +++
target/s390x/tcg/translate.c | 6 --
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git
Fill in the parameters for libffi for Int128.
Adjust the interpreter to allow for 16-byte return values.
Adjust tcg_out_call to record the return value length.
Call parameters are no longer all the same size, so we
cannot reuse the same call_slots array for every function.
Compute it each time
Use tcg_gen_atomic_cmpxchg_i64 for the atomic case,
and tcg_gen_nonatomic_cmpxchg_i64 otherwise.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 2 --
target/i386/tcg/mem_helper.c | 57
target/i386/tcg/translate.c | 54
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Remove extraneous return_low128.
---
target/s390x/helper.h| 22 +++---
target/s390x/tcg/insn-data.h.inc | 20 ++---
target/s390x/tcg/fpu_helper.c| 29 +-
These are not yet considering atomicity of the 16-byte value;
this is a direct replacement for the current target code which
uses a pair of 8-byte operations.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 10 +++
include/tcg/tcg-op.h| 2 +
accel/tcg/cputlb.c | 112
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 48 -
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7e0b2a709a..a82131d635 100644
---
Signed-off-by: Richard Henderson
---
target/s390x/helper.h| 2 --
target/s390x/tcg/insn-data.h.inc | 2 +-
target/s390x/tcg/mem_helper.c| 52 ---
target/s390x/tcg/translate.c | 60
4 files changed, 38 insertions(+),
Make a copy of wout_x1 before modifying it, as wout_x1_P
emphasizing that it operates on the out/out2 pair. The insns
that use x1_P are data movement that will not change to Int128.
Acked-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
target/s390x/tcg/insn-data.h.inc | 12
Replace the flat array tcg_target_call_oarg_regs[] with
a function call including the TCGCallReturnKind.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 9 ++---
tcg/aarch64/tcg-target.c.inc | 10 +++---
Many hosts pass and return 128-bit quantities like sequential
64-bit quantities. Treat this just like we currently break
down 64-bit quantities for a 32-bit host.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 37 +
1 file changed, 33 insertions(+), 4
From: Ilya Leoshkevich
Add a basic test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
Message-Id: <20221025213008.2209006-2-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
tests/tcg/s390x/clst.c | 82 +
Note that the previous direct reference to reserve_val,
- tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
-? offsetof(CPUPPCState, reserve_val2)
-: offsetof(CPUPPCState, reserve_val)));
was incorrect because all references should have
Pack the quotient and remainder into a single uint64_t.
Signed-off-by: Richard Henderson
---
v2: Fix operand ordering; use tcg_extr32_i64.
---
target/s390x/helper.h | 2 +-
target/s390x/tcg/int_helper.c | 26 +-
target/s390x/tcg/translate.c | 8
3
Use tcg_gen_atomic_cmpxchg_i128 for the atomic case,
and tcg_gen_qemu_ld/st_i128 otherwise.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 4 ---
target/i386/tcg/mem_helper.c | 69
target/i386/tcg/translate.c | 44
Normally this is automatically handled by the CF_PARALLEL checks
with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special
case of !PREFIX_LOCK where it always wants the non-atomic version.
Split these out so that x86 does not have to roll its own.
Signed-off-by: Richard Henderson
---
This will allow targets to avoid rolling their own.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 11 +
include/tcg/tcg-op.h | 5 +++
tcg/tcg-op.c | 85 +++
accel/tcg/atomic_common.c.inc | 45
This will be used by _WIN64 to return i128. Not yet used,
because allocation is not yet enabled.
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 1 +
tcg/tcg.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
When allocating a temp to the stack frame, consider the
base type and allocate all parts at once.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 99e6e4e1a8..7e69e2c9fd
Fill in the parameters for the host ABI for Int128 for
those backends which require no extra modification.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/loongarch64/tcg-target.h | 2 ++
Fill in the parameters for the host ABI for Int128.
Adjust tcg_target_call_oarg_reg for _WIN64, and
tcg_out_call for i386 sysv. Allow TCG_TYPE_V128
stores without AVX enabled.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 10 ++
tcg/i386/tcg-target.c.inc | 30
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-Id: <20221112042555.2622152-3-richard.hender...@linaro.org>
---
target/arm/helper-a64.h| 2 --
target/arm/helper-a64.c| 43 ---
target/arm/translate-a64.c | 61
These will be used by some hosts, both 32 and 64-bit, to pass and
return i128. Not yet used, because allocation is not yet enabled.
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 3 +
tcg/tcg.c | 135 -
2 files changed, 135
Acked-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tests/tcg/s390x/long-double.c | 24
tests/tcg/s390x/Makefile.target | 1 +
2 files changed, 25 insertions(+)
create mode 100644 tests/tcg/s390x/long-double.c
diff
Begin staging in support for TCGv_i128 with Int128.
Define the type enumerator, the typedef, and the
helper-head.h macros.
This cannot yet be used, because you can't allocate
temporaries of this new type.
Signed-off-by: Richard Henderson
---
include/exec/helper-head.h | 7 +++
Changes for v4:
* About half of the v3 series has been merged,
* AArch64 host requires even argument register.
* target/{arm,ppc,s390x,i386} uses included here.
Patches requiring review:
01-tcg-Define-TCG_TYPE_I128-and-related-helper-macro.patch
Add code generation functions for data movement between
TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract).
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 4
tcg/tcg-internal.h | 13 +
tcg/tcg-op.c | 20
3 files changed, 37
This case is trivial to implement inline.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 0dafa27dab..b8cb21c395 100644
--- a/target/s390x/tcg/translate.c
Pack the quotient and remainder into a single Int128.
Use the divu128 primitive to remove the cpu_abort on
32-bit hosts.
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
v2: Extended div test case to cover these insns.
---
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 2 +-
target/s390x/tcg/mem_helper.c | 11 ---
target/s390x/tcg/translate.c | 8 ++--
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git
Implement the function for arm, i386, and s390x, which will use it.
Add stubs for all other backends.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 2 ++
tcg/aarch64/tcg-target.c.inc | 7 +++
tcg/arm/tcg-target.c.inc
This enables allocation of i128. The type is not yet
usable, as we have not yet added data movement ops.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 32 +
tcg/tcg.c | 60 +--
2 files changed, 74
We are about to allow passing Int128 to/from tcg helper functions,
but libffi doesn't support __int128_t, so use the structure.
In order for atomic128.h to continue working, we must provide
a mechanism to frob between real __int128_t and the structure.
Provide a new union, Int128Alias, for this.
Hi!
I am experimenting with post-copy by modifying qemu-6.0.0 in my research.
I transfer a VM between two machines but it fails most of the time with
these error messages.
```
qemu-system-x86_64: postcopy_ram_listen_thread: loadvm failed: -5
qemu-system-x86_64: error while loading state for
Thank you for your reply.
My first patch is already merged as a commit
75ac231c67cdb13f0609943fab5499963858b587 by Paolo.
But it seems my second patch isn't merged yet.
If Paolo or someone else plans to merge it, it's no problem.
This is just a ping to the second patch. Not a new fix.
-
On 05/01/2023 14:41, Philippe Mathieu-Daudé wrote:
No need to document magic values when the definition names
from "standard-headers/linux/pci_regs.h" are self-explicit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/grackle.c | 2 +-
hw/pci-host/raven.c| 6 +++---
On 05/01/2023 14:31, Bernhard Beschow wrote:
This series consolidates the implementations of the PIIX3 and PIIX4 south
bridges and is an extended version of [1]. The motivation is to share as much
code as possible and to bring both device models to feature parity such that
perhaps PIIX4 can
On 05/01/2023 14:32, Bernhard Beschow wrote:
Now that PIIX4 also uses the "proxy-pic", both implementations
Should "proxy-pic" be replaced with "isa-pic" (or even TYPE_ISA_PIC) here?
can share the same struct.
Signed-off-by: Bernhard Beschow
Reviewed-by: Michael S. Tsirkin
Message-Id:
On 05/01/2023 14:32, Bernhard Beschow wrote:
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines. PIIX3 doesn't expose such intterupt lines
typo here: s/intterupt/interrupt/
either, so remove them for PIIX4 for simplicity and consistency.
On 05/01/2023 14:32, Bernhard Beschow wrote:
Having an i8259 proxy allows for ISA PICs to be created and wired up in
southbridges. This is especially interesting for PIIX3 for two reasons:
First, the southbridge doesn't need to care about the virtualization
technology used (KVM, TCG, Xen) due
On 05/01/2023 14:32, Bernhard Beschow wrote:
This even spares some casts in hot code paths along the way.
Signed-off-by: Bernhard Beschow
---
Note: The next patch will introduce a class "isa-pic", which is
shall not be confused with the isa_pic singleton.
---
include/hw/intc/i8259.h | 6
On 04/01/2023 18:04, Richard Henderson wrote:
On 1/4/23 05:45, Mark Cave-Ayland wrote:
The FPSR quotient byte should be set to the value of the quotient and not the
result. Manually calculate the quotient in the frem helper in round to nearest
even mode (note this is different from the
On Fri, 6 Jan 2023 at 06:33, Song Gao wrote:
>
> The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
>
> Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into
> staging (2023-01-05 16:59:22 +)
>
> are available in the Git repository at:
>
>
On 7/1/23 19:20, Richard Henderson wrote:
Recently the g_assert(cpu == current_cpu) test has been
intermittently failing with gcc. Reorg the code around
the setjmp to minimize the lifetime of the cpu variable
affected by the setjmp.
This appears to fix the existing issue with clang as well.
Recently the g_assert(cpu == current_cpu) test has been
intermittently failing with gcc. Reorg the code around
the setjmp to minimize the lifetime of the cpu variable
affected by the setjmp.
This appears to fix the existing issue with clang as well.
Resolves:
Use the attribute, which is supported by clang, instead of
the #pragma, which is not supported and, for some reason,
also not detected by the meson probe, so we fail by -Werror.
Include only as that is the outermost "official"
header for these intrinsics -- emmintrin.h and smmintrin.> are
older
On 1/7/23 6:05 AM, Bernhard Beschow wrote:
> Am 7. Januar 2023 01:08:46 UTC schrieb Chuck Zmudzinski :
> >On 1/6/23 6:04 PM, Chuck Zmudzinski wrote:
> >> On 1/6/23 2:08 PM, Chuck Zmudzinski wrote:
> >>> On 1/6/23 7:25 AM, Philippe Mathieu-Daudé wrote:
> On 6/1/23 12:57, Bernhard Beschow
On 1/3/23 20:31, Stefan Hajnoczi wrote:
The other problem with this file is that it appears to
be generated differently depending on the host distro
(specifically the default value for the --libdir option).
That also would seem to nudge towards "don't commit a
generated file".
I wasn't aware
On 1/7/23 02:19, Alex Bennée wrote:
Richard Henderson writes:
On 1/6/23 15:43, Alex Bennée wrote:
What about cloning objects after they are realised? After all that is
what we do for the core CPUClass in user-mode.
No we don't. Where do you get that idea?
Well linux-user does cpu_copy
On Wed, Jan 4, 2023 at 6:54 AM Arthur Sengileyev
wrote:
>
> It should be possible to reuse cache built by previous iteration
> processing next executables. Already processed dependencies are
s/processing/to process
> already skipped later based on dll name.
>
> Signed-off-by: Arthur Sengileyev
On 7/1/23 14:32, Paolo Bonzini wrote:
configure uses "pkg-config" directly so that GLIB_VERSION is always based
on host glib version. To correctly handle cross-compilation it should use
"$pkg_config" and take GLIB_VERSION from the cross-compiled glib.
Reported-by: Валентин
Resolves:
Philippe Mathieu-Daudé writes:
> On non-x86_64 host, if KVM is not available we get:
>
> Traceback (most recent call last):
> File "tests/vm/basevm.py", line 634, in main
> vm = vmcls(args, config=config)
> File "tests/vm/basevm.py", line 104, in __init__
> mem = max(4,
Before this change, e1000e_write_packet_to_guest() allocated the
receive descriptor buffer as an array of uint8_t. This does not ensure
the buffer is sufficiently aligned.
Introduce e1000_rx_desc_union type, a union type of all receive
descriptor types to correct this.
Signed-off-by: Akihiko
On 06/01/2023 10.24, Bin Meng wrote:
On Fri, Jan 6, 2023 at 3:35 AM Thomas Huth wrote:
On 05/01/2023 09.34, Thomas Huth wrote:
On 04/01/2023 23.01, Peter Maydell wrote:
On Wed, 4 Jan 2023 at 12:36, Thomas Huth wrote:
The windows jobs (especially the 32-bit job) recently started to
hit
On Fri, 6 Jan 2023 at 08:29, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
>
> .gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2
> jobs (2023-01-04 18:58:33 +)
>
> are available in the Git
Exceptions caused by IDT accesses have the interrupt number in bits 3:10 of
the error code. When in long mode an IDT descriptor is 16 bytes in size,
and due to a copy-and-paste mistake the multiplication by 8 (shift by 3)
was changed to a multiplication by 16 even in the computation of the
error
configure uses "pkg-config" directly so that GLIB_VERSION is always based
on host glib version. To correctly handle cross-compilation it should use
"$pkg_config" and take GLIB_VERSION from the cross-compiled glib.
Reported-by: Валентин
Resolves:
The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging
(2023-01-05 16:59:22 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 20 ---
.../ci/org.centos/stream/8/x86_64/configure | 2 +-
2 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/configure b/configure
index
On Fri, 6 Jan 2023 at 22:28, Richard Henderson
wrote:
>
> On 1/6/23 13:59, Peter Maydell wrote:
> > We also set some properties in code -- eg aspeed_ast2600.c clears
> > the 'neon' property on its CPUs, lots of the boards clear
> > has_el3 and has_el2, etc.
>
> Yes indeed, but in all of those
On Fri, 6 Jan 2023 at 03:19, Alistair Francis
wrote:
>
> From: Alistair Francis
>
> The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
>
> Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into
> staging (2023-01-05 16:59:22 +)
>
> are available in
Am 7. Januar 2023 01:08:46 UTC schrieb Chuck Zmudzinski :
>On 1/6/23 6:04 PM, Chuck Zmudzinski wrote:
>> On 1/6/23 2:08 PM, Chuck Zmudzinski wrote:
>>> On 1/6/23 7:25 AM, Philippe Mathieu-Daudé wrote:
On 6/1/23 12:57, Bernhard Beschow wrote:
>
>
> Am 4. Januar 2023 15:35:33
Am 6. Januar 2023 17:35:18 UTC schrieb David Woodhouse :
>On Wed, 2023-01-04 at 15:44 +0100, Bernhard Beschow wrote:
>> + if (xen_enabled()) {
>
>Could this perhaps be if (xen_mode != XEN_DISABLED) once we merge the
>Xen-on-KVM series?
It's the same condition which selected
Richard Henderson writes:
> On 1/6/23 15:43, Alex Bennée wrote:
>> What about cloning objects after they are realised? After all that is
>> what we do for the core CPUClass in user-mode.
>
> No we don't. Where do you get that idea?
Well linux-user does cpu_copy which involves a create step
TaiseiIto writes:
> This is a ping to the patch below.
>
> https://patchew.org/QEMU/ty0pr0101mb42855925d8414e4773d6fa36a4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
>
> Before this commit, when GDB attached an OS working on QEMU, order of FPU
> stack registers printed by GDB command
Drop support for sequential OR and XOR, as the serial dependency is
slower than loading the constant first. Let the register allocator
handle such immediates by matching only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
The new select instruction provides two separate register inputs,
whereas the old load-on-condition instruction overlaps one of the
register inputs with the destination.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 15 +++
1 file
Give 64-bit comparison second operand a signed 33-bit immediate.
This is the smallest superset of uint32_t and int32_t, as used
by CLGFI and CGFI respectively. The rest of the 33-bit space
can be loaded into TCG_TMP0. Drop use of the constant pool.
Reviewed-by: Ilya Leoshkevich
Signed-off-by:
There is an older form that produces per-byte results,
and a newer form that produces per-register results.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 4 ++--
tcg/s390x/tcg-target.c.inc | 36
2 files
The fast-bcr-serialization facility is bundled into facility 45,
along with load-on-condition. We are checking this at startup.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 1 -
tcg/s390x/tcg-target.c.inc | 3 ++-
2 files changed, 2
The general-instruction-extension facility was introduced in z10,
which itself was end-of-life in 2019.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 10 ++--
tcg/s390x/tcg-target.c.inc | 100 -
2 files
Add one instead of dropping odd addresses to the constant pool.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc
The distinct-operands facility is bundled into facility 45,
along with load-on-condition. We are checking this at startup.
Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there
is no space savings for avoiding the distinct-operands insn.
Reviewed-by: Ilya Leoshkevich
Signed-off-by:
Reuse code from movcond to conditionally copy a2 to dest,
based on the condition codes produced by FLOGR.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.c.inc | 20 +++-
2 files changed, 12
There are multiple variations, with different fields.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 47 +-
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc
The general-instruction-extension facility was introduced in z196,
which itself was end-of-life in 2021. In addition, z196 is the
minimum CPU supported by our set of supported operating systems:
RHEL 7 (z196), SLES 12 (z196) and Ubuntu 16.04 (zEC12).
Check for facility number 45, which will be
Return both regular and inverted condition codes from tgen_cmp2.
This lets us choose after the fact which comparision we want.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 19 ---
1 file changed, 16 insertions(+), 3
Generalize movcond to support pre-computed conditions, and the same
set of arguments at all times. This will be assumed by a following
patch, which needs to reuse tgen_movcond_int.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 3 +-
The MIE2 facility adds 3-operand versions of multiply.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 1 +
tcg/s390x/tcg-target.c.inc | 34 --
3 files changed, 26
98 matches
Mail list logo
